JPH0521812A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the malfunction of an nonselected memory cell by voltage stress by applying constant voltage above earth voltage and below power source voltage to the erasing gate of the memory cell at the time of writing. CONSTITUTION:The voltage independent of the power supply voltage VCC within the range of 0<VEG<VCC is applied to the erasing (erase) gate EG of a memory cell M, at the time of data writing (at programing). Hereby, the voltage between the erase gate EG and a floating gate FG and the electric field between the floating gate FG and the source are weakened. Therefore, at programming, in a nonselected cell M (B), the injection of electrons from the erase gate EG or a channel (substrate) to the floating gate FG and the discharge of electrons from the floating FG to the erase gate EG become hard to occur. In short, the mal function in the nonselected memory cell M (B) at the time of writing is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory in which data can be electrically programmed, and more particularly, to prevent malfunction due to voltage stress of non-selected cells to improve reliability. is there.

[0002]

2. Description of the Related Art EEPROM (Electrically Erasa) capable of electrically erasing and rewriting stored data.
ble and Programmable ROM) allows data to be erased and programmed by electrical signals while it is still installed on the board. Therefore, it is easier to use than an ultraviolet erasable EPROM. For this reason, demand for control, IC cards (memory cards), etc. is rapidly increasing. Further, in an EEPROM capable of realizing a particularly large capacity, for example, as can be seen from FIG. 5, a nonvolatile transistor having a three-layer polycrystalline silicon structure including a floating gate FG, a control gate CG, and an erase gate EG is a memory cell M. Is used as. Then, such memory cells are arranged in a matrix to form a memory cell array MA. Then, at the time of erasing data, a positive high voltage is applied to the erase gate EG. As a result, the electrons accumulated in the floating gate FG in advance are released to the erase gate EG, and the data is erased. Further, at the time of writing data, high voltage is applied to the control gate CG and the drain D of the selected memory cell M, respectively. As a result, electrons are injected into the floating gate FG.

In the conventional EEPROM, the erase gate voltage is usually set to 0 V or V _CC when writing data. Therefore, the voltage stress in the floating gate of the non-selected memory cell becomes large at the time of writing data. As a result, the electric field strength to the erase gate and the electric field strength to the channel seen from the floating gate become large, and electrons are injected (wrong write) from the erase gate or substrate to the floating gate, or electrons escape from the floating gate to the erase gate. There is a problem that a malfunction such as (erroneous deletion) occurs.

The voltage stress of the non-selected memory cell will be described in more detail below while explaining the basic operation of the pattern plan view of the cell and the equivalent circuit formula.

FIG. 6A is a pattern plan view of a memory cell, FIG. 6B is a sectional view taken along the line AA 'in FIG. 6A, and FIG. It is a BB 'sectional view taken on the line a). In FIG. 6, 11 is a floating gate made of the first-layer polycrystalline silicon layer, 12 is an erase gate made of the second-layer polycrystalline silicon layer, and 13 is a control made of the third-layer polycrystalline silicon layer. It is a gate. Control gate 13
Is also used as the word line of the memory cell. Also, 1
Reference numeral 4 is a p-type substrate, 15 and 16 are sources and drains formed of an n ⁺ -type diffusion layer formed on the substrate 14, 17 is a contact hole, and 18 is a drain and the drain 16 via the contact hole 17. It is a data line made of an aluminum layer to be connected. Further, 19 is a gate insulating film of the floating gate transistor portion, 20 is a gate insulating film provided between the floating gate 11 and the erase gate 12, and 21 is a gate provided between the floating gate 11 and the control gate 13. It is an insulating film. The gate insulating film 21 is composed of a three-layer structure film having an O-N-O structure (Oxide-Nitride-Oxide). Reference numeral 22 is a gate insulating film provided between the erase gate 12 and the control gate 13, which also has an ONO structure. Reference numeral 23 is a gate insulating film of the select transistor portion using the third-layer polycrystalline silicon layer as a gate electrode. Further, 24 is a field insulating film, and 25 is an interlayer insulating film.

Next, the basic operation of the memory cell having such a structure will be described. As can be seen from FIG. 5, when writing data, a high voltage, for example + 8V, is applied to the drain 16.
The source 15 is 0 V, the control gate 13 is a positive high voltage, for example 12 V, and the erase gate is a power supply voltage, for example 5 V.
Are applied respectively. This allows
The hot electron effect occurs near the drain, electrons generated by impact ionization are injected into the floating gate, and the floating gate 11 is negatively charged. As a result, the threshold voltage of this memory cell becomes high. This state is data "0".

Data is erased from the memory cell in which the data "0" is written by the above write operation as follows. First, 0 V is applied to the source 15 and drain 16 and the control gate 13 of the memory cell in which electrons have been injected into the floating gate 11, and a positive high voltage, for example, +21 V is applied to the erase gate 12. At this time,
Due to the Fowler-Nordheim tunnel effect, electrons in the floating gate are emitted to the erase gate by field emission, and the floating gate 11 is positively charged. As a result, the threshold voltage of this memory cell becomes low. This state is data "1".

FIG. 7 shows an equivalent circuit of the memory cell shown in FIGS. 6A to 6C, and FIG. 8 shows an equivalent circuit of a capacity system. In FIG. 7, V _D is the drain voltage, V
_S is a source voltage, V _FG is a floating gate voltage, V _EG is an erase gate voltage, and V _CG is a control gate voltage. Further, in FIG. 8, C _FC is the capacitance between the floating gate 11 and the control gate 13, C _FE is the capacitance between the floating gate 11 and the erase gate 12, and C _FD is the floating gate 11 and the drain 16. , C _FS is the other capacitance seen from the floating gate 11.

The memory cells as described above are arranged in a matrix in an actual memory. Here, in order to simplify the explanation, consider a 4-bit memory cell array MA as shown in FIG. That is, FIG. 5 shows four memory cells M
FIG. 3 is a circuit diagram of a memory cell array including (A) to M (D). The drains D of these four memory cells M are connected to one of the two data lines DL1 and DL2, the control gate CG is connected to one of the two word lines WL1 and WL2, and all the memory cells are connected. The erase gate EG of M is commonly connected to the erase line EL, the source S has a reference voltage,
For example, 0V is applied.

In the memory cell array MA having such a configuration, a case will be described in which one memory cell is selected and data is written. Now, assume that data “0” is written in the memory cell M (A), for example. At this time, a high voltage of + 8V is applied to the data line DL1 and a high voltage of + 12V is applied to the word line WL1. At this time, the other data lines DL2 and word lines WL2 are set to 0V, respectively. In this state, the memory cells M (B) to M (D) are not selected and writing is not performed. However, in the non-selected memory cells M (B) to M (D), a voltage of 0 V or more is applied to the drain or the control gate and the erase gate. As a result, unselected memory cells M (B) to
At M (D), voltage stress is applied to the floating gate. Next, try to find this voltage stress.

In FIG. 8, the initial value Q (I) of the amount of charge stored in all capacitors is given by the following equation.

Q (I) = (V _FG −V _CG ) · C _FC + (V _FG −V _EG ) · C _FE + (V _FG −V _D ) · C _FD + (V _FG −V _S ) · C _FS (1) Further, when the total sum of all capacities in FIG. 8 is C _T , C _T
Is given by

C _T = C _FC + C _FE + C _FD + C _FS (2) Therefore, the voltage V _FG applied to the floating gate is given by the following equation.

V _FG = {(V _CG · C _FC + V _EG · C _FE + V _D · C _FD + V _S · C _FS ) / C _T } + {Q (I) / C _T } ... (3) where , Q (I) / C _T = V _FG (I), and V _S = 0V, the above equation 3 can be rewritten as follows.

V _FG = {(V _CG · C _FC + V _EG · C _FE + V _D · C _FD ) / C _T } + V _FG (I) (4) Here, the value of each capacitance is as follows. Given by the formula.

C _FC = (ε _ox · S _C ) / t _ox1 (5) C _FE = (ε _ox · S _E ) / t _ox2 (6) C _FD = (ε _ox · S _D ) / _{t ox3 ...... (7) C FS} = {(ε ox · S S) / t ox3} + {(ε ox · S F) / t ox4} ...... (8) However, S _C is a floating gate and a control gate Facing area,
t _ox1 is the film thickness of the insulating film 21 existing between them, S _E
Is the facing area between the floating gate 11 and the erase gate 12, t
_ox2 is the thickness of the insulating film 20 existing therebetween, S _D is the facing area between the floating gate 11 and the drain 16, t _ox3 is the thickness of the insulating film 19 existing between them, S _S is the floating gate 11 opposing area between the source 15 and channel, S _F
Is the facing area between the floating gate 11 and the field insulating film 24, _tox4 is the film thickness of the field insulating film 24, and ε _ox is the dielectric constant of the insulating film.

Here, in FIG. 6, the insulating films are
t _ox1 = 680 Å, t _ox2 = 370 Å, t _ox3 = 280 Å, t
_ox4 = 8000 angstroms,
^{_{S C = 1.4mm 2, S E}} = 0.42mm 2, S D = 0.3
mm ^2, and ^{_{S S = 0.4mm 2, S F}} = 1.12mm 2, the depth of the diffusion layer, and x _j = 0.3μm.

The malfunctions of the non-selected memory cells M (B) to M (D) at the time of writing data are shown below in Table 1.
Will be described in detail based on. However, Table 1 and Table 2 show V _EG
2 shows the gate voltage and the voltage stress applied to the floating gate of the selected cell and the non-selected cell when V is set to 0 V and 5 V, respectively, based on the equivalent circuit formula.

[0019] _{Table 1 (EG = 5V) FG-} EG _{between FG- source} memory cell _{V CG V EG V D V S} V FG _{potential difference (V) potential (V) V EG -V FG V} S -V FG _A "1" _{12 5 8 0} 9.68 -4.68 -9.68 "0" 3.68 1.32 -3.68 _B "1" _{12 5 0 0} 8.21 3.21 -8.21 "0" 2.91 2.79 -2.91 _C "1" _{0 5 8 0} 5.44 -0.44 (C) -5.44 "0" -0.56 5.56 0.56 _D "1" _{0 5 0 0} 3.97 1.03 -3.97 "0" -2.03 (D) 7.03 2.03 _{Table 2 (EG = 0V) FG-EG} memory _FG-source memory cell _{V CG V EG V D V S} V FG _{potential difference (V) potential (V) V EG -V FG V} S -V FG _A "1" _{12 0 8 0} 8.71 -8.71 -8.71 "0" 2.71 -2.71 -2.71 _B "1" _{12 0 0 0} 7.24 (B) -7.24 -7.24 "0" 1.24 -1.24 -1.24 _C "1" _{0 0 8 0} 4.47 -4.47 -4.47 "0" -1.53 1.53 1.53 _D "1" _{0 0 0 0} 3 -3 -3 "0" -3 3 3 In the unselected memory cell M (B) in the "1" state, When the erase gate voltage is low (for example, V _EG = 0V), a voltage of −7.24V is applied between the erase gate and the floating gate. At the time of erasing, in the selected memory cell M, the erase gate is +
A voltage of 10.3V is applied. That is, the memory cell M
In (B), the same voltage is applied as the reverse voltage during erase. Therefore, electrons are injected from the erase gate to the floating gate due to the tunnel effect, resulting in erroneous writing.

Further, the non-selected memory cell M in the "1" state
In (C), when the potential of the erase gate is high (for example, V _EG = 5.0V), a potential difference of −5.44V is generated between the floating gate and the source. This causes erroneous writing.

At this time, in particular, the selected memory cell M
The occurrence rate of erroneous writing is high in cells close to (A). This will be described in detail below.

When writing the selected memory cell M (A),
In the vicinity of the drain, the concentration of electric field accelerates the electrons, creating high-energy electron hole pairs. The holes generated by this are the memory cells M (A)
Raise the substrate potential in the vicinity. As a result, the threshold V _th in the cells near the memory cell M (A) (for example, the cells M (C) adjacent to each other on the same data line) is lowered.
Therefore, a minute cell current flows, and as described above, electrons are injected into the floating gate due to the electric field between the substrate and the floating gate, resulting in erroneous writing.
Furthermore, the same state as the memory cell M (C) (V _EG = 5.0
V, V _CG = 0V, V _D = 8V, V _S = 0V, 1 state), that is, unselected cells on the same data line, which are close to the selected cell, are apt to be erroneously written. is there.

In the memory cell M (D) in the "0" state, if the erase gate is high, for example, V _EG = 5.0V.
Then, between the erase gate and the floating gate, 7.
A voltage of 03V is applied. Due to this electric field, electrons are emitted from the floating gate to the erase gate, causing erroneous erasing.

In the above Tables 1 and 2, (B),
(C), (D), respectively, each potential difference, (B) = V _EG stress causing erroneous writing in the memory cell B (C) = V _EG stress causing erroneous writing of the memory cell C (D) = Memoriru It is V _EG stress that causes erroneous erasure of D.

[0025]

In the above conventional circuit,
V _EG = V _CC = 5.0V is set. In this case,
As described above, erroneous writing occurs in the memory cell M (C), and erroneous erasing occurs in the memory cell M (D). This erase gate voltage has V _CC dependency, and
_{When CC} becomes higher than 5.0V, the memory cell M
Erroneous writing and erasing in (C) and M (D) become worse. For example, in the EP compatible mode used in a program with a ROM writer, V _CC = 6.0V to 6.5
In the command mode corresponding to V, onboard, V _CC = 4.
It is 5V to 5.5V. At this time, in the memory cell M (D) in the “0” state, the voltage threshold, which is the potential difference between the floating gate and the erase gate depending on the mode, reaches 1.6 V at maximum. Further, when V _EG = 0V, erroneous writing and erasing are suppressed in the memory cells M (C) and M (D). However, as described above, the memory cell M (B)
Then, the voltage of the floating gate becomes higher than that of the erase gate, and erroneous writing occurs.

As described above, the erase gate voltage depends on V _CC , and if the voltage stress is different, it is difficult to optimize both the design and the process for improving the reliability of the memory cell.

As described above, in the memory using the non-volatile transistor having the floating gate, the control gate and the erase gate as the memory cell, the non-selected memory cell is
There is a problem that malfunction occurs due to voltage stress applied to the floating gate.

The present invention has been made in view of the above, and an object thereof is to provide a highly reliable nonvolatile semiconductor memory which prevents malfunction of unselected memory cells due to voltage stress at the time of writing. is there.

[0029]

A first non-volatile semiconductor memory of the present invention is a memory which is a non-volatile transistor having a floating gate, a control gate and an erase gate capacitively coupled to the floating gate, and a source and a drain. A plurality of cells, which are driven by a power supply voltage and a ground voltage, and which are targeted among the memory cells,
And a peripheral circuit for electrically writing, erasing and reading data, the peripheral circuit, when writing,
The memory cell is provided with voltage output means for applying a constant voltage lower than the power supply voltage and higher than the ground voltage to the erase gate of the memory cell.

The second non-volatile semiconductor memory of the present invention is
A plurality of memory cells, which are non-volatile transistors each having a floating gate and a control gate and an erase gate capacitively coupled to the floating gate, and are driven by a power supply voltage and a ground voltage to be a target of the memory cells. A peripheral circuit for electrically writing and erasing data and reading data, the peripheral circuit causing an erroneous write in an unselected cell in the erase gate of the memory cell at the time of the writing. It is configured to include a voltage output unit that applies a constant voltage that relaxes the voltage stress and the voltage stress that causes erroneous erasing to the same degree.

The third nonvolatile semiconductor memory of the present invention is
In the first or second nonvolatile semiconductor memory, the voltage output means is configured to output the constant voltage as being unaffected by a change in the potential of the power supply voltage.

The fourth non-volatile semiconductor memory of the present invention is
In any one of the first to third nonvolatile semiconductor memories, the constant voltage is configured to be a value approximately at the center between the power supply voltage and the ground voltage.

A fifth non-volatile semiconductor memory of the present invention is
In any one of the first to fourth nonvolatile semiconductor memories, the constant voltage is configured to be about 2 to 3V when the power supply voltage is 5V and the ground potential is 0V.

[0034]

When data is written (programmed), a voltage independent of the power supply voltage (V _CC ) within the range of 0 <V _EG <V _CC is applied to the erase (erase) gate of the memory cell. This weakens the voltage between the erase gate and the floating gate and the electric field between the floating gate and the source. Therefore, during programming, in the non-selected cells, injection of electrons from the erase gate or channel (substrate) to the floating gate and emission of electrons from the floating gate to the erase gate are less likely to occur. That is, a malfunction in the non-selected memory cell at the time of writing is prevented.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an overall configuration diagram of the present invention.

The memory cell array MA has a plurality of memory cells (transistors) M. Here, four cells M
Only (A) to M (D) are shown. Each cell M has a drain D, a source S, a floating gate FG, an erase gate EG, and a control gate CG. These cells operate similar to those shown in FIG. The word line WL connected to the memory cell array MA is selected by the row decoder RD. That is, row address A
_R is decoded by the row decoder RD and one word line WL is selected. The data line DL has a column address A
_C is decoded by the column decoder CD and selected. In the program mode, write data D _in
Are transmitted to the selected data line DL via the data input circuit DI. At the time of reading, the data read to the data line DL is output as output data D _out via the data output circuit DO. During erase (erase), the erase voltage V _EG from the erase voltage output circuit EVB
Is added to the erase gate EG of each cell M, and the data is erased all together.

More specifically, the erase voltage output circuit EVB has address decoder signals ERA and ERB, a program state and erase state signal HD, and an erase state signal E.
OSC is added. By applying these signals, the erasing voltage output circuit EVB outputs a high voltage for erasing (eg, 21V) during erasing, a low voltage (eg, 0V) during reading and standby, and 0V during programming.
Between the power supply voltage and the power supply voltage V _CC (eg 5V) (eg 3V)
Or 2V) is output.

2 to 4 show different embodiments of the erase voltage output circuit EVB of FIG. 1 which operates as described above. The circuits of FIGS. 2 to 4 will be described step by step.

First, referring to FIG. 2, this output circuit EVB
Includes a booster circuit 101, a voltage relaxation circuit 102, and a block decoder 103. The booster circuit 101 has N-channel transistors T1 to T8.
1, T4 are D type (V _th <0), and T2, T3
T6 and T7 are E type (V _th > 0), and T5 and T8
Is an I type (V _th = nearly 0 V). Voltage relaxation circuit 1
02 has transistors TA to TC, which are N-channel and D-type. The block decoder 103
The transistors T9 to T16 are provided, and T9 to T11 and T1.
6 is an N channel and is an E type, and T12 to T15 are P channels.

In the booster circuit 101, the signal EOSC is a 0-V _CC transmission signal only when erasing, and 0 V when not erasing.
Becomes The signals ERA and ERB are block decoder signals. Signal HD is "1" during programming and erasing
The other signals are "0".

In FIG. 2, V _SS is applied to the gate of the transistor TA, and the threshold voltage | V of the D-type transistor TA is used as the output voltage V _EG during programming.
_enabled to output _th |.

Table 3 shows input / output signals in each mode in FIG. This table is a summary of selected blocks of the input signals ERA = "1" and ERB = "1" to the block decoder 103. As can be seen from this table, since EOSC = "L" during programming, the booster circuit 101
Is off. Therefore, the output terminal HE is not charged from the booster circuit 101 side. However, because HD = "H",
V _CC is supplied from the block decoder 103 side. At this time, the D type transistor TA is in the ON state with V _SS applied to its gate, and the D type transistors TB and TC are also ON. Therefore, | V _th | of the D-type transistor TA is output as the output V _EG .
As a result, the voltage V _EG input to the erase gate of the memory cell becomes independent of V _CC . At the time of erase, EOSC is in an oscillating state, the output of the block decoder 103 is also "1", and the booster circuit 101 is operating. Therefore, 21 V is output as the output V _EG . At this time,
The voltage relaxation transistors TA to TC gradually reduce the voltage to prevent the high voltage from being applied to the block decoder 103. HD during reading and standby
== “L”, the output terminal HE is discharged by the transistor T16, and the output voltage V _EG = 0V. EOSC =
It is “0”, and the booster circuit 101 is also off.

[0043]   Table 3 (Fig. 2)     Mode REB HD Boost circuit Node a Node V_b  Output V_EG      Program L H Off L H 3V   Erase L H on L H 21V   Lead L L Off H L 0V   Standby L L Off H L 0V            Table 4 (Figure 4)           Mode NErase HD NProg Booster circuit V_b  Output V_EG                  Program H H L Off 2V 2V         Erase L H H on 5V 21V         Lead H L H Off 0V 0V         Standby H L H Off 0V 0V            In the circuit of FIG. 2, during programming, the output voltage V_EGIs
Charge from the transistor T15 side of the lock decoder 103
To be done. However, the output terminal HE is set to an arbitrary voltage.
And V_PP= 12V of the connected transistor T7
Input to the gate. Therefore, the charge from the booster circuit is also generated.
I will mess up. By combining these charges, the output terminal HE
The voltage is set. Therefore V_CCIs more than 5.5V
V in the high range_CCDependency occurs. But V_CC=
V within the range of 4.5V to 6.5V_CCLittle dependence,
V_CCThere is no problem in the actual use range of ± 10%.

FIG. 9 shows the output characteristic of the circuit of FIG.

Next, the circuit of FIG. 3 will be described.

The circuit of FIG. 3 is different from the circuit of FIG. 2 in that an E type transistor TD is added to the charging path from the booster circuit 101 side, and E type transistors TE, TF and TG are added to the output of the block decoder 103. There is a point.
The transistors TE and TG are N-channel, and a signal Prog which becomes H level during programming is added. The transistor TF is a P channel, and a signal NProg which becomes L level during programming is added.

These E type transistors TD to TG
Is added to the booster circuit 101 from the output terminal HE.
Current is prevented from flowing to the side. Therefore, the output voltage V _EG having an arbitrary value is not supplied to the gate of the transistor 7. In other words, this eliminates the charging from the ascending circuit 101 side. However, the level of the output terminal HE during erase operation, V _th amount corresponding fallen value of the transistor TD (V _EG
= Becomes V _g -V _th), it becomes V _EG = about 19V.

In the circuit of FIG. 3, the erase gate voltage at the time of programming is determined by the V _th of the transistor TA. Further, this erase gate voltage is set to a voltage value completely independent of V _CC when the voltage value is V _th or higher. FIG. 10 shows the output characteristic of the circuit of FIG.

Next, the circuit of FIG. 4 will be described.

The circuit of FIG. 4 has the same booster circuit 101, voltage relaxation circuit 102, and block decoder 103 as those of FIGS.
In addition to the constant voltage circuit 104, the feedback circuit 105
It is composed by.

The circuit operation in each mode will be described below.

During programming, EOSC = "L" and the booster circuit 101 is off. Further, in the selected state of the block decoder, the node _Vb is charged from T15. At the same time, the constant voltage circuit 104 and the feedback circuit 105 also operate and set the node V _b, that is, the output terminal HE to 0.
The set voltage is set within the range of <V _b <V _CC . Further, the output H of the constant voltage circuit 104 is the I type transistor T24 ...
The voltage is set to the voltage determined by the ratio of T28 and is input to the gate of the I-type transistor T19. Further, at the time of programming, the signal NProg = "L". Therefore, the transfer gate T20 in which two transistors of P channel and N channel are arranged in parallel is turned on. Therefore, the node K is connected to the transistors T17, T18, T1.
The potential becomes 9, which is determined by the ratio of T21, and is input to the gate of the discharge transistor T21. Here, the transistor T18 has a particularly small conductance gm. Furthermore, when node _Vb is still low, node K is not charged either. Therefore, the discharge transistor T21 is in the off state, and the node _Vb is charged from the transistor T15. At this time, the I-type transistor T19 is turned on, but since the conductance gm of the transistor T18 is small, the charge from the transistor T17 is small. Voltage value of V _b by charging from T15 increases, at a _{V b = V a -V th19,} I -type transistors T19 is turned off, the node K is charged from pch transistor T18. That is, the output terminal HE and the node V _b are charged by the transistor T15, the transistors T17, T18, T19, and the transistor T2.
It becomes a set value depending on the balance of the discharge of 1.

At the time of erasing, since the booster circuit 101 is on, the output terminal HE is set to 21V. Signal HD
= “H”, the node V _b is charged to 5V from the transistor T15 on the block decoder 103 side. Here, If there is no transfer gate T20, leakage current is generated through the transistor T19, T22 at node V _b = 5V, the lower the voltage at node V _b, the booster circuit 101 does not operate normally. However, since the transfer gate T20 is provided, the generation of this leak current is suppressed and malfunction is prevented. Further, since NProg = “H” during reading and standby, both the constant voltage circuit 104 and the feedback circuit 105 are off. The booster circuit 101 is also off. At this time,
The transistor T16 is turned on and the output terminal HE is set to 0V.

In the circuit of FIG. 4, the voltage at the output terminal HE is produced by a feedback type circuit to eliminate the instability of the voltage at the output terminal HE due to variations in the threshold _Vth of the transistor due to the process. There is. Further, by making it possible to arbitrarily set the voltage of the output node H of the constant voltage circuit 104, the voltage of the output terminal HE can be finely adjusted, and a stable output terminal HE voltage can be obtained.

Tables 5 and 6 show the voltage stress when V _EG = 2V or 3V is set by the circuits of FIGS. Table 7 shows a comparison of large stresses when V _EG = 0, 5, 2V, and it can be seen that the stress can be reduced on average when the voltage is 2V.

[0056]                             _{Table 5 (V = 2V)}    ^EG   _{Memory cell    V V V V V}  Between FG and EG Between FG and source    ^{CG EG DS FG Potential difference (V) Potential difference (V)}   _A  "1"_{12 2 8 0}    8.10 -6.10 -8.10   "0" 4.10 -2.10 -4.10   _B  "1"_{12 2 0 0}    6.63 -4.63 (B ") -6.63   "0" 2.63 -0.63 -2.63   _C  "1"_{0 2 8 0}    3.86 -1.86 -3.86 (C ")   "0" -0.04 2.04 0.04   _D  "1"_{0 2 0 0}    2.39 -0.39 -2.39   "0" -1.61 3.61 (D ") 1.61                             _{Table 6 (V = 3V)}    ^EG   _{Memory cell    V V V V V}  Between FG and EG Between FG and source    ^{CG EG DS FG Potential difference (V) Potential difference (V)}   _A  "1"_{12 3 8 0}    9.29 -6.29 -9.29   "0" 3.29 -0.29 -3.29   _B  "1"_{12 3 0 0}    7.82 -4.82 (B ') -7.82   "0" 1.82 1.18 -1.82   _C  "1"_{0 3 8 0}    5.05 -2.05 -5.05 (C ')   "0" -1.05 4.05 1.05   _D  "1"_{0 3 0 0}    3.58 -0.58 -3.58   "0" -2.42 5.42 (D ') 2.42     Table 7     _{Memory cell}    V_EG= 0 (V) 5 2 3            _{B "1"} (B) -7.24_{-4.6 (B ") -4 82 (B ')}     (Wrong writing)       _{C "1"}                 (c) -5.44_{-3.86 (C ") -5.05 (C ')}     (Wrong writing)       _{D "0"}                 (D) 7.03_{3.61 (D ") 5.42 (D ')}     (Erase by mistake)   More specifically, the flow of the memory cell M (B) in FIG.
The voltage stress applied to the gate FG is V_EG= 0
When it was V, it was -7.24V. But V_EG= 2V
, This voltage stress is suppressed to -4.63V.
available. Along with this, the floating gate and erase
The electric field E applied between the gate and the gate is E = (V_EG−
V_FG) / T_ox2Is given by the formula. That is, V_EG= 0V
Then, E = 7.24 / 370 angstrom = 1.9
It becomes 6 (MV / cm). On the other hand, V_EG= Set to 2V
When set, E = 4.63 / 370 angstroms
Mu = 1.25 (MV / cm). Similarly, memory cells
The voltage applied to the floating gate FG of M (C)
Res is V_EG= 5.0V, it is -5.44V
It was But V_EGWhen set to = 2V, -3.8V is set.
It can be suppressed to 6V. The electric field at this time is 1.94 MV /
cm becomes 1.38 MV / cm. In addition, the memory cell M
The voltage stress that causes erroneous erasure in (D) is 7.03.
Although it was V, it is suppressed to 3.61V. In other words
In these non-selected cells, the voltage is about half, and the electric field is 30.
The stress can be reduced by as much as 50% to 50%. In this way, each non-selected
Select cell voltage stress, that is, as in the above embodiment,
V is applied to the erase gate when writing data_CCLess than positive polarity
Voltage value of, for example, 2V and V_CCApply independent value
Then, erroneous writing and erasing in unselected memory cells
The last is greatly improved. As a result, trust as memory
It is possible to significantly improve the sex.

Even when V _EG = 3V, V _EG =
The stress can be relieved more than the case of 0V or 5V.
It is clear from Table 7.

[0058]

As described above, according to the present invention, the voltage applied to the erase gate of a non-selected cell at the time of writing is set to a value with which stress is relieved.
It is possible to prevent a non-selected memory cell from malfunctioning due to voltage stress and provide a highly reliable nonvolatile semiconductor memory.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a first specific example of the erase voltage output circuit of FIG.

FIG. 3 shows a second specific example of the erase voltage output circuit of FIG.

FIG. 4 is a third specific example of the erase voltage output circuit of FIG.

FIG. 5 is an example of an array of memory cells.

FIG. 6 is a pattern plan view of a memory cell, a sectional view taken along the line AA ′, and a sectional view taken along the line BB ′.

7 is an equivalent circuit diagram of the cell of FIG.

8 is an equivalent circuit diagram of a capacity system of the cell of FIG.

9 is an output characteristic diagram of the circuit of FIG.

10 is an output characteristic diagram of the circuit shown in FIG.

[Explanation of symbols]

FG Floating gate CG Control gate EG Erase gate S Source D Drain M (A) to M (D) Memory cell V _CC Power supply voltage V _SS Ground voltage EVB Voltage output means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 27/115 8831-4M H01L 27/10 434

Claims (5)

[Claims] 1. A floating gate, a plurality of memory cells which are nonvolatile transistors each having a control gate, an erase gate, and a source and a drain capacitively coupled to the floating gate, and driven by a power supply voltage and a ground voltage, A peripheral circuit for electrically writing, erasing or reading data for a target one of the memory cells, wherein the peripheral circuit has an erase gate of the memory cell at a voltage lower than the power supply voltage at the time of the writing. And a voltage output means for applying a constant voltage equal to or higher than the ground voltage. 2. A plurality of memory cells, which are nonvolatile transistors each having a floating gate and a control gate and an erase gate capacitively coupled to the floating gate, and a plurality of memory cells driven by a power supply voltage and a ground voltage. A peripheral circuit for electrically writing and erasing data as well as reading data for the target one of them, wherein the peripheral circuit, at the time of the writing, is connected to the erase gate of the memory cell 2. A non-volatile semiconductor memory comprising: a voltage output unit that applies a constant voltage that relaxes the voltage stress that causes erroneous writing and the voltage stress that causes erroneous erasing to the same extent. 3. The nonvolatile semiconductor memory according to claim 1, wherein the voltage output means outputs the constant voltage as being unaffected by a change in the potential of the power supply voltage. 4. The nonvolatile semiconductor memory according to claim 1, wherein the constant voltage is a value approximately in the center between the power supply voltage and the ground voltage. 5. The nonvolatile semiconductor memory according to claim 1, wherein the constant voltage is about 2 to 3 V when the power supply voltage is 5 V and the ground potential is 0 V.