JPH05218104A - Charge transfer device - Google Patents

Abstract

PURPOSE:To reduce the capacity of a stray diffused layer and to improve a detecting sensitivity of a signal charge by forming a thicker insulating film than a gate insulating film on a surface of the layer. CONSTITUTION:A p-type impurity diffused layer 3 for isolating an element of an n-type impurity diffused layer 2 of a buried channel region, a thick oxide film 4a, a gate insulating film 5, and first, second gate electrodes 6, 8 made of polycrystalline silicon are formed on a p-type semiconductor substrate 1. Further, a potential barrier p-type diffused layer 9, an output gate electrode 10, an n-type stray diffused layer 11, an n-type drain 12 to be applied by a reset drain voltage, a reset gate electrode 13 and an output transistor 14 for detecting a potential change of the n-type stray diffused layer are formed, and a surface of the layer 11 is covered with a thick insulating film 4b for isolating an element. A capacity of the n-type stray diffused layer is largely reduced as compared with that of prior art, and a detecting sensitivity to be defined by an output voltage to a predetermined signal charge by the transistor 14 is raised.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device,
In particular, the present invention relates to a charge transfer device in which a floating diffusion layer for detecting the transfer charge amount is formed in the output section.

[0002]

2. Description of the Related Art A charge transfer device that stores and transfers information such as incident light and electric signals in the form of electric charges and takes out the electric charges as voltage signals is widely used for applications such as image pickup devices and memory devices.

FIG. 2 is a sectional view showing the vicinity of the output portion of a conventional charge transfer device. This conventional example is an example of a buried channel type two-phase drive type charge transfer device. In the figure, 1 is a p-type semiconductor substrate, 2 is an n-type impurity diffusion layer forming an embedded channel region formed thereon, 3 is a p-type impurity diffusion layer for element isolation, and 4 is a p-type impurity for element isolation. Thick oxide film on the diffusion layer, 5 is a gate insulating film, 6 is a first gate electrode made of polycrystalline silicon, 7 is an insulating film formed on the surface of the first gate electrode, and 8 is made of polycrystalline silicon. A second gate electrode, 9 is a p-type diffusion layer for potential barrier formed under the second gate electrode 8, 10 is an output gate electrode to which a fixed output gate voltage V ₂ is applied, and 11 is a transfer charge amount. An n-type floating diffusion layer formed in the same process as the n-type impurity diffusion layer 2 which is a buried channel region for detection, and 12 is applied with a reset drain voltage V _1.
Type drain diffusion layer, 13 is an n-type floating diffusion layer 11 periodically
Is a reset gate electrode for resetting the potential of V to the reset drain voltage V ₁ , and 14 is an output transistor for detecting a potential change of the n-type floating diffusion layer. Further, each first gate electrode of the charge transfer portion is connected to the second gate electrode on the left side thereof, and φ ₁ and φ are alternately connected to this connection portion.
_The transfer electrode is constructed by applying the clock of ₂ .

Next, the operation of this conventional example will be described. First, a reset pulse is applied to the reset gate electrode 13 to reset the potential of the n-type floating diffusion layer 11 to the reset drain voltage V ₁ . At this time, the clock φ ₁ has a high potential and the clock φ ₂ has a low potential, and the charge is φ ₁
Is stored under the first gate electrode to which is applied. Next, when the potentials of the clock φ ₁ and the clock φ ₂ are reversed,
The charges under the final gate electrode to which the clock φ ₁ is applied pass through the channel under the output gate electrode 10 and flow into the n-type floating diffusion layer 11.

If the charge amount of the signal charges transferred here is Q and the capacitance of the n-type floating diffusion layer is C, the potential change ΔV of the n-type floating diffusion layer before and after the charge flows is ΔV. = Q / C. Then, this potential change is taken out through the output transistor 12.

[0006]

In the above charge transfer device, the magnitude of the output signal with respect to the signal charge is determined by the capacitance of the floating diffusion layer. That is, the smaller the capacitance of the floating diffusion layer, the higher the detection sensitivity defined by the output voltage for a constant signal charge. Therefore, the area of the floating diffusion layer has conventionally been reduced as a means for realizing a highly sensitive charge transfer device. However, the reduction of the area has almost reached the limit at present, and it is required to take new measures to replace it.

[0007]

According to the present invention, there is provided a charge transfer having a charge transfer region provided in a surface region of a semiconductor substrate and a charge transfer electrode formed through an insulating film provided on the charge transfer region. In a charge transfer device having an element, a floating diffusion layer provided at a subsequent stage of the charge transfer element, for receiving charges transferred in the charge transfer element, and an output transistor for detecting a potential of the floating diffusion layer,
At least part of the floating diffusion layer is provided below the insulating film that is thicker than the gate insulating film.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention. In the figure, parts corresponding to those of the conventional example of FIG. 2 are designated by the same reference numerals, and a duplicate description will be omitted.

This embodiment is similar to the conventional example shown in FIG.
The surface of the n-type floating diffusion layer 11 is provided with a thick insulating film 4 for element isolation.
It is covered with a thick insulating film 4b formed in the same step as a. Here, the n-type floating diffusion layer 11 and the gate electrode of the output transistor 14 are connected by making a hole in the thick oxide film 4b, or by forming a gate insulating film 5 only near the connection portion and making a hole in that portion for connection. It can also be realized.

In the present invention thus formed, n
The capacitance of the type floating diffusion layer 11 is significantly smaller than that of the conventional example. This means that the capacitance of the n-type floating diffusion layer has an overlapping capacitance portion with the output gate electrode 10 and the reset gate electrode 13, and this component can be obtained by forming the n-type floating diffusion layer portion directly under the thick insulating film. This is because it can be reduced.
For example, the thickness of the gate insulating film 5 below the output gate electrode is set to 1
00 nm silicon oxide film, thick insulating films 4a and 4b
By using a silicon oxide film having a thickness of 800 nm, the capacitance of the n-type floating diffusion layer could be reduced by 40%.

[0012]

As described above, according to the present invention, the capacitance of the floating diffusion layer can be reduced by forming the insulating film thicker than the gate insulating film on the surface of the floating diffusion layer, and the detection sensitivity of the signal charge can be reduced. Can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a sectional view showing a conventional example.

[Explanation of symbols]

 1 p-type semiconductor substrate 2 n-type impurity diffusion layer 3 p-type impurity diffusion layer 4a, 4b thick insulating film 5 gate insulating film 6 first gate electrode 7 insulating film 8 second gate electrode 9 p-type barrier diffusion layer 10 output Gate electrode 11 n-type floating diffusion layer 12 n-type drain diffusion layer 13 reset gate electrode 14 output transistor

Claims (1)

[Claims] 1. A charge transfer device having a charge transfer region provided in a surface region of a semiconductor substrate and a charge transfer electrode formed via a gate insulating film provided on the charge transfer region, and the charge transfer device. At least one of the floating diffusion layers is provided in a charge transfer device that is provided in a subsequent stage and has a floating diffusion layer that receives charges transferred in the charge transfer element and an output transistor that detects a potential of the floating diffusion layer. The charge transfer device, wherein the portion is provided below the insulating film that is thicker than the gate insulating film.