JPH05216833A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce special constitution, an over head and the load on a master board by making a communication between processors through a communication path which is formed on a mother board and connect respective daughter boards differently from a common signal line. CONSTITUTION:On the mother board 1E, the communication path 1D which connects processor boards 1A and 1B as the daughter boards is provided in addition to a multiprocessor bus 1C. The processor boards 1A and 1B make a data communication normally through the multiprocessor bus 1C, but use this communication path 1D for a communication which can not be made between the processor boards 1A and 1B by using the multiprocessor bus 1C. This constitution is not special constitution as compared with the use of a cable; even if one of the daughter boards 1A and 1B is the master board, the master board need not write or read data by obtaining the initiative and is not loaded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors are included in a system and data is transmitted and received among the processors.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional multiprocessor system. In this system, a daughter board 2A to 2F having a processor is connected to a mother board 2H provided with a multiprocessor bus 2G, and the multiprocessor bus 2 is connected between the processors of the daughter boards 2A to 2F.
Data is transmitted and received via G.

In the above multiprocessor system, daughter boards are classified by the following two classification methods. The first is to classify depending on whether the processor is included or not. The daughter board including the processor is called a processor board, and the daughter board not including the processor is called a non-processor board. The second is
The multiprocessor bus is classified according to whether or not it has an address output function. A daughter board having the function is called a master board (or simply a master), and a daughter board having no function is called a slave board (or simply a slave). .. All daughter boards have one of four categories related to the combination of the above two classifications.
Applicable to one. That is, the first category is a processor board and a master board, the second category is a processor board and a slave board, the third category is a non-processor board and a master board, and the fourth category is a non-processor board and a slave board. To give a specific example, the first category daughter board is a CPU board which is the center of the system, and the second
The daughter boards in the 3rd category are CPU boards responsible for secondary processing in the system, and the daughter boards in the 3rd category are DMA boards.
The controller board and the daughter board of the fourth category are general memory boards and I / O boards. The multiprocessor system is configured by a combination of all or part of the daughter boards in the first to fourth categories. And
The requirement of the multiprocessor system is that there are a plurality of daughter boards of the first and second categories in total, and at least one daughter board of the first category.

In the multiprocessor system as described above, it is usually necessary to send and receive data between the processors. Such conventional communication methods for data transmission and reception between processors include (1) common slave method,
The (2) master / slave system and (3) separate communication channel system have been conventionally known.

This (1) common slave system is realized by a system as shown in FIG. That is, the shared slave board 3C is provided for the processor boards 3A and 3B to perform data communication. And the processor board 3
A and 3B and the slave board 3C are connected by a multiprocessor bus 3D. And the processor board 3A
When sending data from the processor board 3B to the processor board 3B, the processor board 3A writes the data to the slave board 3C, and the processor board 3B sends the data to the slave board 3B.
The data is read from C. Further, when data is sent from the processor board 3B to the processor board 3A, the operation is performed in reverse to the above.

The (2) master / slave system is used for data communication between the master board and the slave boards. In this method, the communication method differs depending on whether the slave board is provided with the dual port memory. Here, the dual port memory means a memory which is provided on a slave processor board and can be accessed by both the processor on the processor board and the processor on the master processor board.

If a dual port memory exists, it is considered to be a shared memory between a master processor and a slave processor, and therefore it is equivalent to (1) common slave system.

On the other hand, if the dual port memory does not exist, the system shown in FIG. 4 is obtained. In the system shown in the figure, in order to transmit a message from the master board 4A to the slave board 4B, the master board 4A transmits the message to the slave board 4B via the multiprocessor bus 4C.
You can write to. Conversely, slave board 4
To send a message from B to master board 4A,
The master board 4A may read data from the slave board 4B via the multiprocessor bus 4C.

Further, (3) the separate communication path system is adopted for communication between master boards, communication between a master board and slave boards, and communication between slave boards. As shown in FIG. 6, this method is used in the processor board 5
A multiprocessor bus 5C is connected between A and the processor board 5B to share the multiprocessor bus 5C, while the processor boards 5A and 5B
A dedicated communication path (cable) 5D is provided between the communication path and the communication path and necessary data communication is performed via this communication path 5D.

[0010]

However, each of the above conventional methods has the following problems. First,
(1) The common slave method has a problem that a special board called the slave board 3C is required. In addition, there is a problem that the masters compete with each other to inevitably generate overhead, which hinders improvement in system performance.

(2) In the master / slave system, the slave board does not have any initiative in data communication, and the master board must be used in any direction for data communication, and the load on the master board is inevitable. There is a problem of concentration.

Further, (3) the separate communication path system requires a special communication path that is completely independent of the multiprocessor bus, which causes a problem of increasing the size of the system.

The present invention has been made to solve the above problems of the conventional multiprocessor system.
It is an object of the present invention to provide a multiprocessor system which has as few special configurations as possible, has less overhead, and has less load concentrated on the master board.

[0014]

According to the present invention, a plurality of daughter boards each having a processor mounted thereon and coupling means for coupling the daughter boards to each other are provided, and a common signal line for connecting the processors mounted on each daughter board is provided. In a multiprocessor system including a provided motherboard, a communication path for connecting each daughter board different from the common signal line is formed on the motherboard, and communication is performed between processors via this communication path. I did it.

[0015]

According to the above structure, since the communication path is formed on the mother board, the structure is not so special as the cable. Even if one of the daughter boards is the master board, the master board takes the initiative. There is no need to write data or read data, and this master board is not overloaded. Further, it is possible to eliminate the problem that overhead inevitably occurs as in the common slave system.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a part of a multiprocessor system according to an embodiment of the present invention. The motherboard 1E is provided with a multiprocessor bus 1C for connecting the daughter boards, as in the conventional case. The multiprocessor bus 1C includes a processor board 1A, which is a daughter board,
Connect 1B. Also, the multiprocessor bus 1C is
If required, it is connected to a non-processor board. Therefore, in normal operation, each board performs data communication via the multiprocessor bus 1C.

In this embodiment, in addition to the above configuration, a communication path 1 for connecting between the processor boards 1A and 1B is provided on the motherboard 1E, separately from the multiprocessor bus 1C.
D is provided. The processor boards 1A and 1B are
As described above, data communication is normally performed via the multiprocessor bus 1C, but the processor board 1
For communication between A and 1B, which cannot be performed using the multiprocessor bus 1C (communication when the multiprocessor bus 1C is occupied by another board, etc.), the communication path 1D is used. To use.

FIG. 2 shows the processor board 1A (1B).
A more detailed configuration of is shown. Processor board 1
At one side edge of A (1B), a card edge connector 21 that is connected to a connector provided on the motherboard 1E.
A and 21B are provided. Card edge connector 21A
To the multiprocessor bus 1C, and the card edge connector 21B to the communication path 1D. A switching means 22 such as a multiplexer is provided between the card edge connectors 21A and 21B and the processor 20. The processor 20 controls the switching means 22 via the signal line 23 according to the situation of the multiprocessor bus 1C, and switches the bus extending from the processor 20 to either the card edge connector 21A or 21B.

Although the number of processor boards is two in this embodiment, the present invention can be applied to the case of three or more processor boards. In this case, three or more processor boards may be connected by one communication path, or a plurality of communication paths may be provided to connect each processor board in a one-to-one relationship. Further, the plurality of processor boards may be in a master / master relationship, a master / slave relationship, or a slave / slave relationship.

[0020]

As described above, according to the present invention, since the communication path is formed on the mother board, a special structure is not required as much as a cable. In addition, even if one of the daughter boards is the master board, the master board is not loaded, and the problem that the overhead inevitably occurs unlike the common slave method can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an essential part of an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a block diagram of a conventional example.

FIG. 6 is a block diagram of a conventional example.

[Explanation of symbols]

1A, 1B Processor board 1C Multiprocessor bus 1D Communication path 1E Motherboard 20 Processor 21A, 21B Card edge connector 22 Switching means 23 Signal line

Claims (2)

[Claims] 1. A plurality of daughter boards each having a processor mounted thereon, and coupling means for coupling to the daughter boards,
In a multiprocessor system including a motherboard provided with a common signal line for connecting the processors mounted on each daughter board, a communication path connecting between the daughter boards different from the common signal line is provided on the motherboard. A multiprocessor system characterized by being formed and communicating between the processors via this communication path. 2. The multiprocessor system according to claim 1, wherein the daughter board is provided with switching means for switching between connecting the processor to a common signal line or a communication path.