JPH0521637A - Leadless chip carrier and manufacture thereof - Google Patents

Leadless chip carrier and manufacture thereof

Info

Publication number
JPH0521637A
JPH0521637A JP3171524A JP17152491A JPH0521637A JP H0521637 A JPH0521637 A JP H0521637A JP 3171524 A JP3171524 A JP 3171524A JP 17152491 A JP17152491 A JP 17152491A JP H0521637 A JPH0521637 A JP H0521637A
Authority
JP
Japan
Prior art keywords
resin
chip carrier
leadless chip
leadless
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3171524A
Other languages
Japanese (ja)
Inventor
Katsutoshi Fujita
勝利 藤田
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP3171524A priority Critical patent/JPH0521637A/en
Publication of JPH0521637A publication Critical patent/JPH0521637A/en
Application status is Pending legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To increase the surface flatness of a sealing resin more than those of conventional ones without using a resin frame at all. CONSTITUTION:A chip part 2 is mounted on a board 1 and then the chip part 2 is connected with a conductor layer 4 by wires 5. Next, a sealing resin 8 is molded by transfer molding step to resin-seal the chip part 2 and the wires 5. At this time, the configuration size of a leadless chip carrier can be diminished by the size of the eliminated resin frame. Besides, the thickness size of the leadless chip carrier itself can be diminished by the increased surface flatness size of the sealing resin 8. Furthermore, the manufacturing cost can be cut down by the cost of the eliminated resin frame fitting manhours.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はリードレスチップキャリアおよびその製造方法に関する。 The present invention relates to a leadless chip carrier and a method of manufacturing the same.

【0002】 [0002]

【従来の技術】従来のリードレスチップキャリアの一例を図2に示す。 BACKGROUND ART An example of a conventional leadless chip carrier shown in FIG. 図2(a)は、このリードレスチップキャリアの斜視図であり、図2(b)は、図2(a)におけるAーA断面図である。 2 (a) is a perspective view of the leadless chip carrier, Fig. 2 (b) is a A-A sectional view in FIG. 2 (a).

【0003】図2(a)および(b)を参照すると、このリードレスチップキャリアでは、基板1の中央にチップ部品2がマウントされている。 [0003] With reference to FIGS. 2 (a) and (b), in this leadless chip carrier, the chip component 2 is mounted in the center of the substrate 1. 基板1は、基材層3とその上に形成された導体層4とからなっている。 Substrate 1 is made from the base material layer 3 and formed thereon a conductor layer 4. チップ部品2上の電極と基板1上の導体層3とは、ワイヤ5で接続されている。 The electrode and the conductor layer 3 on the substrate 1 on the chip components 2 are connected by wires 5. 基板1上には樹脂枠6が設けられており、この樹脂枠6の内側には封止用樹脂7が充填され、 On the substrate 1 and the resin frame 6 is provided, the sealing resin 7 on the inside of the resin frame 6 is filled,
これによってチップ部品2とワイヤ5とが封止されている。 This is sealed chip component 2 and the wire 5 Togafu.

【0004】従来のリードレスチップキャリアでは、上述のように、基板1の上に樹脂枠6が設けられていることが特徴である。 [0004] In the conventional leadless chip carrier, as described above, it is characterized in that the resin frame 6 is provided on the substrate 1. この樹脂枠6は、製造中に、内部に充填された封止用樹脂7が流れ出さないようにするためのものである。 The resin frame 6, during manufacture, is intended to prevent the sealing resin 7 filled inside is not flow.

【0005】すなわち、このリードレスチップキャリアでは、基板1の構造が単板構造であるので、チップ部品2と導体層4とを電気的に接続するためには、基板1表面に設けられた導体層4に対してボンディングを行なうことになり、ワイヤ5の高さが基板表面よりも必ず高くなる。 Namely, in this leadless chip carrier, since the structure of the substrate 1 is a single plate structure, in order to electrically connect the chip component 2 and the conductive layer 4, the conductor provided on the substrate 1 surface would do bonding to the layer 4, the height of the wire 5 is always higher than the substrate surface. 従って、封止用樹脂7としては、ワイヤ5を確実に覆うためには、高さが基板1表面より高くなくてはならず、このため、製造中に封止用樹脂7が流れ出さないようにするための樹脂枠6が必要になるのである。 Accordingly, the sealing resin 7, to cover the wire 5 to ensure the height must not be higher than the surface of the substrate 1, and therefore, so that the not flow sealing resin 7 during manufacture it become necessary resin frame 6 for the.

【0006】 [0006]

【発明が解決しようとする課題】上述したように、従来のリードレスチップキャリアでは、チップ部品2およびワイヤ5が基板1表面より高くなることから、流れ止めとしての樹脂枠6が必要であり、その取り付けのための工事が必要になる、又、作業順序によっては、チップ部品2がマウントされる前に樹脂枠6が取り付けられていることがあり、チップをマウントするためのマウントペーストを印刷によって供給することが不可能となるなど、製造工程での能率がよくない。 [0007] As described above, in the conventional leadless chip carrier, since the chip component 2 and the wire 5 is higher than the surface of the substrate 1, it is necessary resin frame 6 as antirunning, its construction is required for the attachment, also by work order, there is the resin frame 6 is attached before the chip component 2 is mounted, by printing a mount paste for mounting a chip etc. can be supplied becomes impossible, poor efficiency of the manufacturing process.

【0007】又、リードレスチップキャリアそのものとしては、樹脂枠6を取り付けるためのスペースが必要となり、その分だけ寸法が大きくなってしまう。 [0007] As the leadless chip carrier itself, space for attaching the resin frame 6 is required, the size is correspondingly increased. 更に、封止用樹脂7の充填はポッティングにより行なわれるため、樹脂表面の平坦性がよくなく、外形的にも高さを低くすることには限界がある。 Furthermore, the filling of the sealing resin 7 is effected by potting, without good flatness of the resin surface, there is a limit to reducing the even height external shape. 従来のリードレスチップキャリアでは、このような封止用樹脂7の形状のばらつきに基ずく厚さの寸法精度は、±0.5mmが限度であった。 In conventional leadless chip carrier, the dimensional accuracy of the base Nuisance thickness variation of such a shape of the sealing resin 7, ± 0.5 mm was limits.

【0008】本発明は、上記のような従来のリードレスチップキャリアの問題点に鑑みてなされたものであって、樹脂枠が不要で、しかも封止樹脂表面の平坦性に優れ、厚さ寸法精度が良好なリードレスチップキャリアを提供するこを目的とする。 [0008] The present invention was made in view of the problems of the conventional leadless chip carrier, as described above, it requires no resin frame, moreover excellent in flatness of the sealing resin surface, thickness accuracy is the purpose of this to provide good leadless chip carrier.

【0009】 [0009]

【課題を解決するための手段】本発明のリードレスチップキャリアは、基板上に搭載されたチップ部品を、トランスファモールドにより樹脂封止したことを特徴としている。 Leadless chip carriers SUMMARY OF THE INVENTION The present invention is a chip component mounted on the substrate, is characterized in that resin-sealed by transfer molding.

【0010】 [0010]

【実施例】次に、本発明の最適な実施例について、図面を参照して説明する。 EXAMPLES Next, the best embodiments of the present invention will be described with reference to the drawings. 図1(a)は、本発明の第1の実施例の断面図である。 Figure 1 (a) is a cross-sectional view of a first embodiment of the present invention.

【0011】図1(a)を参照すると、本実施例のリードレスチップキャリアでは、基板1上にチップ部品2がマウントされている。 Referring to FIG. 1 (a), the leadless chip carrier of this embodiment, the chip component 2 is mounted on the substrate 1. チップ部品2と基板1上の導体層4とはボンディングされたワイヤ5によって接続されている。 The chip component 2 and the conductor layer 4 on the substrate 1 are connected by a wire 5 that is bonded. そして、チップ部品2とワイヤ5とが、トランスファモールドされた封止用樹脂8によって封止されている。 Then, the chip component 2 and the wire 5 are sealed by the sealing resin 8 that is transfer molding. 本実施例では、上述のような構造・工法をとることにより、流れ止めの樹脂枠を使用することなしに、封止樹脂8の表面の平坦性が従来のものよりも更に優れたリードレスチップキャリアを実現している。 In the present embodiment, by adopting the structure and construction methods as described above, without the use of resin frame antirunning, leadless chip flatness of the surface of the sealing resin 8 is more excellent than the conventional It has achieved a career.

【0012】本実施例では、封止用樹脂7の表面平坦性がよくなったことから、リードレスチップキャリアとしての厚さの寸法精度を±0.2mm程度にまで向上させることができた。 [0012] In this embodiment, since the surface flatness of the sealing resin 7 becomes better, it was possible to improve the dimensional accuracy of the thickness of a leadless chip carrier to about ± 0.2 mm. 又、樹脂枠が不要になったので、そのスペース(10mm 2 〜40mm 2 )分だけ外形寸法を小さくすることができた。 In addition, since the resin frame is no longer needed, it was possible to reduce the outer dimensions only that space (10mm 2 ~40mm 2) minutes.

【0013】次に、本発明の第2の実施例について説明する。 [0013] Next, description will be given of a second embodiment of the present invention. 図1(b)は、本発明の第2の実施例の断面図である。 Figure 1 (b) is a cross-sectional view of a second embodiment of the present invention.

【0014】図1(b)を参照すると、本実施例が図(a)に示す第1の実施例と異なるのは、基板1の、チップ部品2がマウントされる部分である。 [0014] Referring to FIG. 1 (b), it differs from the first embodiment in which the present embodiment is shown in FIG. (A), a portion of the substrate 1, the chip component 2 is mounted. 本実施例における基板1には、中央に座ぐり9が設けられている。 The substrate 1 in this embodiment, spot facing 9 is provided in the center.

【0015】本実施例は、チップ部品2をこの座ぐり9 [0015] The present embodiment, the chip component 2 this counterbore 9
内にマウントして封止用樹脂7で覆うことによって、リードレスチップキャリアとしての厚さ寸法を、第1の実施例よりも更に薄くすることができるという利点を持っている。 By covering with a sealing resin 7 and mounted within, it has the advantage that the thickness of the leadless chip carrier, may be thinner than the first embodiment.

【0016】尚、上述の第1の実施例および第2の実施例においては、チップ部品が1個だけ搭載されたシングルチップ構造のリードレスチップキャリアについて説明したが、本発明はこれに限られるものではない。 [0016] In the first and second embodiments have been described in relation leadless chip carrier single-chip structure with which the chip components are mounted only one, the present invention is limited thereto not. チップ部品が2個以上のマルチチップ構造であっても、実施例と同様の効果が得られることは明らかである。 Even chip component is in two or more multi-chip structure, it is clear that the same effect as the embodiment can be obtained.

【0017】 [0017]

【発明の効果】以上説明したように、本発明によれば、 As described in the foregoing, according to the present invention,
リードレスチップキャリアにおいて、チップ部品をトランスファモールドによって樹脂封止することによって、 In leadless chip carrier, by the resin sealing by transfer molding a chip component,
樹脂枠を用いることなしに、封止用樹脂の表面平坦性を従来のものよりも向上させることができる。 Without using a resin frame, the surface flatness of the sealing resin can be improved than conventional ones.

【0018】このため、リードレスチップキャリアそのものとしては、樹脂枠が不要になった分外形寸法を小さくすることができ、又、封止用樹脂表面の平坦性が向上した分、厚さ寸法を低くすることができる。 [0018] Therefore, as the leadless chip carrier itself, it is possible to reduce the amount outside dimension resin frame is no longer needed, also partial flatness of the sealing resin surface is improved, the thickness it can be lowered. しかも、樹脂枠取り付けの工数が不要となるので製造コストを低減することができる。 Moreover, it is possible to reduce the manufacturing cost since man-hours of the resin frame mounting is not required.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】分図(a)は、本発明の第1の実施例のリードレスチップキャリアの断面図である。 [1] partial view (a) is a cross-sectional view of a leadless chip carrier of the first embodiment of the present invention. 分図(b)は、本発明の第2の実施例のリードレスチップキャリアの断面図である。 Min Figure (b) is a cross-sectional view of a leadless chip carrier of a second embodiment of the present invention.

【図2】分図(a)は、従来のリードレスチップキャリアの斜視図である。 [2] fraction view (a) is a perspective view of a conventional leadless chip carrier. 分図(b)は、分図(a)におけるAーA断面図である。 Min Figure (b) is a A-A sectional view in partial FIG (a).

【符号の説明】 DESCRIPTION OF SYMBOLS

1 基板 2 チップ部品 3 基材層 4 導体層 5 ワイヤ 6 樹脂枠 7,8 封止用樹脂 9 座ぐり 1 substrate 2 chip component 3 substrate layer 4 conductive layer 5 wires 6 resin frame 7,8 encapsulating resin 9 countersunk

Claims (1)

  1. 【特許請求の範囲】 【請求項1】 基板上に搭載されたチップ部品を、トランスファモールドにより樹脂封止したことを特徴とするリードレスチップキャリア。 Claims 1. A leadless chip carrier and chip component mounted on the substrate, wherein the resin-sealed by transfer molding. 【請求項2】 基板上に搭載されたチップ部品を、トランスファモールドにより樹脂封止する工程を含むことを特徴とするリードレスチップキャリアの製造方法。 2. A chip component mounted on the substrate, a manufacturing method of the leadless chip carrier, characterized in that it comprises a step of resin-sealing by transfer molding.
JP3171524A 1991-07-12 1991-07-12 Leadless chip carrier and manufacture thereof Pending JPH0521637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3171524A JPH0521637A (en) 1991-07-12 1991-07-12 Leadless chip carrier and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3171524A JPH0521637A (en) 1991-07-12 1991-07-12 Leadless chip carrier and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0521637A true JPH0521637A (en) 1993-01-29

Family

ID=15924718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3171524A Pending JPH0521637A (en) 1991-07-12 1991-07-12 Leadless chip carrier and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0521637A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6838751B2 (en) 2002-03-06 2005-01-04 Freescale Semiconductor Inc. Multi-row leadframe

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943554A (en) * 1982-09-03 1984-03-10 Toshiba Corp Resin-sealed semiconductor device
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943554A (en) * 1982-09-03 1984-03-10 Toshiba Corp Resin-sealed semiconductor device
JPS59208756A (en) * 1983-05-12 1984-11-27 Sony Corp Manufacture of semiconductor device package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6838751B2 (en) 2002-03-06 2005-01-04 Freescale Semiconductor Inc. Multi-row leadframe

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