JPH05181673A - Microprocessor - Google Patents

Microprocessor

Info

Publication number
JPH05181673A
JPH05181673A JP3345705A JP34570591A JPH05181673A JP H05181673 A JPH05181673 A JP H05181673A JP 3345705 A JP3345705 A JP 3345705A JP 34570591 A JP34570591 A JP 34570591A JP H05181673 A JPH05181673 A JP H05181673A
Authority
JP
Japan
Prior art keywords
instruction
processing
control
control processing
macro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3345705A
Other languages
Japanese (ja)
Inventor
Hitoshi Takahashi
均 高橋
Original Assignee
Fujitsu Ltd
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, 富士通株式会社 filed Critical Fujitsu Ltd
Priority to JP3345705A priority Critical patent/JPH05181673A/en
Publication of JPH05181673A publication Critical patent/JPH05181673A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide the microprocessor which executes a high-speed event processing without accelerating a clock frequency, improves versatility and facilitates an interface with a high-level language. CONSTITUTION:This device is provided with a peripheral circuit (exclusive processing means) 3, main memory (instruction storing means) 1 to store a macro instruction composed of a general-purpose instruction and an extending instruction, extending instruction conversion table 6 to convert the extending instruction in the macro instruction stored in the instruction storing means 1 into a processing instruction for executing prescribed control in a prescribed controlled system, and control processing means 2 to execute the various control processings of the controlled system based on the macro instruction stored in the instruction storing means 1 when executing any prescribed instruction and in case of executing the control processing based on the extending instruction as the macro instruction, the control processing means 2 executes the prescribed control processing converted by the extending instruction conversion table 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor which is suitable for use in the field of electric appliances containing a microcomputer and which controls various operations of the electric appliances. In recent years, for example, air conditioners,
Many electric appliances with a built-in microcomputer, such as rice cookers, are provided, and along with this, many microprocessors to be built into electric appliances are being developed.

As a function required for this microprocessor, a microprocessor capable of performing high-speed event processing, which is a predetermined process under a specific situation, is required in the market, and each company has its own high-speed, high-performance CPU (Central Processor).
We are developing single-chip microcomputers (microprocessors) each equipped with an ocessing unit) core and are trying to meet this demand.

[0003]

2. Description of the Related Art As a conventional microprocessor of this type, there has been a microprocessor according to the following method for performing event processing at high speed. The clock supplied from the outside has been made faster to improve the processing function per unit time (clock frequency increase).

When an event occurs, the instruction operation of the CPU is temporarily stopped, and priority is given to transfer between blocks required for event processing (automatic transfer). It has a built-in peripheral circuit that processes only the event of interest.
Except when it is necessary to transfer data to and from PU, processing is performed only by the peripheral circuit for event processing (built-in dedicated circuit).

[0005]

However, in the above-described conventional microprocessor, since the clock frequency is increased, the current consumption increases as the speed of the external clock increases. Also,
The noise generated from the device also increases. Further, there is a problem that the device used also needs to support a high clock speed, which increases the cost of the device.

In the conventional microprocessor, the transfer between blocks required for event processing is preferentially performed, that is, automatic transfer is performed. Normally, the automatic transfer function is used. It is generally not possible to transfer data between predetermined blocks and perform operations other than predetermined calculations. When setting the functions required by each user in the microprocessor, do not create a microprocessor for each user. However, there is a problem that the versatility is low.

Since the conventional microprocessor has a structure in which a peripheral circuit dedicated to event processing is built in, the processing can be performed at high speed, but the structure is more specialized than that of the conventional microprocessor. Therefore, the versatility is further reduced, and since the user must recognize and use the control register of the peripheral circuit as an absolute address, it is difficult to interface with a high-level language such as C language. There has been a problem that the effort for creating software for use becomes great.

[Object] Therefore, an object of the present invention is to provide a microprocessor that performs high-speed event processing without increasing the clock frequency, has high versatility, and easily interfaces with a high-level language. ..

[0009]

In order to achieve the above-mentioned object, a microprocessor according to the present invention has a dedicated processing means for performing various control processing for each of the plurality of controlled objects, and various control processing in the dedicated processing means. Corresponding to, a command storage for storing a macro command including a general-purpose command that is a processing command that performs basic control among various control processes in the control target and an extended command that is a processing command that performs different control depending on the intended use Means, an extended instruction conversion table for converting an extended instruction in the macro instruction stored in the instruction storage means into a processing instruction for performing predetermined control in a predetermined control target, and stored in the instruction storage means when executing a predetermined instruction Control processing means for executing various control processing of the controlled object based on the generated macro instruction, and the control processing means stores the macro instruction as the macro instruction. When performing control processing based on Zhang instructions, and configured to perform predetermined control process that is converted by the extended instruction conversion table.

[0010]

According to the present invention, since the dedicated processing means is provided, the high-speed event processing can be avoided even if the clock is not speeded up, and the macro instruction which is the direct processing execution instruction in the control processing means is extended with the general-purpose instruction. Further, in the case of an extended instruction, the extended instruction conversion table converts the instruction into a processing instruction for performing a predetermined control in a predetermined control target, so that a special control process for each user is defined in the extended instruction conversion table. By doing so, high versatility is obtained.

Further, by describing the absolute address or the like in the dedicated processing means in the extended instruction conversion table, for example, the programmer does not need to recognize the absolute address or the like of the dedicated processing means, so that an interface with a high-level language is provided. Will be easier. That is, a high-speed event processing can be performed without increasing the clock frequency, versatility is enhanced, and a microprocessor that easily interfaces with a high-level language can be obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 3 are diagrams showing an embodiment of a microprocessor according to the present invention, FIG. 1 is a block diagram showing an overall configuration of the present embodiment, and FIG. 2 is a block diagram showing a main configuration of the present embodiment. FIG. 3 is a flow chart for explaining an operation example of this embodiment.

First, the structure will be described. The microprocessor of this embodiment is roughly composed of a main memory 1 which is an instruction storing means, a CPU 2 which is a control processing means, and a peripheral circuit 3 which is a dedicated processing means. In the figure, reference numeral 4 is a bus that serves as a transfer path for address and data between the main memory 1, the CPU 2, and the peripheral circuit 3.

The main memory 1 is a main memory of the CPU 2, and internally stores a storage area 5 for macro instructions including general instructions and extended instructions and an extended instruction conversion table 6. The CPU 2 performs various arithmetic operations and control processing for the peripheral circuit 3 based on the macro instruction in the main memory 1. The peripheral circuit 3 is a collection of processing circuits necessary for executing a predetermined event process.

As shown in FIG. 2, the extended instruction conversion table 6 describes, for example, the address of the peripheral circuit 3, a portion indicating the content of processing (in this case, a product-sum operation), parameters necessary for processing, and the like. It is a thing. Next, the operation will be described with reference to FIG. First, when the macro instruction stored in the main memory 1 is fetched by the CPU 2 (step 1) and the macro instruction is interpreted and the macro instruction is an extension instruction (step 2), the extension instruction conversion table 6 Is taken in (step 3), and the predetermined processing is performed by the CPU 2 based on the description contents converted by the extended instruction conversion table 6.

In this case, specifically, the address data of the peripheral circuit 3 is set in the address register (step 4), the product-sum operation is instructed to the operation circuit 2a in the CPU 2, and the product is added to the counter 2b in the CPU 2. The sum number parameter is set (step 5). Then, the product-sum operation is performed by the arithmetic circuit 2a the number of times set in the counter 2b (step 6).

That is, in this embodiment, when the macro instruction is an extension instruction, the identification of the specific peripheral circuit 3 and the identification of the operation pattern parameter are performed according to the description contents of the extension instruction conversion table 6, and the CPU 2 and the peripheral circuit 3 are identified. A predetermined process is executed between and. This makes it possible to create a unique instruction for each development product type or each user, and easily deal with it according to the application.

As described above, in this embodiment, since the peripheral circuit and the CPU operation can be performed in parallel by the peripheral circuit, the processing can be speeded up without increasing the speed of the external clock. Further, any peripheral circuit can be selected simply by changing the description of the extended instruction conversion table.

Further, since the target register can be referred to without designating the address (in particular, the absolute address), the interface with a high-level language is facilitated and the code efficiency at the time of program creation is improved. Therefore, high-speed event processing can be performed without increasing the clock frequency, and a microprocessor with high versatility and easy interface with a high-level language can be obtained.

Not limited to the above embodiment, the main memory may be an external memory which is referred to only when the extended instruction is executed, and the bus which refers to the table may be a dedicated bus.

[0021]

According to the present invention, by providing the dedicated processing means, high-speed event processing can be performed without speeding up the clock, and the macro instruction is divided into a general-purpose instruction and an extension instruction, and the extension instruction In this case, since the extended instruction conversion table is used to convert into a processing instruction for performing a predetermined control on a predetermined control target, by defining a special control process for each user in the extended instruction conversion table, high versatility can be obtained. it can.

Further, by describing the absolute address or the like in the dedicated processing means in the extended instruction conversion table, the programmer does not need to recognize the absolute address or the like of the dedicated processing means, so that the interface with a high-level language is provided. It will be easier. Therefore, high-speed event processing can be performed without increasing the clock frequency, and a microprocessor with high versatility and easy interface with a high-level language can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of this embodiment.

FIG. 2 is a block diagram showing a main configuration of the present embodiment.

FIG. 3 is a flowchart for explaining an operation example of the present embodiment.

[Explanation of symbols]

 1 main memory (instruction storage means) 2 CPU (control processing means) 3 peripheral circuit (dedicated processing means) 4 bus 5 macro instruction storage area 6 extended instruction conversion table

Claims (1)

[Claims]
1. A dedicated processing means for performing various control processing for each of the plurality of control objects, and a basic control processing among the various control processing for the control objects corresponding to the various control processing by the dedicated processing means. Instruction storing means for storing a macro instruction including a general instruction which is a processing instruction for performing various controls and an extended instruction which is a processing instruction for performing different control depending on the intended use, and a macro instruction stored in the instruction storing means. An extended instruction conversion table for converting an extended instruction into a processing instruction for performing a predetermined control in a predetermined control target, and various control processing for the control target based on a macro instruction stored in the instruction storage means when a predetermined instruction is executed. Control processing means for executing the control processing means, wherein the control processing means performs control processing based on the extension instruction as the macro instruction, the extension instruction conversion table Therefore microprocessor and performs the converted predetermined control process.
JP3345705A 1991-12-27 1991-12-27 Microprocessor Withdrawn JPH05181673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3345705A JPH05181673A (en) 1991-12-27 1991-12-27 Microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3345705A JPH05181673A (en) 1991-12-27 1991-12-27 Microprocessor

Publications (1)

Publication Number Publication Date
JPH05181673A true JPH05181673A (en) 1993-07-23

Family

ID=18378409

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3345705A Withdrawn JPH05181673A (en) 1991-12-27 1991-12-27 Microprocessor

Country Status (1)

Country Link
JP (1) JPH05181673A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292881B1 (en) 1998-03-12 2001-09-18 Fujitsu Limited Microprocessor, operation process execution method and recording medium
US8187099B2 (en) 2000-03-30 2012-05-29 Nintendo Co., Ltd. Game method and apparatus for enabling a video game system console to execute video game programs originally written for execution on architecturally different video game platforms
US8986112B2 (en) 2006-11-17 2015-03-24 Nintendo Co., Ltd. System and method for downloading video game programs

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6292881B1 (en) 1998-03-12 2001-09-18 Fujitsu Limited Microprocessor, operation process execution method and recording medium
US8187099B2 (en) 2000-03-30 2012-05-29 Nintendo Co., Ltd. Game method and apparatus for enabling a video game system console to execute video game programs originally written for execution on architecturally different video game platforms
US8986112B2 (en) 2006-11-17 2015-03-24 Nintendo Co., Ltd. System and method for downloading video game programs
US9259654B2 (en) 2006-11-17 2016-02-16 Nintendo Co., Ltd. System and method for obtaining software programs

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990311