JPH05167991A - Image conversion device capable of compensating resolution - Google Patents

Abstract

PURPOSE:To obtain an output image signal which has high resolution in a time direction without causing any deterioration in motion from an input image signal which has low resolution in the time direction. CONSTITUTION:An SD video signal consisting of 25 frames per second is supplied to an input terminal 1. This SD video signal is converted by a block converting circuit 2 into block structure (2X2X5 frames) and used as the address input of a memory 3. The memory 3 is stored with a previously generated mapping table and the output image signal (video signal consisting of 30 frames per second) of block structure (2X2X6 frames) is read out of the memory 3. This output image signal is converted by a block decomposing circuit 4 in the order of raster scanning and led out to an output terminal 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image conversion apparatus capable of resolution compensation applicable to conversion of the number of frames in system conversion of television signals, for example.

[0002]

2. Description of the Related Art There are various image signals having different temporal resolutions. For example, in the television system, NT
In the SC system, 30 frames are included in 1 second, and CCI
In the R method, 25 frames are included in 1 second. Also,
The number of frames in a movie is different from these television signals. Conventionally, a frame number conversion method using motion compensation is used to convert the number of frames of a television signal.

[0003]

However, in the conventional frame number conversion method, particularly, the method for increasing the resolution in the time direction, smoothing is performed, but there is a problem that motion deterioration (jerkiness) occurs. .. For example, the hatched area in FIG. 6 indicates the band of the video signal SD having a low resolution in the time direction. Even if this video signal is interpolated by frame number conversion to form a video signal of a higher resolution, the input signal A high-resolution HD component that does not exist is not restored. As a result, the movement of the output image deteriorates.

Therefore, an object of the present invention is to provide an image conversion apparatus capable of restoring high resolution components in the time direction and capable of resolution compensation.

[0005]

According to the present invention, a block circuit (2) for converting the order of a first digital image signal having a first temporal resolution into a block structure and a mapping table are stored. A first digital image signal converted into a block structure is supplied as an address, and a second digital image signal having a second time-direction resolution higher than the first time-direction resolution is supplied according to a mapping table. Memory (3) from which is read, and memory (3)
And a block decomposition circuit (4) for converting the order of the output signals of the two to the original one, and the mapping table forms two images with different temporal resolutions for the same image. Image is converted into a block structure and is trained with a plurality of patterns in advance so as to show the correlation between the blocks of the two images. It is a device.

[0006]

The mapping table is formed by using the source images of various pictures for training and showing the correlation between two image signals having different temporal resolutions. Therefore, with this mapping table, the high resolution component in the time direction that is not included in the input image signal can be restored.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below. In this embodiment, a video signal of 25 frames per second (a video signal having a low temporal resolution, which will be referred to as an SD video signal hereinafter) of the PAL system is a video signal of 30 frames per second (the time) This is an example of converting a video signal having a high directional resolution into an HD video signal hereinafter). In FIG. 1, a digital SD video signal is supplied to an input terminal indicated by 1. Examples of this SD video signal are SDVTR reproduction signals, broadcast signals, and the like. The blocking circuit 2 converts the SD video signal from the normal raster scan order to the block order.

As shown in FIG. 2, the output of the blocking circuit 2 is composed of regions P1 to P5 which are obtained by cutting out the same position of five temporally consecutive frames, and each region is (2 × 2 × 8 bits = 32). A video signal converted into a three-dimensional block containing bits) is generated. This (32 × 5 = 160 bits) is supplied to the memory 3 as an address. Memory 3
As described below, the mapping table based on the correlation between the SD image and the HD image is stored. This memory 3
Is composed of, for example, a nonvolatile RAM.

From the memory 3, as shown in FIG.
A video signal having a block structure including areas Q1 to Q6 of (× 2 × 8 bits) and each area occupying the same position in six consecutive frames is read. That is, an input video signal of 5 frames is converted into an output video signal of 6 frames. The position occupied by each area of the three-dimensional block of the output image is the same as that of each area of the three-dimensional block of the input image.

The output image data read from the memory 3 is supplied to the block decomposition circuit 4, and the order of the data is converted into the order of raster scanning. The output image data from the block decomposition circuit 4 is taken out to the output terminal 5. A monitor is connected to the output terminal 5 via a D / A converter (not shown). Since the output image is converted into 30 frames per second, the image can be reproduced by the NTSC monitor.

FIG. 3 shows an example of a configuration for creating the mapping table stored in the memory 3. In FIG. 3, a digital video signal of 150 frames per second is supplied to the input terminal indicated by 11. 150 frames are 25 frames and 3
The number of frames is the least common multiple of 0 frames. This input video signal is preferably a standard signal considering the creation of a mapping table.

This input video signal is supplied to the thinning circuits 26 and 28, respectively. The decimating circuit 26 decimates the input video signal by ⅕ in the time direction to form a video signal of 30 frames per second. The decimation circuit 28 forms a video signal of 25 frames per second. The output video signals of the thinning circuits 26 and 28 are supplied to the blocking circuits 27 and 29, respectively. The block circuit 27 outputs the video signals in the raster scanning order (2 × 2 ×
(6 frames) 3D block structure. The block circuit 29 converts the video signal in the raster scanning order into the structure of a (2 × 2 × 5 frame) three-dimensional block.

The output video signal of the blocking circuit 29 is supplied to the memory 20 and the frequency memory 21 as their addresses. The memory 20 has an address space of 2 ¹⁶⁰ , and (2 × 2 × 6 × 8 bits = 192 bits) of data is written to each address. The frequency memory 21 also has the same address space as the memory 20, but the data written to each address is frequency. That is, the read output of the memory 21 is the adder 22.
To the memory 21 and the output of the adder 22 is added to the memory 21.
Are written to the same address of. Memories 20 and 21
In the initial state, the contents of each address are cleared to zero.

The 192 bit data read from the memory 20 is supplied to the multiplier 23 and is multiplied by the frequency read from the frequency memory 21. The output of the multiplier 23 is supplied to the adder 24, and the adder 24 blocks the blocking circuit 2
It is added with the input data from 7. The output of the adder 24 is supplied to the divider 25 as a dividend. The output of the adder 22 is supplied to the divider 25 as a divisor. The output (quotient) of the divider 25 becomes the input data of the memory 20.

In the configuration of FIG. 3 described above, when a certain address Ai corresponding to one block of the SD video signal is first accessed, the read outputs of the memories 20 and 21 are 0, so one block of the HD video signal is obtained. The data X1 is written in the memory 20 as it is, and the value of the corresponding address in the memory 21 is set to 1. And then,
When this address is accessed again, the output of the adder 22 is 2 and the output of the adder 24 is (X1 + X2) (X
2 is an output of the delay circuit 13. Therefore, the divider 2
The output of 5 is (X1 + X2) / 3, which is the memory 2
Written to 0. On the other hand, in the frequency memory 21, the frequency 2
Is written. Furthermore, when the above address is accessed thereafter, the data in the memory 20 is updated to (X1 + X2 + X3) / 3 by the same operation, and the frequency is also 3.
Will be updated.

By performing the above-described operation for a predetermined period, the memory 20 stores an H signal formed from the same video signal.
A mapping table is stored showing the correlation between blocks of D video signals and blocks of SD video signals. In other words, when the pattern of the data of the block of the SD video signal is given, it is possible to form a mapping table which outputs the pattern of the block of the HD video signal which corresponds to the pattern evenly. This mapping table is stored in the memory 3 having the configuration of FIG.

FIG. 4 shows another embodiment of the present invention. Another embodiment is intended to reduce the memory capacity for creating the mapping table and storing it. As shown in FIG. 4, the output of the blocking circuit 2 has a three-dimensional ADRC.
The encoder 6 is inserted. ADRC (encoding adapted to dynamic range) is related to the proposal of the present applicant and utilizes the fact that a plurality of pixels in a block have a temporal and spatial correlation so that the number of bits of each pixel is 8
Bits are compressed to, for example, 4 bits.

The ADRC encoder 6 has a maximum value MAX of pixel data of a block, a minimum value MIN thereof, and (MAX-
A circuit for detecting a dynamic range DR represented by MIN = DR), and the dynamic range DR 2 ⁴ equal parts, by subtracting a circuit for generating the quantization step, the minimum value MIN, the pixels of the block It includes a subtractor circuit for normalizing the data and a quantizer circuit for dividing, ie, requantizing, the output of the subtractor circuit by a quantizing step. A
The DRC encoder 6 outputs a dynamic range DR for each block, a minimum value MIN, and a 4-bit code signal DT corresponding to each pixel.

The code signal DT in the output signal of the ADRC encoder 6 is supplied to the memory 3 as an address. From the memory 3, a video signal with the number of frames converted according to the mapping table is read. The dynamic range DR and the minimum value MIN in the encoded output of the ADRC encoder 6 are supplied to the delay circuit 7. Delay circuit 7
The dynamic range DR appearing at the output of is supplied to the dividing circuit 8 and divided by 2 ⁴ = 16. Therefore, the division circuit 8 obtains the quantization step of the block.

The code signal of the block of the output image signal read from the memory 3 is supplied to the multiplier 9. The quantization step is supplied to the multiplier 9, and therefore, the data after the minimum value removal can be restored from the multiplier 9. The output signal of the multiplier 9 is supplied to the adder 10 and the minimum value MIN from the delay circuit 7 is added. Therefore, the adder 1
From 0, the restored data of the HD video signal is obtained. This restored data is supplied to the block decomposition circuit 4, and the order of the data is converted into the order of raster scanning. The output image data from the block decomposition circuit 4 is taken out to the output terminal 5.

The embodiment of FIG. 4 is
Since the data for each block is compressed, the capacity of the memory 3 can be reduced. The process of creating the mapping table is similar to that described above, except that the correlation between the signals compressed by ADRC is detected. Therefore, the memory capacity for creating the mapping table can also be reduced.

In the process of creating the above-mentioned mapping table, in reality, data cannot be written in all the addresses of the memory 20, and an address of which data is 0 may occur. In that case, interpolation is performed with the data predicted from the non-zero data of the peripheral address. An example of the structure for this interpolation is shown in FIG.

In FIG. 5, the memory 30 is a memory in which the mapping table created as described above is stored. Counters 31 and 3 are used as address inputs of the memory 30.
One of the 32-bit addresses from 2 is the switching circuit 3
3 is supplied selectively. The clock CK from the input terminal 34 is supplied to the clock input of the counter 31 through the gate circuit 35. The address from the counter 31 is supplied to the switching circuit 33, the address memory 36, and the comparison circuit 37. The clock CK from the input terminal 38 is supplied to the counter 32, and the output thereof is supplied to the switching circuit 33 and the comparison circuit 37. Further, the output of the address memory 36 is supplied to the counter 32 as a preset input.

The output data of the memory 30 is supplied to a non-zero detection circuit 39 and a buffer memory (may be a latch) 40, and is also supplied to an interpolation data forming circuit 42 via a gate circuit 41. The interpolation data forming circuit 42 receives the output of the buffer memory 40, the output of the gate circuit 41, the output of the counter 31, and the output of the address memory 36, and forms interpolation data in place of zero data. This interpolation data is used as the data input of the memory 30.

The detection signal of the non-zero detection circuit 39 is supplied to the flip-flop 43 as its set input. Further, this detection signal is used to control ON / OFF of the gate circuit 41, control of writing / reading of the buffer memory 40 and the address memory 36, and control of the counter 32.

The output of the comparison circuit 37 for comparing the output of the counter 31 and the output of the counter 32 is supplied to the clear terminal of the counter 32 and the reset terminal of the flip-flop 43. By the output signal of the flip-flop 43,
ON / OFF of the gate circuit 35, control of the switching circuit 33, and writing of the memory 30 are controlled.

In order to explain the operation of the configuration of interpolation data formation of FIG. 5 described above, it is assumed that some of the data stored in the memory 30 is as follows.

[Table 1]

First, the counter 31 is incremented by the clock CK, and sequentially generated address signals are supplied to the memory 30 via the switching circuit 33. The read data from the memory 30 is supplied to the non-zero detection circuit 39. When the read data is non-zero, that is, when the data is obtained by the training image, the content of the buffer memory 40 is read and the output of the memory 30 is newly written in the buffer memory 40. At the same time, the gate 41 is turned on and the memory 3
The output of 0 is supplied to the interpolation data forming circuit 42.

Considering the timing at which the data D5 of the address A5 of the memory 30 is read as in the above example, since this is non-zero, the detection signal of the non-zero detection circuit 39 causes the buffer memory 40 to read the data. The previous non-zero data D2 is read out and stored in the buffer memory 40.
The data D5 is written. The data D5 is supplied to the interpolation data forming circuit 42 via the gate circuit 41. The data D2 is also supplied to the interpolation data forming circuit 42.

On the other hand, since the address input of the memory 30 at that time is A5, this is written in the address memory 36 by the nonzero detection signal. The address A2 stored before is read from the address memory 36. These addresses A2 and A5 are supplied to the interpolation data forming circuit 42, and the addresses A2 and A5 are supplied.
5, interpolation data to replace the zero data at the addresses A3 and A4 between the data D2 and D5 is formed.

In this example, the weighted average value according to the distance is formed as the interpolation data. That is, the distance between the addresses A2 and A5 is set to 3, the interpolation data of the address A3 is calculated as (2 · D2 + D5) / 3, and the interpolation data of the address A4 is calculated as (D2 + 2 · D5) / 3. .. As a method of forming the interpolation data, other than this, curve fitting, high-order interpolation, or the like may be used.

The address A2 from the address memory 36 is loaded into the counter 32 by the non-zero detection signal, and the output of the counter 32 sequentially generates the addresses A3 and A4 by the clock CK. When the output of the counter 32 reaches A5, the comparison circuit 37 generates a coincidence output. This coincidence output clears the counter 32 and resets the flip-flop 43.

While the flip-flop 43 is set, the switching circuit 33 selects the address (A3, A4) from the counter 32 and the memory 30 is set to the write mode. Therefore, interpolation data (2D2 + D5)
/ 3 and (D2 + 2 · D5) / 3 are written in the addresses A3 and A4 of the memory 30, respectively. During this period, the gate circuit 35 is turned off and the increment of the counter 31 is stopped.

While the flip-flop 43 is being reset, the gate circuit 35 is turned on and the switching circuit 3
3 selects the address from the counter 31, and the memory 30
Is the read mode. Then, the same operation as described above is performed.

Although the above-described embodiment is an example of conversion of the number of frames in the format conversion of the video signal, the present invention is similarly applied to conversion of an arbitrary number of frames in addition to this. it can. It can also be applied to conversion of image signals other than video signals. Furthermore, as block coding, vector quantization other than ADRC, DCT (Discrete
te Cosine Transform) can be used.

[0036]

According to the present invention, since the high resolution component is restored by utilizing the correlation between the image having a low temporal resolution and the image having a high temporal resolution, the number of frames and the number of frames are converted. It can be performed without deterioration.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a block structure.

FIG. 3 is a block diagram of an example of a configuration for creating a mapping table.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a block diagram of an example of a configuration for data interpolation when creating a mapping table.

FIG. 6 is a schematic diagram for explaining a conventional technique.

[Explanation of symbols]

 1 Input terminal of video signal of 25 frames per second 3 Memory storing mapping table 5 Output terminal of video signal of 30 frames per second

Claims (1)

[Claims] 1. A first digital image converted into the block structure, comprising a means for converting an order of a first digital image signal having a first temporal resolution into a block structure, and a mapping table stored therein. A signal is supplied as an address, and according to the mapping table, a second digital image signal having a second time-direction resolution higher than the first time-direction resolution is read out; Block mapping means for converting the order of the output signals into the original one, and the mapping table forms two images having different temporal resolutions with respect to the same image. Are converted into a block structure, and are formed in advance by training with a plurality of patterns so as to represent the correlation between the blocks of the two images. An image conversion device capable of resolution compensation, characterized in that