JPH05160288A - Manufacture of semiconductor device mounting substrate - Google Patents

Manufacture of semiconductor device mounting substrate

Info

Publication number
JPH05160288A
JPH05160288A JP34916291A JP34916291A JPH05160288A JP H05160288 A JPH05160288 A JP H05160288A JP 34916291 A JP34916291 A JP 34916291A JP 34916291 A JP34916291 A JP 34916291A JP H05160288 A JPH05160288 A JP H05160288A
Authority
JP
Japan
Prior art keywords
semiconductor
thin plate
mounting substrate
layer
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP34916291A
Other languages
Japanese (ja)
Other versions
JP2953163B2 (en
Inventor
Makoto Chokai
Hirokazu Tanaka
Hideaki Yoshida
秀昭 吉田
宏和 田中
誠 鳥海
Original Assignee
Mitsubishi Materials Corp
三菱マテリアル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp, 三菱マテリアル株式会社 filed Critical Mitsubishi Materials Corp
Priority to JP34916291A priority Critical patent/JP2953163B2/en
Publication of JPH05160288A publication Critical patent/JPH05160288A/en
Application granted granted Critical
Publication of JP2953163B2 publication Critical patent/JP2953163B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40091—Arched
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Abstract

(57) [Summary] [Object] To provide a method for manufacturing a substrate for mounting a semiconductor device, in which the nickel plating is prevented from peeling off from the surface of a thin plate such as aluminum, and the reliability is improved. [Structure] A step of forming a layer 12 of aluminum or the like on a surface of a ceramic substrate 11 on which a semiconductor device 16 is mounted,
A step of mechanically polishing the entire surface of the layer 12, a step of depositing a resist having a predetermined pattern on the surface, and a step of chemically polishing a portion where the resist is not deposited.
Since the step of forming the nickel layer 14 on this portion is provided, this portion is altered by the resist process,
Since the altered surface is chemically polished and the nickel layer 14 is formed on this portion, the altered portion is removed by the chemical polishing, and the unaltered surface is nickel-plated. Therefore, peeling of the nickel layer 14 from the layer 12 is completely prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate for mounting a semiconductor device, and more specifically, in the case of manufacturing a ceramic substrate by chemically polishing a thin plate of aluminum or the like adhered to the surface of the ceramic substrate, The present invention relates to a method for manufacturing a semiconductor device mounting substrate, the surface of which is not altered.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device mounting substrate for mounting a semiconductor device such as an IC chip, a ceramic substrate is covered with a thin plate of aluminum or aluminum alloy, and nickel is plated on a predetermined portion of the thin plate. ..

A conventional method of manufacturing a semiconductor device mounting substrate will be described with reference to FIGS. First, a ceramic substrate 21 made of alumina or the like was prepared (FIG. 11), and aluminum or aluminum alloy thin plates 22 for forming a circuit pattern and for heat sink bonding were respectively attached to both surfaces of the ceramic substrate 21 (FIG. 12). .. next,
The thin plate 22 was mechanically polished (FIG. 13) and chemically polished (FIG. 14) in this order. In addition, mechanical polishing is
This is done to remove the oxide layer on the surface of the thin plate 22. Then, chemical polishing is performed to increase the bonding strength between the thin plate 22 and nickel. Next, a resist 23 having a predetermined pattern was applied to a part of the thin plate 22 (FIG. 15). Next, the surface of the thin plate 22 on which the resist 23 was not applied was plated with nickel 24 (see FIG. 1).
6). Next, by removing the resist 24,
The other part of the thin plate 22 is plated with nickel 24 (FIG. 17).

[0004]

However, in such a conventional method for manufacturing a semiconductor device mounting substrate, the surface of the aluminum or aluminum alloy thin plate is altered in the resist step after chemical polishing. .. As a result, the nickel plating comes off. Therefore, there is a problem in that the reliability of the semiconductor device mounting substrate decreases.

[0005]

SUMMARY OF THE INVENTION Therefore, the present invention provides a method for manufacturing a semiconductor device mounting substrate, which prevents the nickel plating from peeling off from the surface of a thin plate of aluminum or aluminum alloy and improves the reliability of the semiconductor device mounting substrate. To do
That is the purpose.

[0006]

According to the present invention, there is provided a step of forming a layer of aluminum or an aluminum alloy on a surface of a ceramic substrate on which a semiconductor device is mounted, a step of mechanically polishing the entire surface of the layer, and a step of performing the mechanical polishing. A step of depositing a resist having a predetermined pattern on the mechanically polished surface, a step of chemically polishing a predetermined portion of the mechanically polished surface on which the resist is not deposited, and a nickel plating layer formed on the predetermined portion A method of manufacturing a semiconductor device mounting substrate, comprising:

[0007]

In the method for manufacturing a semiconductor device mounting substrate according to the present invention, a predetermined portion of the surface of the aluminum or aluminum alloy thin plate is altered by the resist process, and the altered surface is chemically polished. A nickel plating layer is formed on this predetermined portion. For this reason,
The altered portion is removed by chemical polishing, and the surface in the unaltered state is nickel-plated. Therefore, peeling of the nickel plating layer from the aluminum or aluminum alloy layer can be completely prevented.

[0008]

EXAMPLES A method for manufacturing a semiconductor mounting substrate according to the present invention will be described below based on examples. 1 to 10 are for explaining one embodiment of the present invention.

First, as an insulating ceramic substrate,
For example, an alumina substrate 11 which is an Al 2 O 3 sintered body having a predetermined thickness and a purity of 96% is used (FIG. 1). And, on the upper surface of the alumina substrate 11, for example, a purity of 9
The circuit forming thin plate 12 made of 9.99% aluminum is
For example, they are bonded by a brazing material made of an Al-Si alloy and an Al-Ge alloy. Further, the alumina substrate 11
A heat sink joining thin plate 18, which is also made of aluminum and has a purity of 99.99%, is adhered to the lower surface of the sheet by a brazing material (FIG. 2).

These are adhered to each other by brazing the brazing material to a thickness of 30 μm when the thin plate 12 and the thin plate 18 are rolled to form a brazing plate material (brazing sheet), and stacking these materials on the brazing material. 430-610 matched
It is carried out by brazing under a condition of being kept in a vacuum temperature range of 10 ° C. for 10 minutes to form a laminated joined body, followed by heat treatment at 350 ° C. for 30 minutes and then gradually cooling to room temperature. In addition, the circuit formation of the thin plate material 12 is performed by punching out the forming circuit before joining,
Alternatively, etching is performed after joining, or the like.

As the thin plate 12 and the thin plate 18, in addition to pure aluminum, for example, Al-2.5% (weight%, hereinafter the same) Mg-0.2% Cr alloy, Al-1% M.
n alloy, Al-0.02% Ni alloy, Al-0.005%
B alloy or the like can be used.

Next, the upper surface of the thin plate 12 and the lower surface of the thin plate 18 are subjected to mechanical polishing such as polishing (FIG. 3) to remove the oxide film on these surfaces.
Next, a photoresist film 13 is deposited on the upper surface of the thin plate 12 and exposed to light to form a photoresist film 13 having a predetermined pattern (FIG. 4). At this time, there is a possibility that the exposed portion of the upper surface of the thin plate 12 where the resist is removed by this resist process is deteriorated.

Next, the upper surface of the thin plate 12 where the photoresist film 13 is not formed and the lower surface of the thin plate 18 are chemically polished (FIG. 5). For example, in the temperature range of 50 to 90 ° C., phosphoric acid 20 to 60%, nitric acid 2 to 40%, and sulfuric acid 20
It is performed by immersing it in a liquid added with -60% for several seconds to several minutes. By this chemical polishing, the convex portions generated by the mechanical polishing are chemically dissolved and smoothed.

Next, a nickel-plated layer 14 having a thickness of 5 μm is formed on the chemically polished surface, that is, the upper surface of the thin plate 12 on which the photoresist film 13 is not formed and the entire lower surface of the thin plate 18 by a normal electroless plating method. It is applied (Fig. 6). Then, by removing the photoresist film 13, the nickel plating layer 14 is formed on the predetermined surface of the thin plate 12 and the lower surface of the thin plate 18 (FIG. 7).

When mounting a semiconductor device on this semiconductor device mounting substrate, for example, die bonding and wire bonding are performed. That is, first, the Pb—Sn solder 15 is applied to the nickel plating layer 14 (FIG. 8). The IC chip 16 and the like are mounted and fixed via the solder 15 (FIG. 9). Then, using ultrasonic energy, the pad such as the IC chip 16 and a predetermined portion of the circuit pattern of the thin plate 22 having a diameter of 25 to 300 μm and a purity of 9 are used.
Connect with 9.99% aluminum wire 17. further,
A heat sink 19 made of the same material as the thin plates 12 and 18 is joined to the substrate via the solder 15.

As a result of the chemical polishing and nickel plating in this way, the nickel plating layer 14 does not adhere to the aluminum thin plates 12 and 18 poorly, and
The nickel plating 14 does not become brittle, and pits and stains do not occur on it. This improves the adhesion of the solder 15 to the nickel plating layer 14 and improves the bonding strength of the IC chip 16 and the heat sink 19. Therefore, the quality of the semiconductor mounting device substrate is improved.

In the above embodiment, the heat sink 19 may be directly adhered to the alumina substrate 11 via the brazing material instead of the thin plate 18 and the nickel plating layer 15 on the alumina substrate 11.

[0018]

According to the present invention, the altered portion of the surface of a thin plate of aluminum or aluminum alloy can be removed, and this portion is nickel-plated. As a result, peeling of the nickel plating can be prevented. Therefore, the reliability of the semiconductor device mounting substrate can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a step of a method of manufacturing a semiconductor device mounting substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device mounting substrate according to the embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

FIG. 12 is a cross-sectional view showing a step of the method of manufacturing the conventional semiconductor device mounting substrate.

FIG. 13 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

FIG. 14 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

FIG. 15 is a cross-sectional view showing a step of the method of manufacturing the conventional semiconductor device mounting substrate.

FIG. 16 is a cross-sectional view showing a step in the conventional method for manufacturing a semiconductor device mounting substrate.

FIG. 17 is a cross-sectional view showing a step of the method of manufacturing the conventional semiconductor device mounting substrate.

[Explanation of symbols]

 11 Alumina Substrate 12 Circuit Forming Thin Plate 14 Nickel Plating Layer 16 IC Chip 18 Heat Sink Bonding Thin Plate

Claims (1)

[Claims]
1. A step of forming an aluminum or aluminum alloy layer on a surface of a ceramic substrate on which a semiconductor device is mounted, a step of mechanically polishing the entire surface of this layer, and a predetermined pattern on the mechanically polished surface. And a step of chemically polishing a predetermined portion of the mechanically polished surface on which the resist is not deposited, and a step of forming a nickel plating layer on the predetermined portion. A method for manufacturing a substrate for mounting a semiconductor device, which is characterized.
JP34916291A 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device Expired - Lifetime JP2953163B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34916291A JP2953163B2 (en) 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34916291A JP2953163B2 (en) 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device

Publications (2)

Publication Number Publication Date
JPH05160288A true JPH05160288A (en) 1993-06-25
JP2953163B2 JP2953163B2 (en) 1999-09-27

Family

ID=18401892

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34916291A Expired - Lifetime JP2953163B2 (en) 1991-12-06 1991-12-06 Method for manufacturing substrate for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JP2953163B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006524583A (en) * 2003-04-25 2006-11-02 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド Method for machining ceramics
JP2013214541A (en) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp Method for manufacturing power module substrate and power module substrate

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8001682B2 (en) 2004-08-17 2011-08-23 Mitsubishi Materials Corporation Insulation substrate, power module substrate, manufacturing method thereof, and power module using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006524583A (en) * 2003-04-25 2006-11-02 サン−ゴバン セラミックス アンド プラスティクス，インコーポレイティド Method for machining ceramics
JP2013214541A (en) * 2012-03-30 2013-10-17 Mitsubishi Materials Corp Method for manufacturing power module substrate and power module substrate

Also Published As

Publication number Publication date
JP2953163B2 (en) 1999-09-27

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