JPH05145871A - Image signal processor - Google Patents

Abstract

PURPOSE:To easily convert an image signal into a mirror image at low a cost with simple constitution by outputting the signal in the blanking period of the image signal inputted by an image signal input means during the blanking period of a mirror image signal. CONSTITUTION:Digital data outputted by an A/D converter 100 are supplied to one input terminal of a switch circuit 105, which selects and outputs digital data outputted by a switch circuit 104 in the image period of the image signal or the digital data outputted by the A/D converter 100 in the blanking period of the image signal with the control signal S5 outputted from a controller 107. The digital data outputted from the switch circuit 105 are converted by a D/A converter 106 into an analog image signal, which is supplied to a television monitor device, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for processing an image signal, and more particularly to an image signal processing for converting an image signal corresponding to an arbitrary image into a mirror image signal corresponding to a mirror image of the image reflected on a mirror. It relates to the device.

[0002]

2. Description of the Related Art Conventionally, in a system such as a videophone, in order to confirm the contents of an image signal transmitted from the other party, which is imaged by a video camera and transmitted to the other party, the image signal transmitted from the other party is used. A television monitor device that displays a corresponding received image is used to superimpose and display the transmitted image on the screen of the television monitor device.

Further, when the transmitted image is displayed on the television monitor as described above, if the transmitted image is our own image, the self-portrait is displayed by displaying a mirror image of oneself. If the transmitted image is an information image obtained by capturing an image of a document or map with a video camera, the original image (that is, the normal image) can be confirmed. ) Is displayed, you can easily check the contents.
It has a normal image display mode for displaying the transmitted image to be displayed as it is and a mirror image display mode for displaying a mirror image of the transmitted image on a mirror, and the transmitted image is corrected on the screen of the television monitor device according to any one of the display modes. It can be switched and displayed as an image or a mirror image.

When the transmission image is displayed according to the mirror image display as described above, the image signal corresponding to the transmission image is converted by the mirror image conversion circuit for converting the image signal corresponding to the mirror image, and the television is converted. It was supplied to the monitor device.

FIG. 3 is a block diagram showing the configuration of a conventional mirror image conversion circuit.

In FIG. 3, an image signal input from a video camera (not shown) is clamped by a clamp circuit 201, digitized by an A / D converter 202, and supplied to a switch circuit 203.

The switch circuit 203 is a memory controller 2 which generates various control signals according to a horizontal synchronizing signal separated from an image signal input from a video camera (not shown).
The control signal S1 output from the A.D.
The digital data supplied from the converter 202 is alternately switched and supplied to the memory circuit 204 and the memory circuit 205 every horizontal synchronization period.

The memory circuits 204 and 205 are in a data write operation state while the digital data is supplied from the switch circuit 203 by the control signals S2 and S3 output from the memory controller 209, and are not supplied. During the period, it is controlled to be in a data read operation state.

The digital data read from the memory circuits 204 and 205 is supplied to the switch circuit 206 whose switching operation is controlled by the control signal S4 output from the memory controller 209.
The digital data output from the switch circuit 206 is supplied to one input terminal of the switch circuit 207.

The other input terminal of the switch circuit 207 is supplied with pedestal level data output from a pedestal level data generation circuit 208 which generates data indicating the pedestal level in the blanking period of the image signal. The switch circuit 207 is controlled by the control signal S5 output from the memory controller 107 during the image period of the image signal.
And the pedestal level data output from the pedestal level data generation circuit 208 during the blanking period of the image signal. The digital data output from 207 is converted into an analog image signal by the D / A converter 210 and supplied to a television monitor device (not shown) or the like.

The pedestal level data generating circuit 208, for example, when the quantization bit in the A / D converter 220 and the D / A converter 210 is 8 bits and when it is a luminance (Y) signal. 8-bit pedestal level data indicating the level of "0" is added to the color difference (RY
Alternatively, in the case of the BY signal, the pedestal level data of 8 bits showing the level of "128" is generated.

FIG. 4 is a timing chart showing various control signals S1 to S5 output from the memory controller 209 of FIG. 3, and hereinafter, the mirror image conversion processing operation of the image signal according to the configuration shown in FIG. It will be described using the timing chart shown in FIG.

The switch circuits 203 and 206 shown in FIG.
207 is connected to the terminal on the L side in the drawing when the control signals S1, S4, S5 shown in FIG. 4 are at the low level, and is connected to the terminal on the H side in the drawing when the control signals are at the high level. I shall.

First, the switching operation of the switch circuit 203 is controlled by the control signal S1 output from the memory controller 209, and the digital data output from the A / D converter 202 is transferred to the memory circuit 204 via the switch circuit 203. Have been supplied to.

At this time, in the memory circuit 204, the digital data supplied from the A / D converter 202 to the memory in the memory circuit 204 while sequentially incrementing the write address by the control signal S2 output from the memory controller 209. Further, in the memory circuit 205, the digital signal written in the memory in the memory circuit 205 is read while sequentially incrementing the read address by the control signal S3 output from the memory controller 209, and output from the memory controller 209. Switch circuits 206, 2 whose switching operation is controlled by control signals S4, S5
It is supplied to the D / A converter 210 via 07.

Then, after the above-mentioned operation state is performed for one horizontal synchronization period, in the next one horizontal synchronization period, the connection state of the switch circuit 203 is switched by the control signal S1 output from the memory controller 209. , The memory circuit 204 is switched from the data write operation state to the read operation state, and the memory circuit 205 is switched from the data read operation state to the write operation state, and the memory circuit 204 sequentially decrements the read address. The digital data written in the memory in the memory circuit 204 one horizontal sync period before is read, and the switching operation is controlled by the control signals S4 and S5 output from the memory controller 209. It is supplied to the D / A converter 210 and , The memory circuit 205 the memory circuit 20 while sequentially decrements the write address
Digital data supplied from the A / D converter 202 is written in the memory in the memory 5.

As described above, in the digital data write / read operation in the memory circuit 205, the digital data is written while the write address is sequentially decremented when the digital data is written, and the read address is sequentially incremented when the digital data is read. However, the digital data is read out and the digital data write / read operation in the memory circuit 204 is performed by sequentially incrementing the write address when writing the digital data and writing the digital data while reading the digital data. By reading the digital data while decrementing, the writing order of the digital data in each memory circuit 204, 205 And by reversing the read Junsho, and mirror converts the image signal inputted to constitute so as to output as mirror image signal.

The switching operation of the mirror image converted image signal output from the switch circuit 206 and the pedestal level data output from the pedestal level data generation circuit 208 in the switch circuit 207 is performed by the control signal S5 output from the memory controller 209. Is controlled by.

That is, according to the standard, the image signal becomes an image period at a minimum of 9.22 μs after the fall of the horizontal synchronizing signal, and the period from the end of the image period to the next falling of the horizontal synchronizing signal is at least 1. .27 μs,
One horizontal synchronization period of the image signal is about 63.5 μs in total, and the switch circuit 207 is controlled by the control signal S5 output from the memory controller 209, and is output from the switch circuit 206 during the image period. Digital data to be supplied to the D / A converter 210, and the pedestal level data output from the pedestal level data generation circuit 208 is D / A during the blanking period.
It is configured to supply to the converter 210.

[0020]

By the way, in the system such as the above-mentioned videophone, the transmission image signal is converted into the mirror image signal by using the mirror image conversion circuit configured as shown in FIG. However, in the mirror image conversion circuit as shown in FIG. 3, a pedestal level data generation circuit for generating data indicating a pedestal level in the blanking period of the image signal is provided, and the mirror image converted digital image data and the pedestal level data generation are provided. Since the pedestal level data output from the circuit is configured to be output by switching between the image period and the blanking period in the image signal, the level of the blanking period in the input image signal is generated by the pedestal level data generation. Match the level indicated by the pedestal level data output from the circuit. It is necessary to provide the clamp circuit 201 in front of the A / D converter 202 as shown in FIG. 2, which complicates the system configuration and the circuit scale, and increases the cost. There was a problem that it would end up.

The present invention provides an image signal processing apparatus capable of converting an image signal corresponding to an arbitrary image into a mirror image image signal corresponding to a mirror image of the image by a simple and low-cost configuration. The purpose is to provide.

[0022]

An image signal processing apparatus according to the present invention includes an image signal input unit for inputting an image signal, an image signal input by the image signal input unit, and a mirror image of the image indicated by the image signal. Conversion processing means for converting into a mirror image image signal corresponding to the mirror image reflected in, and outputting, and during the image period of the image signal, the signal of the image period of the mirror image image signal output from the conversion processing means is output, And an image signal output unit for outputting a signal of the blanking period of the image signal input by the image signal input unit during the blanking period of the image signal, and an image signal for inputting the image signal. Input means; holding means for holding a signal corresponding to the pedestal level of the image signal input by the image signal input means; and image signal input by the image signal input means A conversion processing unit that converts the image represented by the image signal into a mirror image image signal corresponding to a mirror image reflected on a mirror and outputs the mirror image image signal, and a mirror image image signal output from the conversion processing unit during the image period of the image signal. Image signal output means for outputting a signal in the image period and for outputting a signal corresponding to the pedestal level of the image signal held in the holding means during the blanking period of the image signal.

[0023]

According to the above structure, the image signal corresponding to an arbitrary image can be converted into the mirror image image signal corresponding to the mirror image of the image by a simple and low cost structure. Become.

[0024]

EXAMPLES The present invention will be described below with reference to examples of the present invention.

FIG. 1 is a block diagram showing the configuration of an image signal processing apparatus to which the present invention is applied, as an embodiment of the present invention.

In this embodiment, the transmitted image signal is, for example, a red component (R) signal, a green component (G) signal and a blue component (B) signal or a luminance signal (Y) and two kinds of color difference signals (R- Y, B-Y).

In FIG. 1, a transmission image signal input from a video camera (not shown) is digitized by the A / D converter 100 and supplied to the switch circuits 101 and 105.

The switch circuit 101 is controlled by a control signal S1 output from a memory controller 107 which generates various control signals according to a horizontal synchronizing signal separated from a transmission image signal input from a video camera (not shown).
The digital data supplied from the D / D converter 100 is set to 1
The memory circuit 102 and the memory circuit 103 are provided every horizontal synchronization period.
Are switched alternately to supply.

The memory circuits 102 and 103 are in a data write operation state while the digital data is being supplied from the switch circuit 101 by the control signals S2 and S3 output from the memory controller 107, and are not being supplied. During the period, it is controlled to be in a data read operation state.

The digital data read from the memory circuits 102 and 103 is supplied to the switch circuit 104 whose switching operation is controlled by the control signal S4 output from the memory controller 107,
The digital data output from the switch circuit 104 is supplied to one input terminal of the switch circuit 105.

Digital data output from the A / D converter 100 is supplied to the other input terminal of the switch circuit 105, and the switch circuit 105 outputs a control signal S5 output from the memory controller 107.
Accordingly, during the image period of the image signal, the digital data output from the switch circuit 104,
During the blanking period of the image signal, the digital data output from the A / D converter 100 is selected and output, respectively.
The digital data output from 5 is the D / A converter 1
It is converted into an analog image signal by 06 and supplied to a television monitor device (not shown) or the like.

The mirror conversion processing operation of the image signal with the configuration shown in FIG. 1 will be described below.

The switch circuits 101, 104 shown in FIG.
Reference numeral 105 is connected to a terminal on the L side in the drawing when the control signals S1, S4, S5 output from the memory controller 107 are at a low level, respectively, and is connected to a terminal on the H side in the drawing when at a high level. Shall be done.

First, the switching operation of the switch circuit 101 is controlled by the control signal S1 output from the memory controller 107, and the digital data output from the A / D converter 100 is transferred to the memory circuit 102 via the switch circuit 101. Have been supplied to.

At this time, in the memory circuit 102, the digital data supplied from the A / D converter 100 is supplied to the memory in the memory circuit 102 while the write address is sequentially incremented by the control signal S2 output from the memory controller 107. In addition, the memory circuit 103 reads the digital data written in the memory in the memory circuit 103 by sequentially incrementing the read address by the control signal S3 output from the memory controller 107, and outputs the digital data from the memory controller 107. Switch circuits 104, 1 whose switching operation is controlled by control signals S4, S5
It is supplied to the D / A converter 106 via 05.

Then, after the above-mentioned operation state is performed for one horizontal synchronization period, in the next one horizontal synchronization period, the connection state of the switch circuit 101 is switched by the control signal S1 output from the memory controller 107. , The memory circuit 102 is switched from the data write operation state to the read operation state, and the memory circuit 103 is switched from the data read state to the write operation state.
The memory circuit 102 reads digital data written in the memory in the memory circuit 102 one horizontal synchronizing period before, while sequentially decrementing the read address,
Control signal S output from the memory controller 107
4 and S5 supplies the D / A converter 106 via the switch circuits 104 and 105 whose switching operations are controlled, and the memory circuit 103 sequentially decrements the write address while the memory in the memory circuit 103 is decremented. The digital data supplied from the A / D converter 100 is written in.

As described above, in the digital data write / read operation in the memory circuit 103, the digital data is written while the write address is sequentially decremented when the digital data is written, and the read address is sequentially incremented when the digital data is read. However, the digital data is read out, and the digital data write / read operation in the memory circuit 102 is performed by sequentially incrementing the write address when writing the digital data and writing the digital data while sequentially reading the read address when reading the digital data. By reading the digital data while decrementing, the writing order of the digital data in each memory circuit 102, 103 And by reversing the order read, and mirror converts the image signal inputted to constitute so as to output as mirror image signal.

By the way, in the embodiment shown in FIG. 1, the A / D converter 10 is operated during the blanking period of the image signal.
Digital data output from 0 is supplied to the D / A converter 106 as pedestal level data, but as shown in FIG. 2, the A / D converter 100 and the switch circuit 10 are connected.
5, a latch circuit 108 is provided between the digital signal and the digital signal corresponding to the pedestal level of the image signal among the digital data output from the A / D converter 100 by the control signal S6 output from the memory controller 109. Is temporarily latched, and the digital data latched by the latch circuit 108 is transferred to the switch circuit 105.
The same effect can be obtained even if it is configured to be supplied to the.

Incidentally, in the configuration shown in FIG.
The same reference numerals are given to the same configurations as those shown in, and detailed description will be omitted.

As described above, in this embodiment, when the transmission image signal is subjected to the mirror image conversion processing by using the mirror image conversion circuit, the memory circuit is used during the image period of the image signal output from the mirror image conversion circuit. By outputting the signal of the image period in the image signal subjected to the mirror image conversion and outputting the signal corresponding to the pedestal level of the image signal input to the mirror image conversion circuit as it is during the blanking period of the image signal, Conventionally, even if the clamp circuit, which was required to clamp the image signal input to the mirror image conversion circuit to a constant reference level, is omitted and the circuit configuration is simplified, the same effect as the conventional one can be obtained. Therefore, the system configuration and the circuit scale can be simplified, and the cost can be reduced.

[0041]

As described above, according to the present invention, an image signal corresponding to an arbitrary image is converted into a mirror image signal corresponding to a mirror image of the image with a simple and low-cost structure. It becomes possible to provide an image signal processing device capable of processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image signal processing apparatus to which the present invention has been applied, as an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an image signal processing apparatus to which the present invention has been applied, as another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional mirror image conversion circuit.

FIG. 4 is a timing chart showing various control signals S1 to S5 output from the memory controller of FIG.

[Explanation of symbols]

 100 A / D Converter 101 Switch Circuit 102 Memory Circuit 103 Memory Circuit 104 Switch Circuit 105 Switch Circuit 106 D / A Converter 107 Memory Controller 108 Latch Circuit 109 Memory Controller

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 3/22 C 7037-5C

Claims (2)

[Claims] 1. Image signal input means for inputting an image signal, and conversion processing of the image signal input by the image signal input means into a mirror image image signal corresponding to a mirror image of the image indicated by the image signal. Then, the conversion processing means for outputting and the signal for the image period of the mirror image signal output from the conversion processing means during the image period of the image signal are output, and the image signal input during the blanking period of the image signal. An image signal processing device, comprising: an image signal output device for outputting a signal of a blanking period of the image signal input by the device. 2. An image signal input means for inputting an image signal, a holding means for holding a signal corresponding to a pedestal level of the image signal input by the image signal input means, and an input by the image signal input means. Conversion processing means for converting the image signal into a mirror image signal corresponding to a mirror image of the image represented by the image signal and outputting the converted image signal, and output from the conversion processing means during the image period of the image signal. Image signal output means for outputting a signal in the image period of the mirror image signal and outputting a signal corresponding to the pedestal level of the image signal held in the holding means during the blanking period of the image signal. An image signal processing device characterized by: