JPH05145423A - D/a conversion system - Google Patents

Abstract

PURPOSE:To attain the digital analog conversion with high accuracy and high S/N by smoothing an output of the FIR filter with a capacitor so as to obtain an analog signal and eliminating noise at the outside of a pass band caused by noise shaping in the process of the digital analog conversion thereby eliminating the need for a high-degree analog filter. CONSTITUTION:The system is provided with plural D flip-flop circuits f0-fn in cascade connection, plural resistors R0-Rn connecting respectively to the D flip-flop circuits f0-fn and a capacitor 12, and currents from the plural resistors R0-Rn are summed to form the analog FIR filter and the analog signal is obtained by using the capacitor 12 to smooth the output of the FIR filter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog conversion system suitable for application to, for example, a so-called 1-bit digital-analog conversion system in which 1-bit digital-analog conversion is performed by utilizing oversampling and noise shaping. ..

[0002]

2. Description of the Related Art Heretofore, a so-called 1-bit digital-analog conversion system has been proposed in which 1-bit digital-analog conversion is performed by utilizing oversampling and noise shaping.

FIG. 7 shows an example of this 1-bit digital-analog conversion system. An example of the conventional 1-bit digital-analog conversion system will be described below with reference to FIG.

In FIG. 7, reference numeral 1 denotes an input terminal to which a 16-bit digital signal is supplied, and the digital signal from the input terminal 1 is supplied to the oversampling digital filter 2.

The oversampling digital filter 2 samples the digital signal from the input terminal 1 at a frequency that is, for example, 2 to 8 times the sampling frequency, and the noise power in the audible band is routed from the route 1/2. Reduce to 1/8.

The 18-20 bit digital signal from the oversampling digital filter 2 is supplied to the noise shaper 3.

The noise shaper 3 is, for example, a requantization error at this time when a data string of 18 to 20 bits of a digital signal from the oversampling digital filter 2 is quantized into a data string of upper n bits. A certain lower (18-20-n) bit is fed back to the next input data to push the quantization noise to a higher frequency band and reduce it in the audible band.

As shown in FIG. 8, when noise shaping is performed, the quantization noise is 6 dB / o in the first order.
ct, 12 dB / oct in 2nd order, 1 in 3rd order
The noise power outside the audible band increases as the order increases to 8 dB / oct and 24 dB / oct in the fourth order, but the noise power within the audible band decreases and the S / N is improved.

When the digital signal from the noise shaper 3 is 1 bit, it is directly supplied to the 1-bit DA converter 5, and when it is 2 to 4 bits, it is supplied to the PWM converter 4 shown by a broken line. To be done.

The DA converter 5 converts the 1-bit digital signal from the noise shaper 3 into a pulse waveform of "1" or "0".

This conversion is performed by keeping the amplitude constant and changing the amplitude in the time axis direction.

The above-mentioned PWM (pulse width modulation) converter 4 converts a digital signal of 2 to 4 bits from the noise shaper 3 into time information, that is, turns on / off a reference voltage with time information to obtain a pulse width. Is converted into a 1-bit data string, and this 1-bit digital signal is converted into a 1-bit D-
It is supplied to the A converter 5.

The 1-bit D / A converter 5 switches the 1-bit digital signal from the noise shaper 3 or the PWM converter 4 at a frequency of, for example, 50 MHz to demodulate the signal, and outputs the demodulated signal to a high level. Output terminal 7 via next analog filter (low pass filter) 6
Supply to.

The analog filter 6 is a 1-bit DA.
The noise portion of the demodulated signal from the converter 5, that is, the noise outside the pass band concentrated in the high frequency range by the noise shaper 3, removes the digital-analog converted noise.

Conventionally, a digital signal is converted into an analog signal in this way.

[0016]

In the conventional digital-analog conversion system, the noise shaper 3 compresses the 18 to 20-bit digital signal from the oversampling digital filter 2 as described with reference to FIG. , The noise in the pass band is reduced and the necessary dynamic range is secured. However, noise outside the pass band causes an increase in the order of noise shaping by the noise shaper 3 and a decrease in the number of bits. It increases dramatically in proportion.

As described above, the signal in which the noise outside the pass band is drastically increased is directly in the case of 1 bit, and the signal of several bits is the signal of 1 bit in the PWM converter 4. After that, it is supplied to the 1-bit DA converter 5 and converted into an analog signal.

At this time, the noise outside the pass band, which is concentrated in the high frequency range by the noise shaper 3, is directly digital-analog converted by the DA converter 5, so it is necessary to remove this noise.

For this reason, the analog filter 6 in the subsequent stage of the 1-bit D / A converter 5 must be a high-order (6 to 7 or more) linearity up to about 10 MHz, for example.

However, the high-order analog filter 6
If used, both accuracy and S / N will be deteriorated.

As described above, in the conventional digital-analog conversion system, although the purpose of oversampling was to obtain high precision and high S / N by reducing the order of the analog filter, noise There has been a problem that a high-order analog filter that deteriorates accuracy and S / N must be used in order to remove noise outside the pass band generated by shaping.

The present invention has been made in view of the above point, and noise outside the pass band generated by noise shaping can be removed in the digital-analog conversion process, so that a high-order analog filter is not used. Therefore, the present invention intends to propose a digital-analog conversion system capable of performing digital-analog conversion with high accuracy and high S / N.

[0023]

The digital-analog conversion method of the present invention is, for example, as shown in FIGS. 1 to 6, a plurality of cascade-connected delay elements f0, f1, ... Fn.
, And a plurality of resistors R0, R1, ..., Rn respectively connected to the delay elements f0, f1, ..., Fn, from the plurality of resistors R0, R1 ,. Form an analog FIR filter by adding the currents of
The output of the FIR filter is smoothed to obtain an analog signal.

[0024]

According to the present invention described above, the output of the FIR filter is smoothed to obtain an analog signal, so that noise outside the pass band generated by noise shaping can be removed in the digital-analog conversion process. This eliminates the need for using a high-order analog filter, and makes it possible to perform digital-analog conversion with high accuracy and high S / N.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, referring to FIG.
An example of the analog conversion method will be described in detail.

FIG. 1 shows the principle of the digital-analog conversion system of this embodiment. In FIG. 1, 10 is, for example, 1
An input terminal into which a bit signal is input, and 11 is an input terminal into which a clock signal is input.

The input terminal 10 is connected to the data input terminal D of the D-type flip-flop circuit f0, and the output terminal Q of the D-type flip-flop circuit f0 is connected to the data of the second-stage D-type flip-flop circuit f1. The output terminal Q of the D-type flip-flop circuit f1 is connected to the input terminal D.
Is connected to the data input terminal D of the D-type flip-flop circuit f2 at the third stage, and the D-type flip-flop circuit f
The output terminal Q of No. 2 is connected to the data input terminal D of the D-type flip-flop circuit f3 at the fourth stage, ..., And the output of the D-type flip-flop circuit (not shown) at the (n-1) th stage The terminal Q is connected to the data input terminal D of the n-th stage D-type flip-flop circuit fn.

The input terminal 11 is connected to each clock signal input terminal CK of each D-type flip-flop circuit f0 to fn.

Further, as shown in this figure, the output terminal Q of the D-type flip-flop circuit f0 of the first stage is connected to one end of the resistor R0, and the D-type flip-flop circuit f of the second stage is connected.
1 rotation output terminal Q ″ (here, Q ″ means inverted output) is connected to one end of the resistor R1, and the output terminal of the third-stage D-type flip-flop circuit f2 is a resistor. It is connected to one end of R2, the inverting output terminal Q ″ of the fourth-stage D-type flip-flop circuit f3 is connected to one end of the resistor R3, ... The inverting output terminal Q ″ (not shown) is connected to the resistor Rn−.
1 (not shown), and the output terminal of the n-th stage D-type flip-flop circuit fn is connected to one end of the resistor Rn.

The other ends of the resistors R0 to Rn are connected to each other, and the connection point is connected to one power source (grounded) via the capacitor 12.

Further, as shown in this figure, the output terminal 13 is led out from the connection point of the resistors R0 to Rn and the capacitor 12.

Now, in this example, each of the resistors R described above is
The resistance values of 0 to Rn are made different from each other.

Therefore, these resistors R0 to Rn and D
Type flip-flop circuits f0 to fn for FIR (Fin
An item Impulse Response) filter is configured.

The so-called summing point (addition point) of this FIR filter is the connection point of the other ends of the resistors R0 to Rn.

Further, the 1-bit D / A converter is constituted by the D-type flip-flop circuit f0 of the first stage, the resistor R0 and the capacitor 12, and the D-type flip-flop circuit of the second stage is formed.
1 by flop circuit f1, resistor R1 and capacitor 12
A bit D-A converter is configured, and the third stage D-type flip-flop circuit f2, resistor R2, and capacitor 1
The 1-bit D-A converter is composed of 2 and the 4th stage D
-Type flip-flop circuit f3, resistor R3, and capacitor 12 constitute a 1-bit DA converter,
.. The 1-bit D-A converter is configured by the n-1 stage D-type flip-flop circuit (not shown), the resistor Rn-1 (not shown), and the capacitor 12,
D-type flip-flop circuit fn in the nth stage, resistor Rn
Also, the capacitor 12 constitutes a DA converter.

That is, in this example, as shown in FIG. 1, it operates as an FIR filter and performs digital-analog conversion.

FIG. 2 shows an embodiment based on the principle of the present embodiment shown in FIG. 1, which will be described below.

In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 2, for example, eight D-type flip-flop circuits f0 to f7 are connected in cascade.

That is, the input terminal 10 to which 1-bit data is supplied is connected to the data input terminal D of the D-type flip-flop circuit f0, and the D-type flip-flop circuit f0 is connected.
Of the D-type flip-flop circuit f1 is connected to the data input terminal D of the D-type flip-flop circuit f1.
Of the D-type flip-flop circuit f3, and the output terminal Q of the D-type flip-flop circuit f3 is connected to the data input terminal D of the D-type flip-flop circuit f3. Is connected to the data input terminal D of the D-type flip-flop circuit f4, and the output terminal Q of the D-type flip-flop circuit f4 is connected to the data input terminal D of the D-type flip-flop circuit f5. The output terminal Q of the flop circuit f5 is connected to the data input terminal D of the D-type flip-flop circuit f6, and the output terminal Q of this D-type flip-flop circuit f6.
Is a data input terminal D of the D-type flip-flop circuit f7
Connect to.

Then, the input terminal 11 to which the clock signal is supplied is connected to each clock input terminal CK of each D-type flip-flop circuit f0 to f7.

Further, one end of the resistor R0 is connected to the output terminal Q of the D-type flip-flop circuit f0, one end of the resistor R1 is connected to the output terminal Q of the D-type flip-flop circuit f1, and the D-type flip-flop is connected. .Output terminal Q of flop circuit f2
Is connected to one end of the resistor R2, and one end of the resistor R3 is connected to the output terminal Q of the D-type flip-flop circuit f3.
Resistor R at the output terminal Q of the flip-flop circuit f4
4, one end of the resistor R5 is connected to the output terminal Q of the D-type flip-flop circuit f5, and one end of the resistor R6 is connected to the output terminal Q of the D-type flip-flop circuit f6. Type flip-flop circuit f7 output terminal Q
Is connected to one end of the resistor R7.

Then, the other ends of these resistors R0 to R7 are connected, and the output terminal 1 is connected from the connection point (summing point).
3 is derived.

In this example, a case where analog demodulation is performed by a 1-bit FIR filtering digital-analog conversion circuit having a one-stage moving average filter configuration is shown.

Further, since the resistance values of the weighting resistors R0 to R7 are one-stage moving averages, they are the same.

FIG. 3 shows the amplitude characteristic of the moving average filter.

In FIG. 3, the vertical axis represents the amplitude characteristic (d
B), the horizontal axis represents frequency (kHz), and as shown in FIG. 3, the moving average filter has a comb-shaped characteristic.

Therefore, when a 1-bit digital signal as shown in FIG. 4A is input to the data input terminal D of the D-type flip-flop circuit f0 at the first stage of the 1-bit FIR filtering digital-analog conversion circuit shown in FIG.
The waveform as shown in FIG. 4B, which is obtained by integrating this from the output terminal 13, should be obtained.

When a 1-bit digital signal shown in FIG. 4A is input to the data input terminal D of the D-type flip-flop circuit f0 shown in FIG.
From the output terminal Q of the flop circuit f0, the signal of FIG.
A signal delayed by the clock as shown in FIG. 4C is output, and this signal is supplied to the data input terminal D of the D-type flip-flop circuit f1.

This D-type flip-flop circuit f
1 is supplied with the 1-bit delayed digital signal shown in FIG. 4C, the signal shown in FIG. 4C is delayed from the output terminal Q of the D-type flip-flop circuit f1 by one clock as shown in FIG. 4D. The signal is output.

The signal shown in FIG. 4D is input to the data input terminal D of the D-type flip-flop circuit f2, and further output from the output terminal Q of the D-type flip-flop circuit f2.
The signal shown in FIG. 4D is output as a signal as shown in FIG. 4E delayed by one clock.

The signal shown in FIG. 4E output from the output terminal Q of the D-type flip-flop circuit f2 is supplied to the data input terminal D of the D-type flip-flop circuit f3.
Further, the signal shown in FIG. 4E is delayed by one clock from the output terminal Q of the D-type flip-flop circuit f3.
A signal as indicated by F is output.

The signal shown in FIG. 4F output from the output terminal Q of the D-type flip-flop circuit f3 is input to the data input terminal D of the D-type flip-flop circuit f4, and further, the D-type flip-flop circuit f4. The output terminal Q of the flop circuit f4 outputs the signal shown in FIG. 4F as a signal as shown in FIG. 4G delayed by one clock.

The signal shown in FIG. 4G output from the output terminal Q of the D-type flip-flop circuit f4 is input to the data input terminal D of the D-type flip-flop circuit f5, and further, this D-type flip-flop circuit. The signal shown in FIG. 4G is output from the output terminal Q of the circuit f5 as a signal shown in FIG. 4H delayed by one clock.

The signal shown in FIG. 4H output from the D-type flip-flop circuit f5 is input to the data input terminal D of the D-type flip-flop circuit f6, and further,
The signal shown in FIG. 4H is output from the output terminal Q to the D-type flip-flop circuit f6 as a delayed signal as shown in FIG. 4I.

The signal as shown in FIG. 4I output from the output terminal Q of the D-type flip-flop circuit f6 is input to the data input terminal D of the D-type flip-flop circuit f7, and further, the D-type flip-flop circuit f7. The signal shown in FIG. 4I is output from the output terminal Q of the flop circuit f7 as a signal shown in FIG. 4J delayed by one clock.

Now, each D-type flip-flop circuit f0
The delayed signals shown in FIGS. 4C to 4J output from the output terminal Q of ~ f7 are supplied to the connection points (summing points) of the resistors R0 to R7 via the resistors R0 to R7 shown in FIG. 2, respectively. It

Therefore, the signal as shown in FIG. 4K is output to the output terminal 13 as the digital-analog conversion output terminal.

As shown in FIG. 4K, this output signal has a stepwise shape close to the signal (FIG. 4B) obtained by integrating the input signal shown in FIG. 4A, that is, passing through the low-pass filter.

Therefore, it can be seen that the 1-bit FIR filtering digital-analog conversion circuit shown in FIG. 2 has the characteristics of a low pass filter.

In an actual application, this 1-bit FI
R filtering The weighting of the resistors R0 to R7 and the number of taps (the number of D-type flip-flop circuits and resistors as a pair) and the weightings of the resistors R0 to R7 are changed according to the order of the noise shaper and the oversampling ratio of the preceding stage of the R-filtering digital-analog conversion circuit. It suffices to create a low-pass filter characteristic required to remove noise outside the pass band. Especially, the resistance values of the weighting resistors R0 to R7 are symmetrical with respect to the central tap of the cascaded D-type flip-flop circuits f0 to f7. In such a case, linear phase filtering like an FIR digital filter becomes possible.

Of course, since various FIR digital filter design tools can be used as they are for filter design,
The design of the filter portion of the 1-bit FIR digital-analog conversion circuit described above can be performed very easily.

Now, if the connection points of the resistors R0 to R7 are grounded via a capacitor as in the case of FIG. 1, an analog signal as shown in FIG. 4L can be obtained.

Next, another example 1 of the digital-analog conversion system of this example will be described with reference to FIG.

In FIG. 5, parts corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 5, the D-type flip-flop circuits f0 to fn and the resistors R0 to Rn are connected in the same manner as in FIG. 1, and the output of the connection point (summing point) of the resistors R0 to Rn is further made. Is output via an amplifier circuit to form a current output amplifier circuit, and the weighting resistors R0 to Rn are entirely scaled.

That is, the connection point of the resistors R0 to Rn is
This current / voltage is connected to the inverting input terminal (−) of the voltage conversion circuit 15 and the non-inverting input terminal (+) of this current / voltage conversion circuit 15 is grounded via a reference voltage source 16 of, for example, 2.5V. The output terminal 13 is derived from the output terminal of the conversion circuit 15, and the inverting input terminal (-) of this current / voltage conversion circuit 15 is derived.
Is connected to one end of a parallel circuit of the capacitor 14 and the resistor Rf, and the output terminal of the current / voltage conversion circuit 15 is connected to the other end of the parallel circuit of the capacitor 14 and the resistor Rf.

In this way, the output signals from the D-type flip-flop circuits f0 to fn are output from the resistors R0 to Rn.
4L, is taken out as a current to the current / voltage conversion circuit 15, and further converted into an analog signal as shown in FIG. 4L by the current / voltage conversion circuit 15 and output from the output terminal 13.

The current value at the connection point of the resistors R0 to Rn is Ix
When the resistance value of the resistor Rf is rf and the output voltage from the output terminal 13 is V0, the output voltage V0 is the current value I
It is the product of x multiplied by the resistance value rf and the voltage of the reference voltage source 16 of 2.5 V added thereto.

That is, the amplitude of the output voltage V0 output from the output terminal 13 is determined by the resistance value rf of the resistor Rf centering on the voltage 2.5V output from the reference voltage source 16.

Therefore, in this example, by adopting the current output type, an arbitrary output voltage can be obtained by the current / voltage conversion circuit 15 in the subsequent stage, and a high S / N can be secured.

FIG. 6 shows another example 2 of the digital-analog conversion system of this example, which will be described below.

In FIG. 6, parts corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

That is, in FIG. 6, a network of weighting resistors R0 'to Rn' is further added to the circuit shown in FIG. 1, and the signal output from the connection point of the resistors R0 to Rn and the resistor R0 'are added. The differential output of the signal output from the connection point of ~ Rn 'is obtained. At this time, R1 =
R1 ′, R2 = R2 ′, ... Rn = Rn ′.

That is, as in the case of FIG. 1, the D-type flip-flop circuits f0 to fn are connected in cascade, and the inverting output terminal Q "of the D-type flip-flop circuit f0 is connected to one end of the resistor R0 ', and D Type flip-flop circuit f
1 is connected to one end of a resistor R1 ′, one end of a resistor R2 ′ is connected to an inverting output terminal Q ″ of a D-type flip-flop circuit f2, ... Inverted output terminal Q ″ of fn−1 (not shown)
Connect one end of resistor Rn-1 (not shown) to
One end of the resistor Rn ′ is connected to the output terminal Q of the D-type flip-flop circuit fn.

The other ends of the resistors R0 'to Rn' are connected to each other, and this connection point is connected to the amplifier circuit 17 via the voltage dividing resistor Ra.
Is connected to the non-inverting input terminal (+) of the amplifier, the connection point of the resistors R0 to Rn is connected to the inverting input terminal (-) of the amplifier circuit 17 via the resistor Rc, and the output terminal of the amplifier circuit 17 outputs. The terminal 13 is led out, and the resistor Rd is provided between the inverting input terminal (-) of the amplifier circuit 17 and the output terminal of the amplifier circuit 17.
And the non-inverting input terminal (+) of the amplifier circuit 17 is grounded via the resistor Rb.

At this time, for example, the resistors Ra and Rc have the same resistance value, and the resistors Rb and Rd have the same resistance value.

Now, the signal from the connection point of the resistors R0 to Rn becomes the signal as shown in FIG. 4K, and the resistors R0 'to Rn.
The signal from the connection point of n'is an inverted signal of the signal as shown in FIG. 4K.

Then, an analog signal as shown in FIG. 4L is obtained as a differential output of these two signals. At this time, the asymmetry of the waveform due to the difference in response speed between the P channel and the N channel of the semiconductor element is obtained. Can be canceled.

Therefore, the P channel and N of the semiconductor device are
It is possible to significantly reduce the distortion and noise of the output signal due to the asymmetry of the waveform due to the difference in the response speed between the channels.

The present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0082]

According to the present invention described above, the output of the FIR filter is smoothed to obtain an analog signal, so that noise outside the pass band caused by noise shaping can be removed in the digital-analog conversion process. By doing so, it is not necessary to use a high-order analog filter, and it is possible to perform digital-analog conversion with high accuracy and high S / N.
The weighting of the resistance corresponding to the coefficient is sufficient as long as the relative accuracy can be obtained, so that there is an advantage that the IC can be easily formed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing the principle of an embodiment of a digital-analog conversion system of the present invention.

FIG. 2 is a configuration diagram showing an embodiment of a digital-analog conversion system of the present invention.

FIG. 3 is an example of amplitude characteristics of a moving average filter used for explaining one embodiment of the digital-analog conversion system of the present invention.

FIG. 4 is a timing chart for explaining an embodiment of the digital-analog conversion system of the present invention.

FIG. 5 is a configuration diagram showing another example 1 of the digital-analog conversion system of the present invention.

FIG. 6 is a configuration diagram showing another example 2 of the digital-analog conversion system of the present invention.

FIG. 7 is a configuration diagram showing an example of a conventional 1-bit digital-analog conversion method.

FIG. 8 is a graph showing characteristics of noise shaping.

[Explanation of symbols]

f0, f1, f2, f3, ... Fn D-type flip-flop circuit R0, R1, R2, R3, ... Rn resistor 12 capacitor

Claims (1)

[Claims] 1. An analog FIR filter having a plurality of delay elements connected in cascade and a plurality of resistors respectively connected to the delay elements, and adding currents from the plurality of resistors to form an analog FIR filter. A digital-analog conversion system characterized in that an analog signal is obtained by smoothing the output of the FIR filter.