JPH05143463A - Cache memory device - Google Patents

Abstract

PURPOSE:To provide the cache memory device which shortens valid access time and has high performance even in the case of increasing the cache error ratio of a microprocessor, etc., fetching a cache memory into one chip. CONSTITUTION:When data required for a CPU 1 do not exist in a 1st cache memory 3, the required data are exchanged from a 2nd cache memory 7 and between the 1st cache memory 3 and the 2nd cache memory 7, however, address latches 4 and 6 are provided to hold addresses designating the required data. Since the addresses held in these address latches 4 and 6 are read in a memory made empty by completely transferring the addresses of the next required data in a clock cycle to transfer those address to the low-order memory, the new exchange is started before the preceding exchange is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic computer device, and more particularly to a cache memory device for speeding up.

[0002]

2. Description of the Related Art In a normal cache memory, when a cache miss occurs, as shown in FIG.
Once the execution of the computer was interrupted, the necessary data was fetched into the cache and the execution was reproduced. In that case, since there were many cases where data near that was also needed, usually multiple clocks were used to capture multiple data at the same time. A cache memory adopting this method has a structure shown in FIG. 4A, for example, and first, when reading the cache memory, an address is given and 1s
The t cache memories 42 and 43 are accessed. If a mistake is made here, the second cache memory 45 is accessed to refill the data. The refill control unit 44 performs control to continuously capture a plurality of data. This scheme works well when the cache miss rate is low. This relationship is expressed by the following equation. Ne = (1-Km) * Ca + Km * Cc

Incidentally, Ne is an effective memory access time (clock number) and indicates the performance of the cache memory. Km is the miss rate of the cache memory, and this value changes depending on the size of the cache memory, the nature of the problem, and the like. Further, Ca is an access time (clock number) when the cache memory is hit, and Cc is a time (clock number) required to replace the cache memory. In the normal case, C
Since a is 1, Cc is about 10, and Km is about 1% to 5%, Ne is about 1.1 to 1.5 (clock).
This value is 2 when the normal cache memory is not used.
Since the value is sufficiently small compared to about 3 (clock), there is an effect of using the cache memory.
However, depending on the problem, there are cases where the cache miss rate becomes extremely high. In such a case, Ne becomes large and the cache memory may not be effective, but may be deteriorated. In the case where the cache miss rate is extremely high, it is necessary to deal with the problem that the size of the cache memory cannot be so large and the amount of data used is large in order to develop a microprocessor that includes the cache memory. It is becoming more and more noticeable.

[0004]

As described above, in the conventional cache memory system, the increase of the cache miss rate immediately leads to the increase of the effective access time. In some cases, it is rather harmful and hinders the performance improvement of the microprocessor incorporating the cache memory in one chip.

The present invention has been made in view of the above circumstances, and an object thereof is to enable the calculation to continue without stopping the computer even if a miss occurs and the cache miss rate is high. Another object is to provide a cache memory device that can obtain high performance.

[0006]

In the cache memory device according to the present invention, the data required by the electronic computer is 1st.
If it does not exist in the cache memory, it is provided with a means for replacing the required data from the 2nd cache memory or the main memory, and the replacement of the data from the 2nd cache or the main memory is performed before the previous replacement is completed. It is characterized by starting a new replacement.

Further, in this cache memory device, at least one of the first cache memory, the second cache memory, and the main memory is provided with a holding means for holding an address designating required data, and this holding means is provided. It is characterized in that the determination as to whether or not the required new data exists in the 1st cache memory is started at the clock cycle for transferring the address held in the means to the 2nd cache memory or the main memory.

[0008]

[Operation] When a mistake occurs, do not stop the computer immediately,
The calculation is continued until the read data is actually needed, and the data in the cache is replaced.However, the next replacement can be started in a pipeline without waiting for the completion of the data replacement. It is possible to prevent the computer from stopping even if the continuous occurrence occurs.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a cache memory device according to an embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the apparatus of this embodiment. The square next to this indicates one clock.

First, when reading the cache memory,
The CPU 1 gives an address to access the 1st cache memory. If there is a hit, the data read from the data section 3 of the 1st cache is used, so that the same operation as a normal cache memory is performed. The operation is to check the data part 3 and the tag memory part 2 at the same time,
If the tag memory unit 2 and the input address match, it is a hit, and the result of the data unit 3 is correct. In this case, the data can be accessed in one clock. This is shown in FIG. 2A.

FIG. 2B shows a state of the operation when there is a miss in the 1st cache memory. At clock (2),
If you see a miss in the 1st cache memory, the clock
At (3), the address to be read, which is held in the address latch 4, is output to the outside of the chip 13, and at the clock (4), the tag memory unit 5 of the 2nd cache is accessed. At the clock (5), after confirming a hit there, the address held in the address latch 6 is output. Then, at the clock (6), the data portion 7 of the second cache is accessed with this address.
The data read there is at clock (7)
Passed to the 1st cache via the data latch 8 and 1s
The tag memory unit 2 and the data unit 3 of the t-cache are replaced and data is also sent to the CPU. This data can be used by the CPU 1 after the clock (8), that is, C
This means that the 7th clock or later after PU1 issues the cache memory read address.

These series of operations are performed by the address latch 4, the address latch 6, which holds the intermediate result of each stage.
Due to the presence of the data latch 8 (which is not necessary), it can be pipelined as shown in FIG. Even if the 1st cache memory misses as shown in FIG. 2B, the processing of the CPU is not interrupted, and the next read C is started while continuing the refilling of the missed B in the 1st cache at the next clock. Therefore, compared with the conventional method in which the next read C is started after the refill of B is completed, the time from the start of the read of B to the completion of the read of C is simply halved. Become. That is, according to the present embodiment, even if a miss occurs, the processing progresses every clock, and even if a miss occurs in the 1st cache, the performance of the cache memory does not deteriorate.

However, as shown in FIG. 3A, if the data is desired immediately, the validity of the processing cannot be guaranteed unless the computer is stopped at that time, and the computer is stopped, and the effect of the present invention is obtained. Since it will decrease, in the compiler,
It is necessary to optimize as shown in FIG. That is,
1st after executing the instruction "1d r1, (A)" (read the data of address A into register r1)
In the case of a miss in the cache, it is the 7th clock that can be read, so the actual use of r1 is "add r3, r
The instruction “2, r1” must be placed after the seventh instruction, counting the previous instruction as the first instruction. Between these two instructions, there is no relation with the register r1 and the context of the latter instruction is not specified. Other instructions (shown as etc in the figure) should be placed. If the optimization as shown in FIG. 3 (b) is always possible, the 1st cache is unnecessary, but there are cases where optimization cannot be performed (other harmless instructions cannot be placed). The cache is effective. This is 1 if the 1st cache hits
This is because the data can be read at the clock and the processing of the CPU does not stop even if optimization is not possible. Incidentally, FIG.
If the optimization as in (b) is possible, the existence of the 1st cache does not interfere.

Next, the write operation will be described.
The CPU 1 gives the address and the data to the tag memory unit 2 and the data unit 3 of the 1st cache, respectively, and if the addresses input to the tag memory unit 2 match, a hit occurs and the data sent to the data unit 3 is written as it is. In this case, data can be written in 1 clock. This is shown in FIG. 2E.

When there is a miss in the 1st cache memory, the writing of data in the data section 3 is stopped.
The normal write operation is done in the second half of the clock, and
Since the st cache is in the chip and it takes almost no signal transmission time, writing can be stopped even after it is recognized as a miss. The state of the operation in the case of a miss is shown in FIG. 2D. At clock (4), if it is found to be a miss in the 1st cache memory, at clock (5), the address to be written held in address latch 4 is output to outside chip 13 and held in data latch 9. The stored data is put out of the chip 13.
At the clock (6), the tag memory unit 5 of the second cache is accessed and the data is latched by the data latch 10.
Transfer to. In the clock (7), after confirming the hit there, the address held in the address latch 6 and the data held in the data latch 10 are output, and the clock (8) outputs the second cache data unit 7 Write data to the specified address. Also, when a hit is made in the 1st cache, the above operation is performed when the data is written in the 1st cache and the data is written back to the 2nd cache in order to maintain the consistency of the data.

Here, the function of the memory management unit 11 will be described. Since the order of reading the memory changes depending on the hit or miss of the cache, it is possible that the result of reading the subsequent instruction may be obtained first. However, this phenomenon does not pose a problem by pulling the memory management unit in advance or at the same time when accessing the cache memory to guarantee the validity of the access. The memory management unit stores the virtual address seen by the CPU and the real address on the memory (here, the 2nd cache) in association with each other. The memory management unit 11 is the CPU 1
If there is no real address corresponding to the address issued by, the information is detected as an exceptional condition and this information is sent to the CPU before data is obtained or before writing. The apparatus of this embodiment is sufficiently effective even in a computer capable of simultaneously executing a plurality of load and store instructions, which requires a plurality of data at the same time. In other words, since the probability that the 1st cache misses at the same time is low, there are few data items that need to be refilled from the 2nd cache out of a plurality of pieces of data to be read, and even if there is only one port for the 2nd cache, there is almost no deterioration in performance. .. Of course, for such a large data set, if two or more refill systems (each traffic light in FIG. 1) from the 2nd cache are prepared and a plurality of refills are started at the same time, the speed is further increased. It is clear that is possible.

The present invention also uses a first cache and a second cache.
The present invention is not limited to cache and can be applied to various memory configurations. For example, the configuration in which the 2nd cache of the above-described embodiment is replaced with the main memory also has the configuration of
A configuration for performing the same refill as described above between the nd cache and a main memory (not shown) as well as a configuration for performing refill from the lower memory to the upper memory in the same manner as described above can be realized. Further, the 1st cache of the above embodiment may exist outside the chip.

Further, the timing of refilling does not have to be for each clock. That is, part or all of the operation performed in one clock in the above embodiment may be performed in a plurality of clocks. In the second cache, the tag is first pulled before the data is pulled, but the second cache can also be pulled at the same time. In that case, the address latch 6 and the data latch (8,) 10 are not necessary, and the data can be read at the fifth clock. In this configuration, it is necessary to be careful when writing. As in the case of the 1st cache, writing to the data section can be stopped when the tag section of the 2nd cache is found to be a miss, or access to the 2nd cache can also be accessed at the 1st section of FIG. 1 when reading data. A signal flow similar to that for accessing the cache is taken, and a signal flow as in FIG. 1 is taken when writing data.

In other words, according to the present invention, since the calculation can be continued even when a cache miss occurs, the performance is not deteriorated by optimizing the pipeline processing even if the miss rate is high, and the optimization cannot be performed. Even in the case, if the 1st cache is effective, a cache memory device that can exhibit high performance can be realized.

[0021]

As described above, according to the present invention, even when the cache miss rate is high, such as when the size of the 1st cache is small, the effective access time does not increase and is high. There are practically great effects such as realization of a cache memory device capable of maintaining performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the operation timing of the apparatus of this embodiment.

FIG. 3 is a diagram showing an example of a program executed by the device of this embodiment.

FIG. 4A is a block diagram of a conventional cache memory device and FIG. 4B is a diagram showing operation timing.

[Explanation of symbols]

1, 41 ... CPU, 2, 42 ... 1st cache tag memory section, 3, 43 ... 1st cache data section, 4, 6
... address latch, 5 ... 2nd cache tag memory section, 7 ... 2nd cache data section, 8, 9, 10 ... data latch, 11 ... memory management section, 12, 44 ... refill control section, 13 ... chip, 45 ... 2nd cache

Claims (2)

[Claims] 1. A cache memory device comprising means for replacing the target data from a lower cache memory or a main memory when the target data does not exist in the higher cache memory, and the lower cache or The cache memory device is characterized in that the replacement of data from the main memory starts a new replacement before the completion of the previous replacement. 2. The cache memory device according to claim 1, further comprising holding means for holding an address designating target data between the upper cache memory and the lower cache memory or the main memory. A cache characterized by starting a judgment as to whether or not new target data exists in the upper cache memory in a clock cycle for transferring the address held in the holding means to the lower cache memory or the main memory. Memory device.