JPH0512712B2 - - Google Patents

Info

Publication number
JPH0512712B2
JPH0512712B2 JP62119420A JP11942087A JPH0512712B2 JP H0512712 B2 JPH0512712 B2 JP H0512712B2 JP 62119420 A JP62119420 A JP 62119420A JP 11942087 A JP11942087 A JP 11942087A JP H0512712 B2 JPH0512712 B2 JP H0512712B2
Authority
JP
Japan
Prior art keywords
conductive layer
powder
conductive
chip
isotropic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62119420A
Other languages
Japanese (ja)
Other versions
JPS63284591A (en
Inventor
Junichi Okamoto
Kazuyuki Shimada
Tatsufumi Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62119420A priority Critical patent/JPS63284591A/en
Publication of JPS63284591A publication Critical patent/JPS63284591A/en
Publication of JPH0512712B2 publication Critical patent/JPH0512712B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Description

【発明の詳細な説明】[Detailed description of the invention]

産業上の利用分野 本発明は表示パネルモジユールに関するもので
ある。 従来の技術 透明電極(以下ITOという)が形成された2枚
のガラス板からなる表示パネル(例えば液晶パネ
ル)に駆動用の半導体装置(以下チツプという)
を実装する場合は、ITO電極上にメタライズする
とともにチツプのアルミ電極パツドにもハンダバ
ンプを形しなければならなかつた。これら両者の
接続はチツプのアルミパツド上に設けられたハン
ダバンプによつて、いわゆるハンダ付けによるも
のである。 発明が解決しようとする問題点 従つてITOのように金属酸化物導電膜上にはハ
ンダ付けできない。そのためITO上にはハンダ付
けを可能とするためクロム−金やクロム−ニツケ
ルなどによるメタライズ処理をしなければならな
い。 一方、チツプのアルミパツド部にハンダバンプ
を設けるためには、クロムさらに銅の薄膜上にハ
ンダメツキまたはすずメツキと鉛メツキの二層を
施さなければならない。 このように液晶パネルの引出し電極であるITO
上へチツプを実装するためにはITOのメタライズ
やチツプのアルミパツド部へのバンプ形成など複
雑なプロセスが必要であり、歩どまりの低下、製
品コストのアツプなど多くの問題点を有する。本
発明はITO膜をメタライズ処理することなく表示
パネルへ半導体チツプを実装した安価な表示パネ
ルモジユールを提供することを目的とする。 問題点を解決するための手段 本発明は電極パツド部が光硬化性樹脂と導電性
粉体の等方性導電層からなる半導体装置を光硬化
性樹脂と導電性ゴム粉体からなる異方性導電層に
て透明引出し電極部に接続したものである。 すなわち、等方性導電層はチツプのアクテイブ
エリアが回路基板に接しないように適当なギヤツ
プを設けるために必要であり、異方性導電層はチ
ツプ固定と垂直方向の導電性とチツプ全面の保護
の役を持つものである。 作 用 以上の構成によつて、等方性導電層と回路基板
の電極間とに異方性導電層に含有する導電ゴム粉
末が狭み込まれ垂直方向に導通し、さらに導電粉
末はゴム特性を有しているため、樹脂の収縮に対
しても対応できる信頼度の高い導通を得ることが
でき、また異方性導電層の光硬化性樹脂は、チツ
プを回路基板に固定する役を果す。 実施例 以下、本発明の実施例について説明する。 等方性導電層は、感光性を有する樹脂、例えば
エポキシアクリレート系樹脂、感光性ポリイミド
系樹脂等が使用できる。導電性粉体はニツケル粉
に金コートしたものが使用できる。金コートなし
のものは、接触抵抗の増大をまねき導体としての
役目をはたさない。等方性導電層とは、光硬化性
樹脂と導電粉末からなるペーストを被膜としたと
き水平、垂直方向に同じ導電性を示すことをい
い、異方性導電層とは樹脂と導電粉末からなり、
導電粉末が前記等方性導電膜層のそれとは少なく
含有しており、被膜とした後、圧着することによ
つて垂直方向(厚み方向)に導電性を有するもの
で水平方向には導電粉末が少なく導電性を有しな
いものである。 異方性導電層は、光硬化性樹脂として例えば、
一成分形の液状シリコンゴムが使用できる。導電
性ゴムは、例えばシリコンゴムにカーボン粉末を
分散さし、硬化されたのちに、粉砕し、粉末状に
したものが使用できる。 以下、具体例について述べる。等方性導電層の
材料として以下の配合で塗料(ペースト)化し
た。
INDUSTRIAL APPLICATION FIELD The present invention relates to a display panel module. Conventional technology A display panel (for example, a liquid crystal panel) consisting of two glass plates on which transparent electrodes (hereinafter referred to as ITO) are formed, and a driving semiconductor device (hereinafter referred to as a chip)
When mounting this, it was necessary to metalize the ITO electrode and also form solder bumps on the aluminum electrode pad of the chip. These two connections are made by so-called soldering using solder bumps provided on the aluminum pads of the chips. Problems to be Solved by the Invention Therefore, soldering cannot be performed on a metal oxide conductive film like ITO. Therefore, ITO must be metallized with chrome-gold or chrome-nickel to enable soldering. On the other hand, in order to provide solder bumps on the aluminum pad portion of a chip, it is necessary to apply solder plating or two layers of tin plating and lead plating on a thin film of chromium and copper. In this way, ITO, which is the lead electrode of a liquid crystal panel,
Mounting the chip upward requires complex processes such as metallizing the ITO and forming bumps on the aluminum pad of the chip, which poses many problems such as lower yields and increased product costs. An object of the present invention is to provide an inexpensive display panel module in which a semiconductor chip is mounted on a display panel without metallizing the ITO film. Means for Solving the Problems The present invention provides a semiconductor device in which the electrode pad portion is made of an isotropic conductive layer made of a photocurable resin and conductive powder. It is connected to a transparent lead-out electrode section through a conductive layer. In other words, the isotropic conductive layer is necessary to provide a suitable gap so that the active area of the chip does not touch the circuit board, and the anisotropic conductive layer is necessary to secure the chip, provide vertical conductivity, and protect the entire surface of the chip. It has the role of Effects With the above configuration, the conductive rubber powder contained in the anisotropic conductive layer is sandwiched between the isotropic conductive layer and the electrodes of the circuit board and conductive in the vertical direction, and the conductive powder has rubber properties. , it is possible to obtain highly reliable conduction that can withstand resin shrinkage, and the photocurable resin of the anisotropic conductive layer plays the role of fixing the chip to the circuit board. . Examples Examples of the present invention will be described below. For the isotropic conductive layer, a photosensitive resin such as an epoxy acrylate resin, a photosensitive polyimide resin, etc. can be used. As the conductive powder, nickel powder coated with gold can be used. Those without gold coating increase contact resistance and do not function as conductors. An isotropic conductive layer is a film that exhibits the same conductivity in the horizontal and vertical directions when a paste made of a photocurable resin and a conductive powder is used as a coating.An anisotropic conductive layer is a layer made of a resin and a conductive powder. ,
The conductive powder is contained in a smaller amount than that of the isotropic conductive film layer, and after being formed into a film, it is compressed to have conductivity in the vertical direction (thickness direction), and the conductive powder in the horizontal direction. It has little electrical conductivity. The anisotropic conductive layer is made of photocurable resin such as
One-component liquid silicone rubber can be used. The conductive rubber that can be used is, for example, silicone rubber in which carbon powder is dispersed, hardened, and then crushed to form a powder. A specific example will be described below. The material for the isotropic conductive layer was made into a paint (paste) with the following formulation.

【表】 〓東芝シリコン(株)導電性ミラブ〓
導電性ゴム粉末
[Table] 〓Toshiba Silicon Corporation Conductive Mirab〓
conductive rubber powder

Claims (1)

【特許請求の範囲】 1 電極パツド部が光硬化性樹脂と導電性粉体の
等方性導電層からなる半導体装置が光硬化性樹脂
と導電性ゴム粉体からなる異方性導電層にて透明
引出し電極部に接続されたことを特徴とする表示
パネルモジユール。 2 等方性導電層の導電粉体がニツケル粉に金コ
ートしたものであることを特徴とする特許請求の
範囲第1項記載の表示パネルモジユール。
[Scope of Claims] 1. A semiconductor device in which the electrode pad portion is made of an isotropic conductive layer made of a photocurable resin and conductive powder is formed by an anisotropic conductive layer made of a photocurable resin and conductive rubber powder. A display panel module characterized by being connected to a transparent lead-out electrode section. 2. The display panel module according to claim 1, wherein the conductive powder of the isotropic conductive layer is nickel powder coated with gold.
JP62119420A 1987-05-15 1987-05-15 Display panel module Granted JPS63284591A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62119420A JPS63284591A (en) 1987-05-15 1987-05-15 Display panel module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62119420A JPS63284591A (en) 1987-05-15 1987-05-15 Display panel module

Publications (2)

Publication Number Publication Date
JPS63284591A JPS63284591A (en) 1988-11-21
JPH0512712B2 true JPH0512712B2 (en) 1993-02-18

Family

ID=14761018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62119420A Granted JPS63284591A (en) 1987-05-15 1987-05-15 Display panel module

Country Status (1)

Country Link
JP (1) JPS63284591A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2893070B2 (en) * 1989-09-01 1999-05-17 株式会社 半導体エネルギー研究所 Liquid crystal electro-optical device
US5130833A (en) 1989-09-01 1992-07-14 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal device and manufacturing method therefor

Also Published As

Publication number Publication date
JPS63284591A (en) 1988-11-21

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