JPH05121748A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a semiconductor device suitable for speedup and to enhance the integration degree by a method wherein source layers, channel layers and drain layers are formed in the vertical direction and gate electrode lead-out parts are respectively formed on the sidewalls of the channel layers in such a way that they are connected with these sidewalls. CONSTITUTION:N-type diffused layers 21, source layers 22, channel layers 23 and drain layers 24 are formed in order on a P-type silicon substrate 20 in the vertical direction, drain electrodes 31 are respectively provided on these layers 24 and gate electrode lead-out parts 28 are respectively formed on the sidewalls of the layers 23 in such a way that they are connected with the sidewalls via each gate oxide film 26. Gate electrodes 27 are respectively provided on these lead-out parts 28, the layer 21 in contact with the lower part of the layer 22 is extended in the lateral direction by a necessary amount, a source electrode lead-out part 29 consisting of a polysilicon film is formed on the extended part of the layer 21 and a source electrode 30 is provided thereon. Accordingly, as a semiconductor device is formed into a transistor of a vertical MOS structure, the degree of integration of the device can be raised and the operation speed of the device is easily increased by making thin the layers 21, 22, 23 and 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a vertical MOS structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional MOS transistor, as shown in FIG. 6, the operating regions of the elements are arranged in the lateral direction. That is, a source region 2 and a drain region 4 having a high impurity concentration are laterally formed on the semiconductor substrate 1 at a predetermined interval, and a channel region 8 is formed between the source region 2 and the drain region 4. A source electrode 5 is provided on the source region 2 and a drain electrode 7 is provided on the drain region 4. Further, the gate electrode extraction portion 3 is provided on the channel region 8 via the gate oxide film 9, and the gate electrode 6 is provided thereon. The electrodes 5, 6 and 7 are insulated by the insulating film 10.

Scale-down (also referred to as scaling) is known as a technique for achieving high integration in the MOS transistor having the above structure. This scaling means device dimensions (channel length, channel width, junction depth, lateral diffusion distance, gate oxide film thickness)
As a general rule, all are set to 1 / K of the original size to speed up,
It is to cope with high integration.

[0004]

However, since the higher the degree of integration, the finer the processing is required for the scaling, the manufacturing cost is high and the manufacturing cost is high in order to adapt to the so-called submicron level. The process becomes complicated. In particular, in the conventional MOS transistor, the operating region of the device (source, channel (gate),
Since the drain) is arranged in the lateral direction, even if the self-alignment method is used for high integration,
It is difficult to accurately control the dimensions between them.

In view of the above, the present invention is based on a completely new viewpoint, has a novel structure, a low manufacturing cost, and a simple manufacturing process, and is suitable for high speed and high integration. And a method for manufacturing the same.

[0006]

According to another aspect of the present invention, there is provided a semiconductor device in which a source layer, a channel layer and a drain layer which function as an operation region of a semiconductor element are vertically formed on a semiconductor substrate. The gate electrode extraction part for extracting the gate electrode through the gate oxide film on the side wall of
It is formed so as to be connected to the channel layer.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein a plurality of gate electrode lead-out portions are provided for a channel layer of one semiconductor element, and each gate electrode lead-out portion has a gate electrode. It is provided. A semiconductor device according to a third aspect is the semiconductor device according to the second aspect, wherein a diffusion layer is formed in contact with the source layer, the diffusion layer is laterally extended as much as necessary, and the extended diffusion layer upper portion is formed. A source electrode lead-out portion for taking out the source electrode is formed on the.

A semiconductor device according to a fourth aspect is the semiconductor device according to any one of the first to third aspects, wherein the semiconductor substrate is a silicon substrate, and the source and drain layers are silicon.
The channel layer is made of silicon carbide. According to a fifth aspect of the present invention, in the method for manufacturing a semiconductor device, the step of forming an oxide film on a semiconductor substrate, the oxide film is masked while leaving a semiconductor element operation region, and impurities are diffused to form a diffusion layer on the semiconductor substrate. Step, removing the oxide film in the operating region to expose the diffusion layer and growing the remaining oxide film in the vertical direction, continuously changing the source gas, the source layer, the channel layer and the drain layer on the diffusion layer. In the vertical direction, removing the oxide film growth layer in the gate electrode extraction region,
The sidewalls of the source layer, the channel layer, and the drain layer are exposed, and the source layer, the channel layer, and the drain layer are oxidized, thereby forming an insulating film on the sidewalls of the source layer and the drain layer.
Forming a gate oxide film on the side wall of the channel layer, depositing polysilicon on the gate electrode extraction region, and forming a gate electrode extraction portion so as to connect to the channel layer through the gate oxide film, source electrode Removing the oxide film growth layer on the extraction region to expose the diffusion layer, depositing polysilicon on the diffusion layer to form a source electrode extraction portion,
In addition, a step of forming a gate electrode on the gate electrode extraction portion, a source electrode on the source electrode extraction portion, and a drain electrode on the drain electrode extraction portion are provided.

A method of manufacturing a semiconductor device according to claim 6 is
The method of manufacturing a semiconductor device according to claim 5 is characterized in that the step of forming the gate electrode extraction portion and the step of forming the source electrode extraction portion are performed simultaneously.

[0010]

According to the semiconductor device of the first aspect, the source layer, the channel layer, and the drain layer are vertically formed on the semiconductor substrate to form a vertical MOS structure semiconductor device. As described above, high integration can be achieved without considering a margin and providing a margin. Further, by thinning the source layer, the channel layer and the drain layer, the speed can be easily increased.

According to another aspect of the semiconductor device of the present invention, since the semiconductor element operating region has a vertical structure, it is possible to provide a plurality of gate electrodes for one semiconductor element, and gate electrodes for one semiconductor element. By providing a plurality of electrodes, a logic circuit or the like can be formed with a small number of semiconductor elements. According to another aspect of the semiconductor device of the present invention, the diffusion layer in contact with the source layer is laterally extended as much as necessary, and the source electrode extraction portion is formed on the extended diffusion layer. Can be arranged in three directions with respect to the operating region of, and if these three gate electrodes are OR inputs,
An OR circuit can be formed with one semiconductor element.

According to another aspect of the semiconductor device of the present invention, the source layer and the drain layer are formed of silicon, and the channel layer is formed of silicon carbide. Due to the difference in the oxidation rates of silicon and silicon carbide, the gate oxide film is changed to the source layer and drain layer. Since it can be made thinner than the insulating film that insulates the gate electrode extraction portion, the semiconductor element can be operated at a low voltage.

In the manufacturing method of the fifth aspect, since the source layer, the channel layer and the drain layer are formed while changing the material gas in the operation region forming step, the source-channel-
The drain layer can be formed in a single process by the CVD method, which leads to simplification of the manufacturing process. According to the manufacturing method of the sixth aspect, since the gate electrode lead-out portion forming step and the source electrode lead-out portion forming step are simultaneously performed, the electrode lead-out portion forming step is greatly simplified.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view showing the positional relationship of source, drain, and gate electrodes with respect to the central transistor of FIG. 1, and FIG. 4 is a circuit diagram showing an example of a logic circuit obtained when the electrodes are arranged as shown in FIG.
FIG. 5 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 5 is a diagram showing a manufacturing process after that shown in FIG.

The semiconductor device of this embodiment shown in FIG.
A section of an S-type transistor having a novel vertical structure is shown on the left side and the center of the figure, and a source electrode lead-out portion for the central transistor is shown on the right side. As shown in FIG. 1, this vertical MOS transistor has an N-type diffusion layer 2 on the P-type silicon substrate 20, which acts as a conductive region to the source layer 22.
1, a source layer 22 made of N-type silicon (Si), a channel layer 23 made of P-type silicon carbide (SiC), and a drain layer 24 made of N-type silicon are sequentially formed in the vertical direction.

A gate oxide film 26 is formed on the side wall of the channel layer 23, and a gate electrode lead-out portion 28 made of polysilicon for taking out the gate electrode 27 is formed to be connected through the gate oxide film 26. Has been done. The drain electrode 31 is provided on the drain layer 24, and the gate electrode 2 is provided on the gate electrode extraction portion 28.
7 is provided. On the other hand, the N-type diffusion layer 21 in contact with the lower side of the source layer 22 is extended in the lateral direction as much as necessary (extended to the right in the drawing), and the extended N-type diffusion layer 21. A source electrode lead-out portion 29 made of polysilicon is formed on the above, and a source electrode 30 is formed thereon.
Is provided. The source electrode of the transistor on the left is not shown in the figure.

Further, the source layer 22 and the N-type diffusion layer 21.
And the gate electrode lead-out portion 28, between the drain layer 24 and the gate electrode lead-out portion 28, and the electrodes 27, 31, 3
Between 0, the insulating layer 25 is filled and insulated.
Although the drain layer 24 also serves as a drain electrode extraction portion in FIG. 1, when the drain electrode 31 is arranged on the side of the central transistor (operating region) as shown in FIG. 2, it is made of polysilicon. The drain electrode extraction portion may be provided on the side of the transistor so as to be connected to the drain layer 24.

In the above structure, on the semiconductor substrate 20,
Since the diffusion layer 21, the source layer 22, the channel layer 23 and the drain layer 24 are formed in the vertical direction to form a vertical MOS structure transistor, it is necessary to perform scaling in consideration of an error like a conventional MOS transistor. Can be highly integrated without. Furthermore, the diffusion layer 21 and the source layer 22,
By thinning the channel layer 23 and the drain layer 24, the speed can be easily increased.

By making the transistor vertical,
Since it becomes possible to connect a plurality of gate electrode lead-out portions 28 to one channel layer 23 via the gate oxide film 26, the gate electrode 27 can be connected to one transistor.
A plurality of can be provided. Therefore, it is possible to configure a logic circuit or the like, which is generally composed of a large number of transistors, with a small number of transistors. Then, the N-type diffusion layer 21 in contact with the lower side of the source layer 22 of the central transistor
Are extended in the lateral direction as necessary, and the source electrode lead-out portion 29 is formed on the N-type diffusion layer 21, so that the gate electrode 27 is formed in three directions with respect to the central transistor operation region as shown in FIG. Can be placed at. Therefore, if these three gate electrodes 27 are used as an OR input, one transistor can form an OR circuit as shown in FIG.

Further, by forming the source layer 21 and the drain layer 24 from silicon and the channel layer 23 from silicon carbide, the gate oxide film 26 is formed into the source layer 21 and the drain layer 24 due to the difference in the oxidation rates of silicon and silicon carbide. Since it can be made thinner than the insulating film 25 that insulates the gate electrode extraction portion 28, the transistor can be operated at a low voltage.

Next, a method of manufacturing the vertical MOS structure transistor will be described with reference to FIGS. First, FIG.
As shown in (a), thermal oxidation treatment is performed at 900 ° C. for 30 minutes,
A 1000 Å thick silicon oxide (SiO ₂ ) film 40 is formed on the P-type silicon substrate 20. Next, as shown in FIG. 4B, the silicon oxide film 4 is left while leaving the transistor operating region.
A mask 41 of 0 is applied, and phosphorus (P) as an impurity is diffused by 1E15 cm ⁻³ at 50 KeV by implantation to form an N-type diffusion layer 21 on the silicon substrate 20.

Then, as shown in FIG. 4C, after removing the mask 41 and growing the silicon oxide film 40 by 10000Å in the vertical direction by the CVD method, the growth layer of the silicon oxide film 40 on the diffusion layer 21 is RIE. It is selectively removed by (reactive etching) to expose the diffusion layer 21 in the operation region. Thereafter, as shown in FIG. 4D, the source layer 22, the channel layer 23, and the drain layer 24 are vertically formed on the diffusion layer 21 in the operation region in a single process by changing the material gas and the temperature by the selective CVD method. To form. That is, the source layer 22 made of N-type Si is deposited on the diffusion layer 21 by the CVD method for 5 minutes using a mixed gas of SiH ₄ and PH ₃ as a material gas, and the residual gas of SiH ₄ and PH ₃ is discharged. .. Then, P-type Si is formed on the diffusion layer 21 by a CVD method for 10 minutes using SiH ₄ and C ₃ H ₈ as a material gas.
A channel layer 23 made of C is deposited, and SiH ₄ , C ₃ H
_Eject the residual gas of ₈ . Furthermore, as a material gas, Si
A drain layer 24 made of N-type Si is deposited on the diffusion layer 21 by a CVD method using a mixed gas of H ₄ and PH ₃ for 5 minutes.

Next, as shown in FIG. 4 (e), after removing the gate electrode extraction region left in FIG. 4 (c) by HF etching, thermal oxidation treatment is performed at 1000 ° C. for 60 minutes to form a transistor (source-source). A silicon oxide insulating film 25 is formed on the upper side wall and the side wall of the channel-drain layer. At this time, Si
Due to the difference in the oxidation rates of C and Si, the gate oxide film 26 on the sidewall of the SiC (channel layer) 23 may be different from the other (source layer 2
2, the drain layer 24) is formed thinner than the insulating film 25.

Then, as shown in FIG. 5A, the growth layer of the silicon oxide film 40 on the source electrode extraction region is removed by etching by RIE to expose the source electrode extraction region, and the source electrode extraction region and the gate electrode extraction region are exposed. At the same time, polysilicon is deposited to form a gate electrode extraction portion 28 and a source electrode extraction portion 29. At this time, the gate electrode extraction portion 2
8 is connected to the channel layer 23 via the gate oxide film 26. Further, the source electrode lead-out portion 29 functions as a plug that alleviates the step difference of the source electrode 30.

After that, as shown in FIG. 5B, plasma CV
Gate electrode lead-out portion 28 and source electrode lead-out portion 2 by the D method
A silicon oxide film 42 is deposited on the SOG (Spin
After applying On Glass), the surface is flattened by etching by RIE. Next, FIG. 5 (c)
, The insulating film 2 on the drain layer 24 by RIE
6, the silicon oxide film 42 on the gate electrode extraction part 28 and the source electrode extraction part 29 is removed by etching to expose the drain layer 24, the gate electrode extraction part 28, and the source electrode extraction part 29.

Finally, as shown in FIG. 5D, an electrode material such as aluminum is deposited, and etching is performed while leaving the wiring portion, thereby forming the gate electrode 27, the source electrode 30, and the drain electrode 31. In this way, the source layer 22, the channel layer 23, and the drain layer 2 are changed while changing the material gas.
4 is formed, the source-channel-drain layer is C
It can be formed in a single process by the VD method. Therefore,
This leads to simplification of the manufacturing process.

Further, since the source electrode lead-out portion 29 is formed at the same time as the gate electrode lead-out portion 28, the electrode lead-out portion forming step is greatly simplified. It should be noted that the present invention is not limited to the above embodiment, and many changes and modifications can be made within the scope of the present invention. For example,
In the above embodiment, the semiconductor substrate is an N-type silicon substrate,
The source layer 22 is P-type Si and the channel layer 23 is N-type Si.
Similar effects can be obtained even if the C and drain layers 24 are made of P-type Si.

[0028]

As is apparent from the above description, claim 1
In this semiconductor device, since a source layer, a channel layer, and a drain layer are vertically formed on a semiconductor substrate to form a vertical MOS structure semiconductor device, an error is taken into consideration like a conventional MOS semiconductor device. High integration can be achieved without scaling. Further, by thinning the source layer, the channel layer and the drain layer, the speed can be easily increased.

In the semiconductor device according to the second aspect of the present invention, the semiconductor element operating region has a vertical structure, so that a plurality of gate electrodes can be provided for one semiconductor element.
By providing a plurality of gate electrodes for one semiconductor element, a logic circuit or the like can be formed with a small number of semiconductor elements. According to another aspect of the semiconductor device of the present invention, the diffusion layer in contact with the source layer is laterally extended as much as necessary, and the source electrode extraction portion is formed on the extended diffusion layer. Can be arranged in three directions with respect to the operation region, and if these three gate electrodes are OR inputs, one semiconductor element can form an OR circuit.

According to another aspect of the semiconductor device of the present invention, the source layer and the drain layer are formed of silicon, and the channel layer is formed of silicon carbide. Due to the difference in the oxidation rates of silicon and silicon carbide, the gate oxide film is changed to the source layer and drain layer. Since it can be made thinner than the insulating film that insulates the gate electrode extraction portion, the semiconductor element can be operated at a low voltage.

In the manufacturing method of the fifth aspect, the source layer, the channel layer and the drain layer are formed while changing the material gas in the operation region forming step.
The drain layer can be formed in a single process by the CVD method, which leads to simplification of the manufacturing process. According to the manufacturing method of the sixth aspect, since the gate electrode lead-out portion forming step and the source electrode lead-out portion forming step are simultaneously performed, the electrode lead-out portion forming step is greatly simplified.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing the positional relationship of source, drain, and gate electrodes with respect to the central transistor of FIG.

FIG. 3 is a circuit diagram showing an example of a logic circuit obtained when the electrodes are arranged as shown in FIG.

FIG. 4 is a diagram showing a manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process after that shown in FIG.

FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device.

[Explanation of symbols]

 20 semiconductor substrate 21 diffusion layer 22 source layer 23 channel layer 24 drain layer 25 insulating film 26 gate oxide film 27 gate electrode 28 gate electrode extraction part 29 source electrode extraction part 30 source electrode 31 drain electrode 40 oxide film 41 resist 42 oxide film

Claims (6)

[Claims] 1. A source layer, a channel layer and a drain layer which function as an operation region of a semiconductor device are vertically formed on a semiconductor substrate, and a gate electrode is taken out on a sidewall of the channel layer through a gate oxide film. The gate electrode lead-out part is formed so as to be connected to the channel layer. 2. The semiconductor device according to claim 1, wherein a plurality of gate electrode lead-out portions are provided for a channel layer of one semiconductor element, and each gate electrode lead-out portion is provided with a gate electrode. Semiconductor device. 3. The semiconductor device according to claim 2, wherein a diffusion layer is formed in contact with the source layer, the diffusion layer is extended laterally as much as necessary, and the source electrode is provided on the extended diffusion layer. A semiconductor device having a source electrode lead-out portion for taking out. 4. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate, the source and drain layers are silicon, and the channel layer is silicon carbide. 5. A step of forming an oxide film on a semiconductor substrate, a step of masking the oxide film while leaving a semiconductor element operating region, diffusing impurities to form a diffusion layer on the semiconductor substrate, and an oxide film in the operating region. Removing the diffusion layer to expose the diffusion layer and growing the remaining oxide film in the vertical direction. On the diffusion layer, the source layer is continuously formed while changing the material gas,
The step of vertically forming the channel layer and the drain layer, the oxide film growth layer in the gate electrode extraction region is removed to expose the sidewalls of the source layer, the channel layer, and the drain layer, and the source layer, the channel layer, and the drain layer are removed. Oxidation, thereby forming an insulating film on the sidewalls of the source and drain layers and a gate oxide film on the sidewalls of the channel layer, depositing polysilicon on the gate electrode extraction region, and passing through the gate oxide film. A step of forming a gate electrode lead-out portion so as to be connected to the channel layer, an oxide film growth layer on the source electrode lead-out region is removed to expose a diffusion layer, and polysilicon is deposited on the diffusion layer to form a source electrode lead-out portion. And forming a gate electrode on the gate electrode extraction portion, a source electrode on the source electrode extraction portion, and a drain electrode on the drain electrode extraction portion, respectively. The method of manufacturing a semiconductor device characterized by comprising a step. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the gate electrode lead-out portion and the step of forming the source electrode lead-out portion are performed at the same time.