JPH05121429A - Manufacture of heterojunction bipolar transistor - Google Patents
Manufacture of heterojunction bipolar transistorInfo
- Publication number
- JPH05121429A JPH05121429A JP28106791A JP28106791A JPH05121429A JP H05121429 A JPH05121429 A JP H05121429A JP 28106791 A JP28106791 A JP 28106791A JP 28106791 A JP28106791 A JP 28106791A JP H05121429 A JPH05121429 A JP H05121429A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gaas
- layer
- etching
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、超高周波デバイスや
高速動作のＩＣに用いられる、ＧａＡｓ等を材料とした
ヘテロ接合バイポーラトランジスタ、特にメサ型のヘテ
ロ接合バイポーラトランジスタの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a heterojunction bipolar transistor made of GaAs or the like, particularly a mesa type heterojunction bipolar transistor, which is used for an ultra high frequency device or an IC operating at high speed.
【０００２】[0002]
【従来の技術】エミッタ領域をベース領域よりも禁制帯
幅の大きい材料で構成したいわゆるヘテロ接合バイポー
ラトランジスタ（ＨＢＴ）の開発が進められている。
（例えば特開昭６３−６８７７） 従来メサ型のＨＢＴ
（構造断面の例を図１に示す）は以下に一例を示すよう
な工程で製造されている。2. Description of the Related Art Development of a so-called heterojunction bipolar transistor (HBT) in which an emitter region is made of a material having a band gap larger than that of a base region is under development.
(For example, JP-A-63-6877) Conventional mesa type HBT
(An example of the cross section of the structure is shown in FIG. 1) is manufactured by the steps as shown below.
【０００３】ｎ型又は半絶縁性のＧａＡｓ基板上に分子
線エピタキシー（ＭＢＥ）または有機金属気相エピタキ
シー（ＯＭＶＰＥ）の方法で、ＧａＡｓ、ＡｌＧａＡ
ｓ、ＩｎＧａＡｓ等の層からなる多層エピタキシャル層
を形成する。続いてフォトリソグラフィーを用いて各層
を部分的にエッチングし、エミッタ領域およびベース領
域の電極形成部分を露出させる。露出した電極形成部分
に蒸着等の方法で金属電極を形成する。GaAs, AlGaA on n-type or semi-insulating GaAs substrate by molecular beam epitaxy (MBE) or metalorganic vapor phase epitaxy (OMVPE) method.
A multilayer epitaxial layer composed of layers such as s and InGaAs is formed. Then, each layer is partially etched by using photolithography to expose the electrode formation portions of the emitter region and the base region. A metal electrode is formed on the exposed electrode formation portion by a method such as vapor deposition.
【０００４】[0004]
【発明が解決しようとする課題】ベース層の上に積層さ
れたコレクタ層を部分的にエッチングしてベース層の電
極形成部分を露出させるとき、ベース層の表面でエッチ
ングを停止する必要がある。しかし、ＨＢＴにおいてベ
ース層の厚みは通常５０〜１５０ｎｍと薄いために、こ
のエッチングを正確に停止することは容易ではなく、メ
サ型ＨＢＴを実用化する上での障害になっていた。When the collector layer laminated on the base layer is partially etched to expose the electrode formation portion of the base layer, it is necessary to stop the etching on the surface of the base layer. However, since the thickness of the base layer is usually as thin as 50 to 150 nm in the HBT, it is not easy to stop this etching accurately, which has been an obstacle to putting the mesa-type HBT into practical use.
【０００５】この発明は上記のような従来のメサ型ＨＢ
Ｔの製造方法の問題点を解決し、ベース層で再現性良く
エッチングを停止することができる、ＨＢＴの製造方法
を提供することを目的とする。The present invention is a conventional mesa type HB as described above.
An object of the present invention is to provide a method for manufacturing HBT that solves the problems of the method for manufacturing T and that can stop etching in the base layer with good reproducibility.
【０００６】[0006]
【課題を解決するための手段】ＧａＡｓ基板上に、エミ
ッタ領域となるＡｌＧａＡｓ層およびＧａＡｓ層、ベー
ス領域となるＩｎＧａＡｓ層、およびコレクタ領域とな
るＧａＡｓ層を順次積層する工程と、コレクタ領域の一
部をＨｅとＣＣｌ2Ｆ2を含むガスを用いてエッチングす
る工程とを含むことを特徴とするＨＢＴの製造方法であ
る。A step of sequentially laminating an AlGaAs layer and a GaAs layer to be an emitter region, an InGaAs layer to be a base region, and a GaAs layer to be a collector region on a GaAs substrate, and a part of the collector region. And a step of etching with a gas containing He and CCl 2 F 2 .
【０００７】[0007]
【作用】ＨｅとＣＣｌ2Ｆ2を含むガスを用いて反応性イ
オンエッチングを行うと、ＡｌＧａＡｓおよびＩｎＧａ
Ａｓに対してＧａＡｓが選択的にエッチングされる。す
なわち、ＨｅとＣＣｌ2Ｆ2を含むガスを用いた反応性イ
オンエッチングによって、コレクタ領域となるＧａＡｓ
層はエッチングされ、ベース領域となるＩｎＧａＡｓ層
はエッチングされない。したがって、ベース領域の表面
でエッチングが停止し、ベース領域の表面を再現性良く
露出させることができる。When reactive ion etching is performed using a gas containing He and CCl 2 F 2 , AlGaAs and InGa are obtained.
GaAs is selectively etched with respect to As. That is, GaAs to be a collector region is formed by reactive ion etching using a gas containing He and CCl 2 F 2.
The layer is etched and the InGaAs layer serving as the base region is not etched. Therefore, etching stops at the surface of the base region, and the surface of the base region can be exposed with good reproducibility.
【０００８】[0008]
【実施例】ＯＭＶＰＥ法を用いて、図１に示すように、
ｎ型導電性ＧａＡｓ基板６の上に基板側から順にｎ+−
ＧａＡｓ（エミッタ電極取り出し層）１、ｎ−ＡｌＧａ
Ａｓ（エミッタ領域）２、ｐ−ＩｎＧａＡｓ（ベース領
域）３、ｎ−ＧａＡｓ（コレクタ領域）４、ｎ+−Ｇａ
Ａｓ（キャップ層）５の順にエピタキシャル層を積層
し、ｎ+−ＧａＡｓ（エミッタ電極取り出し層）１、ｐ
−ＩｎＧａＡｓ（ベース領域）３、ｎ+−ＧａＡｓ（キ
ャップ層）５の各層にエミッタ電極７、ベース電極８、
コレクタ電極９を形成した。EXAMPLE Using the OMVPE method, as shown in FIG.
On the n-type conductive GaAs substrate 6, n + − in order from the substrate side.
GaAs (emitter electrode extraction layer) 1, n-AlGa
As (emitter region) 2, p-InGaAs (base region) 3, n-GaAs (collector region) 4, n + -Ga
An epitaxial layer is laminated in the order of As (cap layer) 5, and n + -GaAs (emitter electrode extraction layer) 1, p
-InGaAs (base region) 3 and n + -GaAs (cap layer) 5 each have an emitter electrode 7, a base electrode 8,
The collector electrode 9 was formed.
【０００９】各層の厚みは、ｎ+−ＧａＡｓ（エミッタ
電極取り出し層）１は５００ｎｍ、ｎ−ＡｌＧａＡｓ
（エミッタ領域）２は２００ｎｍ、ｐ−ＩｎＧａＡｓ
（ベース領域）３は１００ｎｍ、ｎ−ＧａＡｓ（コレク
タ領域）４は５００ｎｍ、ｎ+−ＧａＡｓ（キャップ
層）５は２００ｎｍとした。エミッタ領域２のＡｌ組成
比 x（ＡｌxＧａ1-xＡｓ）は、図２（ａ）に示すように
厚み方向に変化させた。また、ベース領域３のＩｎ組成
比 y（ＩｎyＧａ1-yＡｓ）は、図２（ｂ）に示すように
厚み方向に一定とした。The thickness of each layer is 500 nm for n + -GaAs (emitter electrode extraction layer) 1 and n-AlGaAs
(Emitter region) 2 is 200 nm, p-InGaAs
The (base region) 3 was 100 nm, the n-GaAs (collector region) 4 was 500 nm, and the n + -GaAs (cap layer) 5 was 200 nm. The Al composition ratio x (Al x Ga 1-x As) of the emitter region 2 was changed in the thickness direction as shown in FIG. In addition, the In composition ratio y (In y Ga 1-y As) of the base region 3 was constant in the thickness direction as shown in FIG.
【００１０】ベース電極形成の際の、ｎ+−ＧａＡｓ
（キャップ層）５およびｎ−ＧａＡｓ（コレクタ領域）
４のエッチングは次のように行った。反応性イオンエッ
チング装置中にエピタキシャルウエハを置き、Ｈｅおよ
びＣＣｌ2Ｆ2をそれぞれ流量１０ＳＣＣＭおよび４０Ｓ
ＣＣＭで供給した。装置内の圧力は５．０Ｐａに保っ
た。１２０秒間の反応性イオンエッチングを行った結
果、エッチング深さは７０５ｎｍとなり、厚み５００ｎ
ｍのｎ+−ＧａＡｓ（キャップ層）５と厚み２００ｎｍ
のｎ−ＧａＡｓ（コレクタ領域）４が完全にエッチング
され、ｐ−ＩｎＧａＡｓ（ベース領域）３の表面が露出
したことが確認できた。N + -GaAs when forming the base electrode
(Cap layer) 5 and n-GaAs (collector region)
The etching of No. 4 was performed as follows. The epitaxial wafer is placed in a reactive ion etching apparatus, and He and CCl 2 F 2 are supplied at flow rates of 10 SCCM and 40 S, respectively.
Supplied by CCM. The pressure inside the device was maintained at 5.0 Pa. As a result of performing reactive ion etching for 120 seconds, the etching depth is 705 nm and the thickness is 500 n.
m n + -GaAs (cap layer) 5 and thickness 200 nm
It was confirmed that the n-GaAs (collector region) 4 was completely etched and the surface of the p-InGaAs (base region) 3 was exposed.
【００１１】１４枚のエピタキシャルウエハに上記のエ
ッチング方法を適用したところ、すべてのウエハについ
て良好なエッチング結果が得られ、各ウエハから作製し
たＨＢＴはいずれも所望の特性を有していた。When the above-mentioned etching method was applied to 14 epitaxial wafers, good etching results were obtained for all the wafers, and all the HBTs produced from each wafer had desired characteristics.
【００１２】[0012]
【発明の効果】本発明によれば、厚みの薄いベース領域
において確実にエッチングを停止することが可能とな
り、メサ型ＨＢＴデバイス製造の歩留りを向上すること
が出来るという効果が有る。According to the present invention, it is possible to reliably stop the etching in the thin base region, and it is possible to improve the production yield of the mesa type HBT device.
【図１】メサ型ＨＢＴの断面構造の一例を示す模式図で
ある。FIG. 1 is a schematic diagram showing an example of a cross-sectional structure of a mesa-type HBT.
【図２】ベース領域およびエミッタ領域の厚み方向の混
晶組成比分布を示すグラフである。FIG. 2 is a graph showing a mixed crystal composition ratio distribution in a thickness direction of a base region and an emitter region.
１：ｎ+−ＧａＡｓ（エミッタ電極取り出し層） ２：ｎ−ＡｌＧａＡｓ（エミッタ領域） ３：ｐ−ＩｎＧａＡｓ（ベース領域） ４：ｎ−ＧａＡｓ（コレクタ領域） ５：ｎ+−ＧａＡｓ（キャップ層） ６：ｎ型導電性ＧａＡｓ基板 ７：エミッタ電極 ８：ベース電極 ９：コレクタ電極1: n + -GaAs (emitter electrode extraction layer) 2: n-AlGaAs (emitter region) 3: p-InGaAs (base region) 4: n-GaAs (collector region) 5: n + -GaAs (cap layer) 6 : N-type conductive GaAs substrate 7: emitter electrode 8: base electrode 9: collector electrode
Claims (1)
ＡｌＧａＡｓ層およびＧａＡｓ層、ベース領域となるＩ
ｎＧａＡｓ層、およびコレクタ領域となるＧａＡｓ層を
順次積層する工程と、コレクタ領域の一部をＨｅとＣＣ
ｌ2Ｆ2を含むガスを用いてエッチングする工程とを含む
ことを特徴とするヘテロ接合バイポーラトランジスタの
製造方法。1. An AlGaAs layer and a GaAs layer to be an emitter region and an I region to be a base region on a GaAs substrate.
A step of sequentially stacking an nGaAs layer and a GaAs layer serving as a collector region, and He and CC for a part of the collector region
and a step of etching using a gas containing 1 2 F 2 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28106791A JPH05121429A (en) | 1991-10-28 | 1991-10-28 | Manufacture of heterojunction bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28106791A JPH05121429A (en) | 1991-10-28 | 1991-10-28 | Manufacture of heterojunction bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05121429A true JPH05121429A (en) | 1993-05-18 |
Family
ID=17633855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28106791A Pending JPH05121429A (en) | 1991-10-28 | 1991-10-28 | Manufacture of heterojunction bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05121429A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319589A (en) * | 2001-04-20 | 2002-10-31 | Hitachi Ltd | Semiconductor device and power amplifier comprising it |
-
1991
- 1991-10-28 JP JP28106791A patent/JPH05121429A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002319589A (en) * | 2001-04-20 | 2002-10-31 | Hitachi Ltd | Semiconductor device and power amplifier comprising it |
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