JPH05120370A - 論理シミユレータに対する双方向性ソケツト刺激インタフエース - Google Patents

論理シミユレータに対する双方向性ソケツト刺激インタフエース

Info

Publication number
JPH05120370A
JPH05120370A JP9291092A JP9291092A JPH05120370A JP H05120370 A JPH05120370 A JP H05120370A JP 9291092 A JP9291092 A JP 9291092A JP 9291092 A JP9291092 A JP 9291092A JP H05120370 A JPH05120370 A JP H05120370A
Authority
JP
Japan
Prior art keywords
simulator
circuit
logic simulator
logic
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9291092A
Other languages
English (en)
Japanese (ja)
Inventor
Craig Heikes
クレイグ・ヘイクス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH05120370A publication Critical patent/JPH05120370A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
JP9291092A 1991-04-11 1992-04-13 論理シミユレータに対する双方向性ソケツト刺激インタフエース Pending JPH05120370A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US68453991A 1991-04-11 1991-04-11
US684539 2000-10-06

Publications (1)

Publication Number Publication Date
JPH05120370A true JPH05120370A (ja) 1993-05-18

Family

ID=24748470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9291092A Pending JPH05120370A (ja) 1991-04-11 1992-04-13 論理シミユレータに対する双方向性ソケツト刺激インタフエース

Country Status (4)

Country Link
US (1) US6421823B1 (enrdf_load_stackoverflow)
EP (1) EP0508619A2 (enrdf_load_stackoverflow)
JP (1) JPH05120370A (enrdf_load_stackoverflow)
KR (1) KR920020318A (enrdf_load_stackoverflow)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2717902B1 (fr) * 1994-03-25 1996-05-31 Sextant Avionique Procédé et dispositif d'élaboration de tests de cartes électroniques.
US5600579A (en) * 1994-07-08 1997-02-04 Apple Computer, Inc. Hardware simulation and design verification system and method
US6944583B1 (en) 2000-02-02 2005-09-13 Centric Software, Inc. Multi-threaded frame safe synchronization of a simulation
US6721696B1 (en) 2000-02-25 2004-04-13 Centric Software, Inc. Simulation program having generic attribute access schema
JP2002366602A (ja) * 2001-04-06 2002-12-20 Seiko Epson Corp ソフトウエア及びハードウエアのシミュレーション方法及びシステム並びにプログラム
US7395524B2 (en) * 2003-08-28 2008-07-01 International Business Machines Corporation Method, system and program product providing a configuration specification language having clone latch support
US7389490B2 (en) * 2004-07-29 2008-06-17 International Business Machines Corporation Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities
US7386825B2 (en) * 2004-07-29 2008-06-10 International Business Machines Corporation Method, system and program product supporting presentation of a simulated or hardware system including configuration entities
CN107918585B (zh) * 2016-10-07 2023-05-02 福特全球技术公司 用于测试软件程序的方法和装置
US10318406B2 (en) * 2017-02-23 2019-06-11 International Business Machines Corporation Determine soft error resilience while verifying architectural compliance

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55153054A (en) * 1979-05-15 1980-11-28 Hitachi Ltd Logic circuit simulation system
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
EP0099114B1 (en) * 1982-07-13 1988-05-11 Nec Corporation Logic simulator operable on level basis and on logic block basis on each level
US4527249A (en) * 1982-10-22 1985-07-02 Control Data Corporation Simulator system for logic design validation
US4590581A (en) * 1983-05-09 1986-05-20 Valid Logic Systems, Inc. Method and apparatus for modeling systems of complex circuits
GB8327753D0 (en) * 1983-10-17 1983-11-16 Robinson G D Test generation system
US4663703A (en) * 1985-10-02 1987-05-05 Westinghouse Electric Corp. Predictive model reference adaptive controller
US5126966A (en) * 1986-06-25 1992-06-30 Ikos Systems, Inc. High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs
US4792913A (en) * 1986-11-03 1988-12-20 Grumman Aerospace Corporation Simulator for systems having analog and digital portions
JPS63145549A (ja) * 1986-12-09 1988-06-17 Hitachi Ltd 論理回路シミユレ−シヨン方法
US4907180A (en) * 1987-05-04 1990-03-06 Hewlett-Packard Company Hardware switch level simulator for MOS circuits
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
JP2522541B2 (ja) * 1989-03-24 1996-08-07 三菱電機株式会社 シミュレ―ション装置及びシミュレ―ション方法
JPH035801A (ja) * 1989-06-02 1991-01-11 Hitachi Ltd プログラマブルコントローラ
US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
DE3922022A1 (de) * 1989-07-05 1991-01-17 Bodenseewerk Geraetetech Verfahren zur simulation eines elektrischen systems bei der rechnergestuetzten entwicklung elektrischer systeme
US5327361A (en) * 1990-03-30 1994-07-05 International Business Machines Corporation Events trace gatherer for a logic simulation machine
US5193068A (en) * 1990-10-01 1993-03-09 Northern Telecom Limited Method of inducing off-circuit behavior in a physical model

Also Published As

Publication number Publication date
EP0508619A3 (enrdf_load_stackoverflow) 1994-01-12
US6421823B1 (en) 2002-07-16
EP0508619A2 (en) 1992-10-14
KR920020318A (ko) 1992-11-21

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