JPH05120012A - Exception processor - Google Patents

Abstract

PURPOSE:To improve the efficiency of an instruction processing by using a buffer storing an issued instruction until execution terminates. CONSTITUTION:An instruction decoding part 1 issues the instruction and registers the instruction issued to an issuing instruction regist ration buffer 3. When the execution of the instruction terminates in an instruction execution part 2, the registered instruction is eliminated from the issuing instruction registration buffer 3. When an exception occurs, the issuing and the execution of the instruction are interrupted, and a program is switched. When it is resumed, the instruction registered in the instruction registration buffer 3 is supplied to the instruction decoding part 1 before the instruction is supplied from a memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exception handling device in instruction pipeline processing.

[0002]

2. Description of the Related Art An example of a conventional exception handling apparatus will be described below with reference to the drawings. The exception handling device is a device for allowing the program to be correctly resumed when an exception occurs in the instruction pipeline process and the execution of the program is interrupted. FIG. 7 is a block diagram showing the configuration of a conventional exception handling device. In FIG. 7, 7
Reference numeral 1 is an instruction storage memory, and 72 is an instruction decoding unit. Reference numeral 73 is an instruction execution unit, in which various arithmetic units and load / load
It includes execution units such as store units. 74
Is a program counter, which holds an instruction start address which has not been read yet, that is, an address of an instruction which is read next. An unfinished instruction counter 75 stores the address of the first issued instruction among the instructions being executed. The operation of the exception processing device configured as described above will be described below.

In the initial state, the program counter 74
The unfinished instruction counter 75 stores the first fetched instruction address. When performing normal instruction pipeline processing, the instruction at the address indicated by the issued instruction address register 74 is transferred from the instruction storage memory 71 to the instruction decoding unit 72.
And the instruction decoding unit 72 decodes and issues the instruction.
Immediately after the instruction is fetched from the instruction storage memory 71, the content of the program counter 74 is updated to the address of the instruction to be supplied next. The issued instruction is the instruction execution unit 73.
Is executed, the content of the unfinished instruction counter 75 is updated to the address of the instruction to be finished next. Instruction execution unit 7
Execution in No. 3 uses different execution units depending on the type of instruction, and therefore the execution time also differs depending on the instruction, but the order in which the instruction ends and the order in which the instruction is issued are controlled to match. That is, if an instruction finishes executing before an earlier issued instruction, that instruction must wait until all previously issued instructions have finished.

When an exception occurs next, the instruction being executed is suspended and the issuing of the instruction is suspended. When resuming the suspended program, it is necessary to resume the process from the instruction whose execution was suspended. This can be realized by starting the processing from the instruction indicated by the unfinished instruction counter 75. The unfinished instruction counter 75 stores the address of the first issued instruction among the instructions issued by the instruction decoding section 72 and not yet executed by the instruction executing section 73. Since the order of instruction issuance and the order of execution end are the same, the execution of the subsequent instructions has not ended. Therefore, if the process is restarted from the instruction of this address, the program can be restarted correctly.

[0005]

However, in the above-mentioned configuration, the order of issue of instructions and the order of completion of execution must match, so that an instruction issued later will precede an instruction issued earlier. Even if the execution is finished, you must wait until the previously issued instruction finishes,
There was a problem that the efficiency of instruction processing deteriorates.

In view of the above points, the present invention has an object to provide an exception processing apparatus which improves the efficiency of instruction processing.

[0007]

In order to achieve the above object, an exception processing apparatus of the first invention comprises an instruction decoding section, an instruction execution section, and an issued instruction registration buffer for storing a plurality of instructions being executed. In the normal instruction processing, the instruction decoding unit decodes the instruction supplied from the memory, issues the instruction to the instruction execution unit, and simultaneously registers the instruction in the issued instruction registration buffer, After the instruction execution unit completes the execution of the instruction, the instruction registered in the issued instruction registration buffer is deleted, and when an exception occurs, the instruction decoding unit issues the instruction and the instruction execution unit When the instruction execution is suspended and the instruction processing is restarted, the instruction registered in the issued instruction registration buffer before the instruction is supplied from the memory to the instruction decoding unit is transferred to the instruction decoding unit. It is intended to supply.

The exception processing device of the second invention comprises an instruction decoding unit, an instruction execution unit, and an issued instruction registration buffer for storing a plurality of instructions being executed. In normal instruction processing, The instruction decoding unit decodes an instruction supplied from a memory, issues the instruction to the instruction execution unit, and at the same time registers the instruction in the issued instruction registration buffer for a specific type of instruction. After the execution of the instruction is completed, the instruction registered in the issued instruction registration buffer is deleted, and when an exception occurs, the instruction decoding unit interrupts the issuance of the instruction and the instruction execution unit causes the issuance. Execution of the instructions registered in the instruction registration buffer is interrupted, execution of all other instructions is completed, and when restarting the instruction processing, the instructions are supplied from the memory to the instruction decoding unit. And supplies an instruction registered in the issued instruction register buffer before said instruction decoding unit.

Further, the exception handling apparatus of the third invention is such that an instruction decoding unit, an instruction execution unit, and a plurality of issued instruction registrations prepared separately for each type of instruction for storing a plurality of instructions being executed. In a normal instruction processing, the instruction decoding unit decodes an instruction supplied from a memory, issues the instruction to the instruction execution unit, and simultaneously prepares a specific type of instruction separately. When the instruction is registered in the issued instruction registration buffer, the instruction execution unit finishes executing the instruction, the instruction registered in the issued instruction registration buffer is deleted, and an exception occurs, The instruction decoding unit suspends the issuance of instructions, the instruction execution unit suspends the execution of the instructions registered in the issued instruction registration buffer, completes the execution of all other instructions, and terminates the instructions. When restarting the processing, and supplies an instruction registered in the issued instruction registration buffer before supplying instructions to the instruction decoding unit from the memory to the instruction decoding unit.

[0010]

According to the present invention, even if the instruction issue order and the execution end order do not match, the present invention guarantees the restart of the instruction after the exception occurs. You don't have to wait if you don't.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An exception processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the first of the present invention.
3 is a block diagram showing the configuration of an exception handling apparatus in the embodiment of FIG. In FIG. 1, an instruction decoding unit 1 decodes an instruction and issues the instruction. An instruction execution unit 2 includes various arithmetic units and execution units such as load / store units. 3 is an issue instruction registration buffer,
Store the issued instruction. Instruction processing is performed in a pipeline manner.

The operation of the exception handling device configured as described above will be described below with reference to FIGS. 1 and 2.
FIG. 2 is an explanatory diagram showing the configuration and operation of the issued instruction registration buffer in the exception handling device of this embodiment. The issue instruction registration buffer has a circular linear list structure. In FIG. 2, 21 is a buffer area for registering an instruction, 22 is a registration pointer for pointing a buffer area for next registering an instruction, 23
Is a delete pointer that points to the buffer area for the next instruction to be deleted. Although FIG. 2 shows a case where the number of regions is 5, it is sufficient to prepare a sufficient number of regions for processing.

FIG. 2A shows the issue instruction registration buffer in the initial state. In the initial state, the registration pointer and the deletion pointer point to the same buffer area. It is assumed that the instruction processing is started and the instruction A is supplied from the memory. Command A
Is decoded by the instruction decoding unit 1 and issues the instruction A to the instruction execution unit 2. At the same time as the instruction issuance, the instruction A is sent to the issued instruction registration buffer 3 and registered. In the issued instruction registration buffer 3, the content of the instruction A is stored in the area of the buffer pointed by the registration pointer 22, the registration pointer 22 is updated, and the area where the instruction is next registered is pointed to. As a result, the issued instruction registration buffer becomes the state shown in FIG. Command A
Then, when the instruction B is issued and registered in the issued instruction registration buffer, the instruction issuance registration buffer 3 becomes as shown in FIG. Thereafter, in the same manner, when the instruction is issued, the instruction is registered in the issued instruction registration buffer 3. If there is no more area to register, the command issuance is awaited until the registered command is deleted.

The instruction executing section 2 executes an instruction using various arithmetic units, load / store units and registers according to the type of instruction. Although the execution time differs depending on the type of instruction, the instruction issued earlier is controlled so that the execution is always completed earlier than the instruction issued later. The execution of the instruction B does not end before the execution of the instruction A.

Next, when the execution of the instruction A is completed in the instruction execution unit 2, the instruction execution unit 2 sends an instruction to delete the registered instruction to the issued instruction registration buffer 3, and the issued instruction registration buffer 3 stores the instruction in FIG. As in d), the contents of the delete pointer 23 are updated so as to point to the next area, that is, the area in which B is stored. Deletion can be realized by this operation. Although the order of registration and the order of deletion are the same, as described above, the order of issuance and the order of completion of execution match, so that another instruction is not deleted by mistake. Due to such registration and deletion operations,
The instruction being executed is stored.

Next, a case where an exception occurs will be described with reference to FIG. FIG. 3 is a block diagram showing the procedure of exception handling when an exception occurs in the exception handling apparatus of this embodiment. In FIG. 3, 31 is an instruction decoding unit, and 32 is
Is an instruction execution unit, and 33 is an issued instruction registration buffer. FIG. 3A shows the state of the exception handling device at the time when the exception occurs. In FIG. 3A, four instructions A, B, C, and D are processed in this order, and the A,
The instruction B and the instruction C have already been issued from the instruction decoding unit 2, and the instruction D has not been issued. Moreover, the execution of the instruction A is completed, and the instructions B and C are not completed.

If an exception occurs at this point, the instruction decoding unit 31 issues the instruction D and the instruction execution unit 32 issues the instruction B.
And execution of instruction C is interrupted. Issue instruction registration buffer 33
Content is retained. When the processing of this program is restarted, the processing is started from the instruction B. As shown in FIG. 3B, first, the instruction B registered in the issued instruction registration buffer 33 is supplied to the instruction decoding unit 31, the instruction is decoded again, and the instruction is reissued. Next, as shown in FIG. 3C, the instruction C is transferred from the issued instruction registration buffer 33 to the instruction decoding unit 31 like the instruction B.
And reissue. Since the instruction B and the instruction C are already registered in the issued instruction registration buffer 33, they are not registered at the time of issuance. After issuing command B and command C, see Fig. 3 (d).
As shown in, the instruction D is supplied from the memory to the instruction decoding unit 31.

When the instruction D is issued, it is registered in the issued instruction registration buffer 33 as shown in FIG. 3 (e), and the instruction decoding unit 31 is supplied with the next instruction E from the memory. If the instruction B is completed at this point, B is deleted from the issued instruction registration buffer 33.

A comparison will be made with the conventional method. In the conventional method, the unfinished instruction counter is used to supply the corresponding instruction from the memory. In this case, in order to supply the instruction from the memory when the normal instruction processing is restarted, the instruction decoding unit from the memory It takes time to supply the command to. As in the present embodiment, the issued instruction registration buffer 33 to the instruction decoding unit 3
It is faster to supply an instruction to the instruction decoding unit 31.
Can supply the order to. Further, the issue instruction registration buffer 3
Since 3 can supply the instruction to the instruction decoding unit 31, in parallel with the instruction supply from the memory,
Immediately after the instruction supply from the issued instruction registration buffer 33 is completed, the instruction can be supplied from the memory.

As described above, according to the present embodiment, the exception handling device is composed of the instruction decoding unit 31, the instruction execution unit 32, and the issued instruction registration buffer 33 which stores a plurality of instructions being executed. In the instruction processing, the instruction decoding unit 31 decodes the instruction supplied from the memory, issues the instruction to the instruction execution unit 32, and at the same time issues the issued instruction registration buffer 3
3, the instruction execution unit 32 finishes executing the instruction, deletes the instruction registered in the issued instruction registration buffer 33, and when an exception occurs, the instruction decoding unit 31 Of the instruction registered in the issued instruction registration buffer 33 before the instruction is supplied from the memory to the instruction decoding unit 31 when the instruction execution by the instruction execution unit 32 is resumed and the instruction processing is restarted. By supplying the decoding unit 31, the program can be restarted more efficiently than in the conventional example.

In this embodiment, when the instructions B and C are supplied to the instruction decoding section 31, the instructions B and C are left registered in the issued instruction registration buffer 33, and the instructions B are stored. The instruction B and the instruction C were not registered in the issued instruction registration buffer 33, but the instruction B and the instruction C were respectively issued when the instruction B and the instruction C were supplied to the instruction decoding unit 31. Delete from the instruction registration buffer 33,
You may register each when issuing.

Next, the second embodiment of the present invention will be described with reference to FIG.
Will be described with reference to. FIG. 4 is an explanatory diagram of the operation of the exception handling device in this embodiment. In FIG. 4, 41 is an instruction decoding unit, 42 is an instruction execution unit, and 43 is an issued instruction registration buffer. The configuration of the exception handling device of FIG. 4 is similar to that of the first embodiment, but the function of the issued instruction registration buffer 43 is different. Three instructions A, B, C are issued in this order,
It is assumed that the execution by the instruction execution unit 42 ends in the order of B, A, and C. FIG. 4 shows the state of the exception handling device at the time when the instruction B is completed.

Generally, the time required to execute an instruction differs depending on the type of load instruction, integer operation instruction, floating point operation instruction, and the like. Therefore, the instruction issued later may end execution earlier than the instruction issued earlier. In the first embodiment, the end of the instruction is controlled so as to match the issue order, but this is not done in the present embodiment. As a result, the order in which the instructions are registered in the issued instruction registration buffer 43 does not match the order in which they are deleted.

In FIG. 4, registration is performed in the order of A, B, C, and deletion is performed in the order of B, A, C. That is, the instruction B is registered later than the instruction A, but is deleted first. In this case, it is necessary to give information about which instruction to delete to the issued instruction registration buffer 43 from the instruction execution unit 42. In other words, in the first embodiment, the command “Immediately delete” is issued and the command registration buffer 43 is issued.
In this embodiment, the issue instruction registration buffer 43 is instructed to “delete instruction B”, and the issue instruction registration buffer 43 selects the instruction B from the registered instructions. Search and delete. In short, associative memory is used for the issue instruction registration buffer 43. The method for resuming the program is the same as in the first embodiment.

According to the conventional method and the first embodiment, when an instruction finishes execution before an instruction issued earlier than that, the instruction is executed until all the previously issued instructions finish. Since it is kept waiting, the efficiency of instruction processing is reduced by the waiting time.

As described above, according to the present embodiment, by using the associative memory for the issue instruction registration buffer, deletion can be performed regardless of the order of registration, and therefore the order of issue of instructions and the order of execution termination do not match. Since the waiting time therefor is eliminated, an efficient exception handling device can be realized.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5A is a block diagram showing the configuration of the exception device in this embodiment, and FIG. 5B is an operation explanatory diagram of the exception processing device of this embodiment when an exception occurs. In FIG. 5, 51 is an instruction decoding unit, 52 is an instruction execution unit, and 53 is an issued instruction registration buffer, and instructions are deleted in the registered order. 54 is an integer arithmetic unit, 55 is a floating point arithmetic unit, 56 is load / store,
In the unit, these are included in the instruction execution unit 52. In this exception processing device, only load / store instructions and floating-point arithmetic instructions that may generate exceptions are registered in the issued instruction registration buffer 53, and integer arithmetic instructions that do not generate exceptions are not registered. In general, when a page fault occurs when a load / store instruction accesses the memory, another program process is switched to improve the efficiency of the process until necessary data is placed in the memory. Also, in the floating-point operation, when an operation exception such as division by 0 or overflow occurs, the operation is switched to the error recovery processing. On the other hand, the integer operation instruction does not generate an exception. When the execution of the instruction is completed, if the instruction is registered in the issued instruction registration buffer 53, the registration is deleted. When an exception occurs, the execution of the instructions registered in the issued instruction registration buffer 53 is suspended, and the execution of all the unregistered instructions is completed, and then the program is switched.

A specific example will be described with reference to FIG. Figure 5
In (b), A, B, C, D, and E represent individual instructions, which are issued in this order. Also, instructions A and D
Is a load instruction, B and E are floating point arithmetic instructions, and instruction C is an integer arithmetic instruction. Therefore, at the time of issuing each instruction, the instructions A, B, D and E are registered in the issued instruction registration buffer 53, and the instruction C is not registered. Regarding the end of instruction execution, the instructions A, B, D, and E registered in the issued instruction registration buffer 53 must end in the order in which they are issued, but the unregistered instruction C affects the end of other instructions. Not done. That is, the instruction C is issued after the instruction B, but may end before the instruction B.

Next, consider the case where an exception occurs. Figure 5
(b) shows the operation when the instruction A finishes executing, the instructions B, C, and D are executing, the instruction E is decoding, and the instruction D generates an exception. At this point of time, the commands B and D are registered in the issued command registration buffer 53. Instruction A has been deleted because it has already been executed. Execution of the instructions B and D in the instruction execution unit 52 is interrupted due to the occurrence of the exception. Since the instruction C is not registered in the issued instruction registration buffer 53, execution is continued, and program switching waits until the execution of the instruction C is completed. The method for resuming the program is the same as in the first embodiment.

As described above, according to the present embodiment, the exception processing device is composed of the instruction decoding unit 51, the instruction execution unit 52, and the issued instruction registration buffer 53 which stores a plurality of instructions being executed. In the instruction processing, the instruction decoding unit 51 decodes the instruction supplied from the memory, issues the instruction to the instruction execution unit 52, and simultaneously registers the instruction in the issued instruction registration buffer 53 for a specific type of instruction. After execution of the instruction in the instruction execution unit 52, the instruction registered in the issued instruction registration buffer 53 is deleted, and if an exception occurs, the instruction decoding unit 51 interrupts the instruction issuance, The execution unit 52 suspends the execution of the instructions registered in the issued instruction registration buffer 53, completes the execution of all other instructions, and restarts the instruction processing,
By supplying the instruction registered in the issued instruction registration buffer 53 to the instruction decoding section 51 before the instruction is supplied from the memory to the instruction decoding section 51, the overhead of instruction registration and deletion can be reduced. In addition, for an instruction that is not registered in the issued instruction registration buffer 53, the end order of execution is not restricted by the order of instruction issuance, so the waiting time for instruction end can be reduced and the efficiency of instruction processing is improved.

In this embodiment, the issued instruction registration buffer 53 is configured to delete the instructions in the registered order. However, the issued instruction registration buffer 53 may be configured to use an associative memory.

A fourth embodiment of the present invention will be described below with reference to FIG.
Will be described with reference to. FIG. 6A is a block diagram showing the configuration of the exception handling device of this embodiment, and FIG. 6B is an operation explanatory diagram of the exception handling device of this embodiment. In FIG. 6, 61 is an instruction decoding unit, 62 is a first issued instruction registration buffer for registering floating point arithmetic instructions, 63 is a second issued instruction registration buffer for registering load / store instructions, 64
Is an instruction execution unit, 65 is an integer arithmetic unit, 66 is a floating point arithmetic unit, and 67 is a load / store unit. Similar to the third embodiment, only the load / store instruction and the floating point operation instruction are registered in the issued instruction registration buffer. In this embodiment, the issued instruction registration buffer is prepared for each type of instruction. No issue instruction registration buffer is provided for instructions that do not need to be registered. The first issued instruction registration buffer 62 and the second issued instruction registration buffer 63 are both configured to delete instructions in the order in which they are registered.

A concrete example will be described with reference to FIG. Figure 6
In (b), A, B, C, and D represent individual instructions, which are issued in this order. It is also assumed that the instructions A and D are load instructions, the instruction B is a floating point arithmetic instruction, and the instruction C is an integer arithmetic instruction. Instructions A and D are registered in the first issued instruction registration buffer 62, and instruction B is registered in the second issued instruction registration buffer 63. The command C is not registered. Therefore, since the instruction C is not registered in the issued instruction registration buffer, the execution is continued and the program switching waits until the execution of the instruction C is completed. When the instruction C is registered in any of the issued instruction registration buffers, the registration is deleted when the execution of the instruction C is completed. The method for resuming the program is the same as in the first embodiment.

As described above, according to the present embodiment, the exception processing device is provided with the instruction decoding unit 61, the instruction execution unit 64, and a plurality of separately prepared instruction types for storing a plurality of instructions being executed. In the normal instruction processing, the instruction decoding unit 61 decodes the instruction supplied from the memory and issues the instruction to the instruction execution unit 64, and at the same time, outputs the instruction of a specific type. , The issue instruction registration buffers 62 and 6 are prepared separately.
3, the instruction execution unit 64 finishes executing the instruction, and then deletes the instruction registered in the issued instruction registration buffers 62 and 63. When an exception occurs, the instruction decoding unit 61 Interrupts the issuance of instructions, the instruction execution unit 64 interrupts the execution of the instructions registered in the issued instruction registration buffers 62 and 63, completes the execution of all other instructions, and restarts the instruction processing. By supplying the instruction registered in the issued instruction registration buffers 62 and 63 to the instruction decoding section 61 before the instruction is supplied from the memory to the instruction decoding section 61, the execution is completed regardless of other kinds of instructions. Therefore, the waiting time for the instruction end is reduced, and the competition between the instruction registration request and the deletion request in the issued instruction registration buffers 62 and 63 is reduced, so that the instruction processing efficiency is improved.

In this embodiment, the issued instruction registration buffers 62 and 63 are configured to delete the instructions in the registered order, but the issued instruction registration buffers 62 and 63 may be configured to use the associative memory. ..

[0036]

As described above, the exception handling device of the present invention is
It is composed of an instruction decoding unit, an instruction execution unit, and an issued instruction registration buffer that stores a plurality of executing instructions. The issued instruction is registered in the issued instruction registration buffer, and when the execution of the instruction ends, the instruction is issued. When deleting from the instruction registration buffer and restarting the program when an exception occurs, by supplying an instruction from the issued instruction registration buffer to the instruction decoding unit, the program can be restarted correctly and at high speed.
Further, during normal instruction processing, it is not necessary that the instruction issuing order and the execution ending order be the same, and the waiting time therefor is eliminated, so that the instruction processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exception handling device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an issue instruction registration buffer in the same embodiment.

FIG. 3 is a block diagram showing an exception processing procedure in the embodiment.

FIG. 4 is an operation explanatory diagram of the exception handling device according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing the configuration and operation of an exception handling device according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing the configuration and operation of an exception handling device according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional exception handling device.

[Explanation of symbols]

 1 Instruction Decoding Section 2 Instruction Execution Section 3 Issued Instruction Registration Buffer 21 Buffer Area 22 Registration Pointer 23 Delete Pointer 31 Instruction Decoding Section 32 Instruction Execution Section 33 Issued Instruction Registration Buffer 41 Instruction Decoding Section 42 Instruction Execution Section 43 Issued Instruction Registration Buffer 51 Instructions Decoding unit 52 Instruction execution unit 53 Issuing instruction registration buffer 54 Integer calculator 55 Floating point arithmetic unit 56 Load / store unit 61 Instruction decoding unit 62 First issued instruction registration buffer 63 Second issued instruction registration buffer 64 Instruction execution unit 65 integer arithmetic unit 66 floating point arithmetic unit 67 load / store unit 71 instruction storage memory 72 instruction decoding unit 73 instruction execution unit 74 program counter 75 unfinished instruction counter

Claims (3)

[Claims] 1. An instruction decoding unit, an instruction execution unit, and an issued instruction registration buffer that stores a plurality of instructions being executed. In normal instruction processing, the instruction decoding unit is supplied from a memory. The instruction is decoded, the instruction is issued to the instruction execution unit, and at the same time, the instruction is registered in the issued instruction registration buffer, and after the instruction execution unit finishes executing the instruction, the instruction is registered in the issued instruction registration buffer. When the instruction is deleted and an exception occurs, the instruction decoding unit suspends issuing of the instruction and execution of the instruction in the instruction executing unit, and when restarting the instruction processing, the instruction decoding unit decodes the instruction from the memory. An exception processing device for supplying an instruction registered in the issued instruction registration buffer to the instruction decoding section before supplying the instruction to the section. 2. An instruction decoding unit, an instruction execution unit, and an issued instruction registration buffer that stores a plurality of instructions being executed, and in normal instruction processing, the instruction decoding unit is supplied from a memory. The instruction is decoded, the instruction is issued to the instruction execution unit, and at the same time, the instruction is registered in the issued instruction registration buffer for a specific type of instruction, and after the instruction execution unit finishes executing the instruction, When the instruction registered in the issued instruction registration buffer is deleted and an exception occurs, the instruction decoding unit interrupts the issuing of the instruction,
The instruction execution unit suspends the execution of the instructions registered in the issued instruction registration buffer, completes the execution of all other instructions, and resumes the instruction processing from the memory to the instruction decoding unit. An exception processing device that supplies the instruction registered in the issued instruction registration buffer to the instruction decoding unit before supplying the. 3. An instruction decoding unit, an instruction execution unit, and a plurality of issued instruction registration buffers separately prepared for each instruction type for storing a plurality of instructions being executed, and normal instruction processing. In the above, the instruction decoding unit decodes the instruction supplied from the memory, issues the instruction to the instruction execution unit, and simultaneously issues the instruction to the issued instruction registration buffer prepared separately for a specific type of instruction. Is registered and the execution of the instruction is completed by the instruction execution unit, the instruction registered in the issued instruction registration buffer is deleted, and when an exception occurs, the instruction decoding unit interrupts the issue of the instruction. However, the instruction execution unit suspends the execution of the instructions registered in the issued instruction registration buffer, completes the execution of all other instructions, and restarts the instruction processing. An exception processing device that supplies the instruction registered in the issued instruction registration buffer to the instruction decoding unit before supplying the instruction to the instruction decoding unit.