JPH0511819A - Sequence controller - Google Patents

Abstract

PURPOSE:To facilitate control based upon data from an external unit by the sequence controller which controls various FA equipment. CONSTITUTION:A refreshing request means is provided in a sequence control central arithmetic processor (PLC) and when the latest data from the external unit 1 is received by the sequence controller 4, the latest data is inputted after received data stored in a receiving buffer 5 in a communication module 2 are all cleared by the PLC 2. Consequently, since the latest data can be inputted instantaneously, sequence control corresponding to the external data can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence control device for controlling various factory automation (hereinafter referred to as FA) devices.

[0002]

2. Description of the Related Art In recent years, sequence control devices have been enhanced in function and speed by performing control based on data from various external units. An example of the above-described conventional sequence control device will be described below with reference to the drawings.

FIG. 4 shows a conventional sequence control device. FIG. 5 is a flowchart of a part related to a received data fetching process of a sequence control central processing unit (hereinafter referred to as PLC). FIG. 6 is a flowchart of a portion related to a received data fetching process of a communication control processing device (hereinafter, referred to as a communication module) that receives external data.

As shown in FIG.
Is a personal computer (hereinafter referred to as a personal computer)
Etc. is an external unit. 2 is a communication module. 3 is a PLC. Reference numeral 4 is a sequence control device. Reference numeral 5 is a reception buffer in the common storage unit. Reference numeral 6 is a signal at the time of the reception data fetching operation from the PLC 3 to the communication module 2 including the common storage unit. Reference numeral 7 is a signal for a reception completion interrupt which is generated when the data from the external unit 1 is received. Reference numeral 9 is a head address storage unit. Reference numeral 10 is a start address storage unit. Reference numeral 11 is a data counter. Reference numeral 13 is a transmission signal indicating an operation of transmitting data from the external unit 1 to the communication module 2.
Regarding the sequence control device configured as described above,
The operation will be described below.

In FIG. 5, step 2 enters this routine in response to a data fetch request from the PLC 3, and the received data is transferred from the data counter 11 as a memory that stores the number of received data stored in the communication module 13. This is the process of recognizing whether or not there is. Step 3
Is a process in which if there is received data stored in the communication module 13, only 1 byte of the data stored in the receiving buffer 5 first is fetched. Step 4 is a step of incrementing the address of the data fetched in step 3 (hereinafter referred to as the head address). Step 5 is a step of recognizing whether or not the data fetched in step 2 is a code indicating the end of the data (hereinafter referred to as delimiter), and if it is not the delimiter, the process returns to step 3. Step 6 is a step of incrementing the data counter when the fetched data is the delimiter. Step 9 is the process of exiting this routine and returning to the main routine.

In FIG. 6, step 13 enters this routine by a reception completion interrupt that occurs when the communication module 2 provided on the input side receives data from the external unit 1 and stores it in the common storage section. This is a process of comparing whether the storage start address (hereinafter, referred to as a start address) of the reception data newly stored in the reception buffer 5 in the common storage unit is equal to the start address. Step 14 is a process of storing the received data at the designated start address. Step 15 is a step of incrementing the start address. Step 16 is a step of recognizing whether or not the received data is the delimiter. Step 17 is a step of incrementing the data counter if the received data is the delimiter. Step 18 is a step of recognizing whether or not the data counter is zero when the start address and the start address are equal. Step 19 is a process of exiting the reception completion interrupt routine and returning to the main routine.

As described above, the communication module 2 enters the reception completion interrupt routine when the signal 7 is generated, and if the addresses stored in the start address storage unit 9 and the start address storage unit 10 are not the same, the reception buffer 5 Data is stored in, and if they are equal, it is recognized whether or not any data is stored. If not stored, the data is stored in the reception buffer 5, and when one data is received, the data counter 11 is incremented. Was. Also, P
The LC 3 recognizes whether or not the data is stored in the communication module 2 at the time of loading the data, and if the data is stored, sequentially loads the data stored at the address stored in the head address storage unit 9, After fetching the data, the address stored in the head address storage unit 9 is incremented. After the end of capturing one data, the data counter 11 is decremented.

[0008]

However, in the above configuration, when the PLC 3 wants to request the latest data from the external unit 1 in processing, it is not stored in the PLC 3 as it is stored in the reception buffer 5. If the data exists, the PLC 3 has a problem that the latest data cannot be received until after all the data are taken in. The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a sequence control device capable of performing control based on the latest data at high speed in response to a request.

[0009]

In order to achieve the above object, the present invention is a sequence control device which controls by referring to data from the outside, when the PLC requests the latest data from the external unit. In addition, refresh request means for fetching the latest data after erasing all the data stored in the reception buffer is provided on the PLC side. Further, a refresh request processing state flag for notifying the PLC side of the refresh request processing state is provided in the input section for inputting data from the outside.

[0010]

The sequence control device of the present invention having the above-described structure is
When the LC is requesting the latest data from the external unit, the communication module erases all the data stored in the reception buffer under the control of the refresh request means in the PLC by an interrupt signal or the like applied to the communication module. . By doing so, the PLC can receive the latest data from the external unit at high speed.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A sequence control device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the overall configuration thereof, and 1 to 7 are the same as 1 to 7 of the conventional FIG. 1 is an external unit such as a personal computer. Reference numeral 2 is a communication module as an input unit that receives data from the external unit 1. 3 is a PLC. Reference numeral 4 is a sequence control device. Reference numeral 5 is a reception buffer in the common storage unit.
Reference numeral 6 is a signal indicating a reception data fetching operation from the PLC 3 to the communication module 2 including the common storage unit. Reference numeral 7 is a signal for reception completion interrupt which is generated when data from the external unit 1 is received. Reference numeral 8 is a refresh request interrupt signal from the PLC 3 to the communication module 2.
9 to 11 are the same as 9 to 11 in FIG. Reference numeral 9 is a head address storage unit. Reference numeral 10 is a start address storage unit. Reference numeral 11 is a data counter. Further, 12 is a flag indicating the refresh request processing state of the communication module 2. Reference numeral 13 is a transmission signal indicating the operation of receiving data from the external unit 1 to the communication module 2 by the same operation as 13 in FIG.

The operation of the sequence control device configured as described above will be described below with reference to FIGS. 1 to 3. FIG. 2 is a flowchart on the PLC side regarding the received data fetching process in the embodiment. In FIG. 2, step 1 is a process of recognizing whether or not the PLC 3 requests the latest data by entering this routine in response to the PLC 3 data fetch request. Step 2-
Step 6 is similar to steps 2 to 6 in FIG.
After recognizing the presence / absence of data, the data is fetched byte by byte, the head address is incremented, and after the end of fetching the data, the data counter 11 is decremented. Step 7 is a step of issuing a refresh request interrupt signal as a refresh requesting means when the PLC 3 requests the latest data.
Step 8 is a step of recognizing whether the refresh request processing of the communication module 2 is completed. Step 9 is the same as step 9 in FIG. 5, and is a step of returning to the main routine.

FIG. 3 is a flow chart on the side of the communication module regarding the received data fetching processing provided on the input side. In FIG. 3, step 10 is a process of entering this routine by a refresh request interrupt from the PLC 3 and resetting the start address and the start address to the offset address. Step 11 is a process of resetting the data counter 11 to zero. Step 12
Is a process of exiting this refresh request processing routine and returning to the main routine. Steps 13 to 19 are similar to steps 13 to 19 in FIG. 6, and are steps of receiving data transmitted from the external unit 1 of the communication module 2.

As described above, the communication module 2 transmits the transmission signal 13 by the operation of transmitting data from the external unit 1.
Is input, a signal 7 is generated, the addresses stored in the start address storage unit 9 and the start address storage unit 10 are compared, and if they are not equal, data is specified in the reception buffer 5 by the start address storage unit 10. 1 to the address
The data is stored byte by byte, and the address stored in the start address storage unit 10 is incremented. After receiving the data until the end of the data, the data counter 11 is incremented. Even if the addresses stored in the start address storage unit 9 and the start address storage unit 10 are the same, if no data is stored in the reception buffer 5, that is, if the data counter 11 is zero, the start address storage unit 10 The data is stored at the address stored in. P
When requesting the fetching of the received data, the LC 3 recognizes whether or not the latest data is requested. If the latest data is not requested, the data counter 11 recognizes the presence or absence of the data, and the LC 3 If there is received data, a received data fetching operation is performed and the received data is fetched as shown by signal 6. After the end of data acquisition, the data counter 11 is decremented. PLC
If 3 is requesting the latest data, PL signal 8
It is generated in C3 and the communication module 2 is caused to perform the refresh request process. The communication module 2 sets the flag 12 during the refresh request process, and the flag 1 is set when the process is completed.
Reset 2. The PLC 3 recognizes the completion of the refresh request processing by the flag 12 and then fetches the latest data sent from the external unit 1.

[0016]

As is apparent from the above description, the sequence control device of the present invention is provided with the refresh request means in the PLC and the refresh request processing status flag of the communication module as an input unit of data from the outside. When the PLC is requesting the latest data transmitted from the external unit, the latest data transmitted from the external unit can be immediately captured by deleting all the data stored in advance in the reception buffer. Therefore, it becomes possible to flexibly deal with the sequence control.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a sequence control device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a control operation on the PLC side of the sequence control device of the embodiment.

FIG. 3 is a flowchart showing a control operation on the input unit side of the sequence control device of the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional sequence control device.

FIG. 5 is a flowchart showing a control operation on the PLC side of the conventional sequence control device.

FIG. 6 is a flowchart showing a control operation on the input side of the conventional sequence control device.

[Explanation of symbols]

1 External unit 2 Communication module 3 PLC (Sequence control central processing unit) 4 Sequence control device 5 Receive buffer 9 Start address storage 10 Start address storage 11 Data counter 12 flags

Claims (2)

[Claims] 1. A common storage unit for storing various data, and a sequence control central processing unit for performing sequence control by referring to data in the common storage unit, wherein the common storage unit is provided with various data from the outside. When the sequence control central processing unit receives the latest data from the outside, all the received data stored in the reception buffer is erased and then the latest data is refreshed. A sequence control device having request means. 2. The sequence control device according to claim 1, wherein the refresh requesting means fetches the latest data after confirming the flag display for displaying that all the received data stored in the receiving buffer has been erased.