JPH05110091A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05110091A
JPH05110091A JP26965891A JP26965891A JPH05110091A JP H05110091 A JPH05110091 A JP H05110091A JP 26965891 A JP26965891 A JP 26965891A JP 26965891 A JP26965891 A JP 26965891A JP H05110091 A JPH05110091 A JP H05110091A
Authority
JP
Japan
Prior art keywords
film
semiconductor
gate
channel
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26965891A
Other languages
Japanese (ja)
Inventor
Izumi Kobayashi
いずみ 小林
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP26965891A priority Critical patent/JPH05110091A/en
Publication of JPH05110091A publication Critical patent/JPH05110091A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a semiconductor device which can be enhanced in TFT characteristics, yield, and degree of integration by a method wherein a part of a patterned second conductive film is sandwiched between the gate electrodes of a MOS transistor formed of a first conductive film. CONSTITUTION:A silicon oxide film 102 is formed on all the surface of a semiconductor substrate 101, a polysilicon film is formed in a monosilane atmosphere at a temperature of 600-640 deg.C, P-type or N-type impurities are ion- implanted into all the surface of the polysilicon film to form fate electrodes 103 and 104 of a MOS transistor through photolithography and etching. In succession, a silicon oxide film 105 is formed, a polysilicon film is formed in a monosilane atmosphere at a temperature of 600-650 deg.C, then impurities are ion-implanted using resist as a mask for the formation of a source, a drain, and a channel, and thus a TFT channel 106 is formed. A silicon oxide film is formed on all the surface, a pattern is provided, and an aluminum wiring is laid on all the surface, whereby a semiconductor device of this design can be enhanced in transistor characteristics and degree of integration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to M semiconductor devices.
The present invention relates to an electrode structure of an OS transistor.

[0002]

2. Description of the Related Art One of the characteristics of SRAM is a low standby current capable of battery backup. In the conventional high resistance load type cell, the standby current per cell has been kept low by increasing the resistance value of the polysilicon that is the load. If 4MSRAM requires the same standby current as 1MSRAM, the standby current per cell needs to be reduced to 1/4. In that case, only the current equal to or less than the cell node leakage current can be supplied. Information retention becomes difficult. Then it was p
This is called a MOS load type cell. This is a pMOS transistor serving as a load stacked on an nMOS transistor, and has an advantage that higher integration can be achieved as compared with the complete cMOS type. In addition, this pMOS transistor is a TFT (Thin Film Trans) in which a source / drain / channel portion is formed into a thin polysilicon layer.
istor) structure.

The manufacturing method of this TFT transistor is shown in FIG.
Will be explained.

First, a silicon oxide film 302 is formed on a semiconductor substrate 301 by a CVD method, then a polysilicon film is formed by a CVD method, and a gate electrode 303 is formed by etching using a positive resist by photolithography. (FIG. 3A) Next, after forming the gate oxide film 304,
A polysilicon film 305 is formed by an LPCVD method, BF 2 + which is a P-type impurity is ion-implanted using a photoresist as a mask, and a source / drain region 30 is formed by a P + impurity layer.
6, 307 are formed. (FIG. 3B) At this time, the undoped impurity region 305 becomes a channel region. Finally, a pattern is formed by photolithography as shown in FIG.

As a method for improving the characteristics of the TFT transistor, development of a TFT called a double gate structure is under way. A sectional view of this double gate structure is shown in FIG. 4, and the operating mechanism and its features will be briefly described.

In the double gate structure TFT, the transistor is controlled by the upper and lower two gate electrodes 403 and 409. In a transistor having a single gate (single gate transistor), only the surface of the channel portion on the gate electrode side is inverted by applying a gate voltage, whereas in a TFT having a double gate structure with a thin channel portion, the entire channel region is inverted. .. That is, an increase in on-current can be expected.

In addition, the double gate TFT has an increase in channel conductance (g m ), an improvement in subthreshold characteristics, an improvement in short channel effect, as compared with the single gate TFT described above with reference to FIG.
Short channels are possible. That is, it is known that the off current does not increase even if the channel is shortened.

(Conference on Solid Devices and Mate
rials, 1990, pp393-396, Sharp Technical Report No. 46. 199
September 27, P27-31)

[0009]

However, since the double-gate structure TFT described in FIG. 4 has at least a three-layer structure of a lower gate, a bulk (source / drain / channel portion), and an upper gate in the TFT transistor structure, The yield decreases due to the increase in the number of processes. A problem with the increase in wiring layers arises, such as difficulty in flattening due to steep steps in and around the TFT channel portion, and high integration cannot be achieved.

Further, if the channel width (gate width: W) is further reduced due to the progress of high integration and miniaturization, sufficient current cannot be supplied.

Therefore, the present invention solves such a problem. The object of the present invention is not to increase the number of wiring layers even if a double gate is used to improve the TFT characteristics. An object of the present invention is to provide a TFT that can supply a sufficient current even if the planar gate width is reduced.

[0012]

The semiconductor device of the present invention comprises:
Two or more MOS type transistors formed of a first insulating film formed on a semiconductor substrate and a first conductive film having impurities of the first conductivity type formed on the first insulating film and patterned by etching. Of the gate electrode, the second insulating film formed on the first conductive film, and the second conductive film formed on the second insulating film and patterned by etching. A part is sandwiched between the gate electrodes of the MOS transistors formed of the first conductive film. The semiconductor device of the present invention is characterized in that the first conductive film is a refractory metal.

The semiconductor device of the present invention is characterized in that the first conductive film is a refractory metal silicide.

[0014]

EXAMPLES The present invention will now be described in detail based on examples.

FIG. 1 is a diagram showing an embodiment of the present invention in the order of steps. 101 is a semiconductor substrate, 102 and 107 are silicon oxide films, 103 and 104 are gate electrodes, 105 is a gate oxide film, 106 is a TFT channel portion, and 108 is aluminum wiring.

FIG. 2 is a plan view of the embodiment of the present invention.

First, CVD is performed on the entire surface of the semiconductor substrate 101.
Of the silicon oxide film 102 by the method or thermal oxidation.
~ 5000Å form. (FIG. 1A) Next, after forming a polysilicon film of 1000 to 3000 Å at 600 to 640 ° C. in a monosilane atmosphere by a CVD method, BF 2 + which is a P type impurity or P which is an N type impurity is formed on the entire surface. + Dose amount 1 × 10 14 to 1 × 10 16 , energy 30 to 120 k
The gate electrodes 103 and 104 of the MOS transistor are formed of a polysilicon film by ev by ion implantation, photolithography, and etching. (FIG. 1B) At this time, two gate electrodes are formed and the distance between the respective gate electrodes is set to 2000 Å. Since the interval of 2000 Å is not possible with ordinary photo, patterning is performed by excimer laser exposure or EB exposure. Then, a silicon oxide film 105 to be a gate oxide film is formed on the silicon oxide film 105 by a thermal oxide film or a CVD method.
00Å Form. (FIG. 1 (c)) Next, after forming a polysilicon film of 1000 liters at 600 to 650 ° C. in a monosilane atmosphere by the LPCVD method, P using the resist as a mask.
BF 2 + which is a type impurity, or P + which is an N type impurity, a dose amount of 1 × 10 14 to 1 × 10 16 and an energy of 30 to 1
After forming the source / drain and the channel portion by ion implantation at 20 kev, photolithography,
The TFT channel portion 106 is formed by etching.
(FIG. 1D) Next, a silicon oxide film is formed on the entire surface by a CVD method to a thickness of 2000 to 5000 Å, a pattern is formed by photolithography and etching, and aluminum is sputtered, photolithographically and etched to form wiring on the entire surface. (FIG. 1 (e)) According to the semiconductor device of the present invention completed through the above-described steps, the gate of the TFT has a double-gate structure. In addition to improving the transistor characteristics such as above, by forming the gate electrodes on the left and right of the channel part, it is possible to reduce the planar dimension in the channel width direction without changing the channel width. The number of steps is reduced and the yield is improved because it can be formed by using. By forming the channel part between the lower layers as well as reducing the number of wiring layers, it is possible to reduce the step and achieve flatness, which enables high integration. Even if the planar gate width is reduced with the increase in the number of gates, the channel section will be placed between the two gates. By embedding, the planar W can be reduced and a TFT having a large on-current can be formed. In addition, although the polysilicon film is used as the gate electrode in this embodiment, the same effect can be obtained by using refractory metal or refractory metal silicide. The effect is obtained.

In this embodiment, the polysilicon film formed by the LPCVD method is used for the source / drain / channel portion.
Even if a polysilicon film formed by forming an amorphous silicon film at 600 ° C. or 450 to 550 ° C. in a disilane atmosphere and then performing solid phase growth by annealing in an N 2 atmosphere at 550 to 650 ° C. is used, The effect is obtained.

[0019]

According to the present invention, a double gate can be formed without increasing the number of wiring layers. As a result, TFT characteristics are improved, speed is increased, planarization can be achieved, and yield is improved. In addition, since the planar dimension is small, a TFT with high integration can be provided.

[Brief description of drawings]

1A to 1E are cross-sectional views in order of the processes, showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a plan view showing an embodiment of a semiconductor device of the present invention.

3A to 3C are cross-sectional views in order of the processes, showing an embodiment of a conventional semiconductor device.

FIG. 4 is a structural cross-sectional view of an example of a conventional semiconductor device.

[Explanation of symbols]

101, 301, 401 Semiconductor substrate 102, 107, 302, 402 Silicon oxide film 103, 104, 202, 201, 303, 403, 4
09 gate electrode 105, 304, 404, 408 gate oxide film 106, 202, 305 channel part 204, 205, 306, 307 source / drain part 108 aluminum wiring

Claims (3)

[Claims]
1. A first insulating film formed on a semiconductor substrate,
Gate electrodes of two or more MOS transistors formed of a first conductive film having impurities of the first conductivity type formed on the first insulating film and patterned by etching, and formed on the first conductive film. A second insulating film, a second conductive film formed on the second insulating film and patterned by etching, and a part of the second conductive film patterned by the etching is formed by the first conductive film. A semiconductor device characterized by being sandwiched between gate electrodes of MOS transistors.
2. The semiconductor device according to claim 1, wherein the first conductive film is a refractory metal.
3. The semiconductor device according to claim 1, wherein the first conductive film is a refractory metal silicide.
JP26965891A 1991-10-17 1991-10-17 Semiconductor device Pending JPH05110091A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26965891A JPH05110091A (en) 1991-10-17 1991-10-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26965891A JPH05110091A (en) 1991-10-17 1991-10-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05110091A true JPH05110091A (en) 1993-04-30

Family

ID=17475417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26965891A Pending JPH05110091A (en) 1991-10-17 1991-10-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05110091A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8564060B2 (en) 2009-07-21 2013-10-22 Hitachi, Ltd. Semiconductor device with large blocking voltage and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8564060B2 (en) 2009-07-21 2013-10-22 Hitachi, Ltd. Semiconductor device with large blocking voltage and manufacturing method thereof

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