JPH0496661A - Ac power generating circuit - Google Patents
Ac power generating circuitInfo
- Publication number
- JPH0496661A JPH0496661A JP2211373A JP21137390A JPH0496661A JP H0496661 A JPH0496661 A JP H0496661A JP 2211373 A JP2211373 A JP 2211373A JP 21137390 A JP21137390 A JP 21137390A JP H0496661 A JPH0496661 A JP H0496661A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output
- amplifying element
- dropper
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010248 power generation Methods 0.000 claims description 3
- 230000000295 complement effect Effects 0.000 abstract description 8
- 230000003321 amplification Effects 0.000 description 9
- 238000003199 nucleic acid amplification method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 238000009499 grossing Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 101150073536 FET3 gene Proteins 0.000 description 3
- 101150015217 FET4 gene Proteins 0.000 description 3
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000007792 addition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Inverter Devices (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は交流電力発生回路に関するものである。[Detailed description of the invention] The present invention relates to an AC power generation circuit.
交流電力を発生する回路としては従来から、種々の方式
が用いられている。例えば、正弦波信号発生回路からコ
ンプリメンタリベアの電界効果型トランジスタ(FET
)やバイポーラ型トランジスタを用いて直流増幅する方
式がある。このような方式による回路では交流出力電圧
を比較的、高電圧、例えば、280 V程度に選ぶ場合
、使用するコンプリメンタリベアのトランジスタの耐電
圧を1、ooov以上にする必要がある。高耐圧のトラ
ンジスタをコンプリメンタリベアで準備することは現状
では入手に困難性を伴う。従って、同−型のト・ランジ
スタ等をトーテムポール接続とする手段もとられている
が、回路が複雑となる。Conventionally, various systems have been used as circuits that generate AC power. For example, from a sine wave signal generation circuit to a complementary bearer field effect transistor (FET)
) or bipolar transistors for DC amplification. In a circuit based on such a system, when the AC output voltage is selected to be a relatively high voltage, for example, about 280 V, it is necessary that the withstand voltage of the complementary bearer transistor used be 1,000 V or more. Currently, it is difficult to obtain high-voltage transistors using complementary bare. Therefore, a method has been taken in which transistors of the same type are connected in a totem pole connection, but the circuit becomes complicated.
又、前記せる従来回路では、直流増幅用直流電源電圧と
して、交流出力電圧280Vに対し、±500V (1
,0OOV)以上を必要とするなどの欠点があった。In addition, in the conventional circuit shown above, the DC power supply voltage for DC amplification is ±500V (1
, 0OOV) or more.
この発明は前記せる従来回路の問題点を解消し、使用す
る増幅素子を相補型の2種類とすることなく、直流電源
電圧及び増幅素子の耐電圧を1/2になし得る交流電力
発生回路の提供を目的とする。The present invention solves the problems of the conventional circuit described above, and provides an AC power generation circuit that can reduce the DC power supply voltage and the withstand voltage of the amplification element by half without using two complementary types of amplification elements. For the purpose of providing.
第1図は本発明の実施例を示す回路構成図であり、T1
は絶縁トランス、DBlは整流回路、C1は平滑用コン
デンサ、ドロッパーは増幅素子(ここではFET)OP
AMPはオペアンプ、FETI、FET2、FET3、
FET4はFETであってブリッジスイッチ回路を構成
する。その他に、全波整流波形発信回路、電圧コントロ
ールブロックを付設する。交流入力を絶縁トランスT1
に入力し、2次側から出力する。これは、第2図の波形
タイミング図のTI INPUT及びTI 0UT
PUTに示し、それぞれ絶縁トランスT1の1次側及び
2次側の交流電圧波形を表す。FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and T1
is an isolation transformer, DBl is a rectifier circuit, C1 is a smoothing capacitor, and dropper is an amplification element (FET here) OP
AMP is an operational amplifier, FETI, FET2, FET3,
FET4 is an FET and constitutes a bridge switch circuit. Additionally, a full-wave rectified waveform oscillation circuit and voltage control block are included. AC input isolation transformer T1
and output from the secondary side. This corresponds to TI INPUT and TI 0UT in the waveform timing diagram in Figure 2.
PUT represents the AC voltage waveforms on the primary side and secondary side of the isolation transformer T1, respectively.
又、T10UTPUTの交流電圧は整流回路DB1及び
平滑用コンデンサCIにより、整流し、平滑する。その
平滑直流は第2図のドロッパーINPUTに示す。ドロ
ッパーI NPUTの電圧値は所望の交流出力電圧のピ
ーク値以上の値とする。Further, the AC voltage of T10UTPUT is rectified and smoothed by the rectifier circuit DB1 and the smoothing capacitor CI. The smooth DC current is shown at dropper INPUT in FIG. The voltage value of the dropper I NPUT is set to a value greater than or equal to the peak value of the desired AC output voltage.
一方、例えば、ROMやD/Aコンバータ等により構成
する全波整流波形発信回路、出力電圧コントロールブロ
ック、OPAMPによって形成する全波整流波形信号を
ドロッパーでしめす増幅素子に制御入力として与える。On the other hand, for example, a full-wave rectified waveform signal formed by a full-wave rectified waveform generation circuit constituted by a ROM, a D/A converter, etc., an output voltage control block, and an OPAMP is applied as a control input to an amplification element represented by a dropper.
即ち、全波整流波形信号が増幅されることになり、第2
図のドロッパ0UTPUTの波形に示すごとき電圧がド
ロッパの出力側に発生する。次いで、ブリッジスイッチ
回路を構成するFET ]とFET2を導通するごとく
、その制御スイッチであるSWIとSW2をドロッパー
0UTPUT波形のOVのタイミングでオンし、次のド
ロッパー0UTPUT波形のoVのタイミングでSW3
とSW4をオンしてFET3とFET4を導通する。こ
のようにFET1 とFET2、FET3とFET4を
交互ニo■のタイミングでオンオフすることにより、交
流出力端子AB間に、第2図のAB−OUTPUTのご
とき正弦波交流出力を得ることができる。In other words, the full-wave rectified waveform signal is amplified, and the second
A voltage as shown in the waveform of the dropper 0UTPUT in the figure is generated on the output side of the dropper. Next, the control switches SWI and SW2 are turned on at the timing of OV of the dropper 0UTPUT waveform so as to conduct the FET ] and FET2 that constitute the bridge switch circuit, and SW3 is turned on at the timing of oV of the next dropper 0UTPUT waveform.
and turns on SW4 to make FET3 and FET4 conductive. By alternately turning on and off FET1 and FET2, and FET3 and FET4 at the timings of 2 and 4 in this manner, a sine wave AC output such as AB-OUTPUT in FIG. 2 can be obtained between AC output terminals AB.
前述のごとく、本発明の回路においては、所望の交流出
力電圧のせん頭領に等しい直流電源を設け、その直流電
源に直列に増幅素子(ドロッパー)を接続し、増幅され
た全波整流波形を出力し、ブリッジスイッチ回路により
交互に反転するようにして正弦波出力を発生している。As mentioned above, in the circuit of the present invention, a DC power supply equal to the peak area of the desired AC output voltage is provided, an amplification element (dropper) is connected in series to the DC power supply, and an amplified full-wave rectified waveform is output. However, a sine wave output is generated by alternately inverting the signals using a bridge switch circuit.
従って、増幅素子(ドロッパー)には直流電源、即ち、
第2図のドロッパーI NPUTの波形の電圧が印加さ
れ、コンプリメンタリペア等における印加電圧の172
となる。又、これにより、使用する増幅素子の許容耐電
圧を従来回路に比し1/2のものを選択し得る。Therefore, the amplifying element (dropper) is powered by a DC power supply, i.e.
The voltage of the waveform of the dropper I NPUT in Fig. 2 is applied, and 172% of the applied voltage in complementary repair etc.
becomes. Moreover, this makes it possible to select the allowable withstand voltage of the amplifying element to be used that is 1/2 that of the conventional circuit.
更に、増幅素子にFETを選ぶとき、Nチャンネル型と
Pチャンネル型、又バイポーラトランジスタを選ぶとき
、NPN型とPNP型と両型を使用する必要がなく、入
手しやすい型のみを選択できる。Furthermore, when selecting an FET as an amplification element, when selecting an N-channel type, a P-channel type, or a bipolar transistor, it is not necessary to use both NPN type and PNP type, and only the type that is easily available can be selected.
スイッチSW1.2及びSW3.4のオンオフは正確に
OVで行うのが好ましいが、厳密には0■近傍になる。It is preferable to turn on and off the switches SW1.2 and SW3.4 accurately at OV, but strictly speaking, it is close to 0.
第1図の実施例の回路構成を実際の応用では変形、付加
等の設計上の変更をなし得る。In actual applications, the circuit configuration of the embodiment shown in FIG. 1 may undergo design changes such as modifications and additions.
直流電源の構成も第1図のごとく整流回路及び平滑回路
による外、電池やコンバータ出力から得てもよい、又、
AB−OUTPUTを更に整流したり、他の機能回路に
接続してもよい。The configuration of the DC power source may be obtained from a rectifier circuit and a smoothing circuit as shown in Figure 1, or from a battery or converter output.
AB-OUTPUT may be further rectified or connected to other functional circuits.
以上のごとく、本発明の実施により、正確な正弦波交流
電力を得るためにコンプリメンタリペア等のごとく異種
型の使用素子を数多く用いることなく、又電源電圧を所
望交流電圧のせん頭領程度に力発生回路を構成でき、検
査装置用の電源など広い範囲に利用でき産業Eの効果大
なるものがある。As described above, by carrying out the present invention, in order to obtain accurate sine wave AC power, it is not necessary to use a large number of different types of elements such as complementary repair, and power can be generated by adjusting the power supply voltage to about the peak of the desired AC voltage. It can be used to construct circuits and can be used in a wide range of applications, such as power supplies for inspection equipment, making it highly effective for industry.
第1図は本発明の実施例の回路構成図、第2図は第1図
の波形タイミング図であり、T1は絶縁トランス、DB
Iは整流回路、CIは平滑用コンデンサ、ドロッパーは
増幅素子、OPAMPはオペアンプ、FET1.2.3
.4はブリッジスイッチ回路、SWl、2.3.4は制
御スイッチで?ある。FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a waveform timing diagram of FIG. 1, and T1 is an isolation transformer, DB
I is a rectifier circuit, CI is a smoothing capacitor, dropper is an amplification element, OPAMP is an operational amplifier, FET1.2.3
.. 4 is the bridge switch circuit, SWl, 2.3.4 is the control switch? be.
Claims (1)
チ回路を接続し、又、全波整流波形発信回路を設け、そ
の信号を前記増幅素子の制御入力とし、前記増幅素子の
全波整流出力電圧のゼロ近傍で前記ブリッジ型スイッチ
回路の出力側から交流電力を供給し得るようにしたこと
を特徴とする交流電力発生回路。A bridge type switch circuit is connected in series to the DC power supply via an amplifying element, and a full-wave rectified waveform generating circuit is provided, and the signal is used as a control input of the amplifying element, and the full-wave rectified output voltage of the amplifying element is An alternating current power generation circuit, characterized in that alternating current power can be supplied from the output side of the bridge type switch circuit near zero.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2211373A JPH0496661A (en) | 1990-08-08 | 1990-08-08 | Ac power generating circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2211373A JPH0496661A (en) | 1990-08-08 | 1990-08-08 | Ac power generating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0496661A true JPH0496661A (en) | 1992-03-30 |
Family
ID=16604889
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2211373A Pending JPH0496661A (en) | 1990-08-08 | 1990-08-08 | Ac power generating circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0496661A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009033815A (en) * | 2007-07-25 | 2009-02-12 | Canon Inc | Device for forming image |
-
1990
- 1990-08-08 JP JP2211373A patent/JPH0496661A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009033815A (en) * | 2007-07-25 | 2009-02-12 | Canon Inc | Device for forming image |
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