JPH0492426A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0492426A
JPH0492426A JP20981190A JP20981190A JPH0492426A JP H0492426 A JPH0492426 A JP H0492426A JP 20981190 A JP20981190 A JP 20981190A JP 20981190 A JP20981190 A JP 20981190A JP H0492426 A JPH0492426 A JP H0492426A
Authority
JP
Japan
Prior art keywords
isolation trench
metal silicide
melting
point metal
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20981190A
Other languages
Japanese (ja)
Inventor
Hiroichi Sakaguchi
阪口 博一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP20981190A priority Critical patent/JPH0492426A/en
Publication of JPH0492426A publication Critical patent/JPH0492426A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To realize multilayer wining by a method wherein a conductive layer is formed on the inside of an element-isolation trench in the surface of a silicon substrate. CONSTITUTION:SiO2 13 is filled into a groove 12 formed in the surface of a silicon substrate 11; and a conductive layer 14 is buried in it. When the width of an element-isolation trench is set at about 2mum and its depth is set at about 1mum, wining whose sheet resistance is at about 10OMEGA/square can be formed and the gate electrode of a MOS transistor can sufficiently be driven when a high- melting-point metal silicide layer 1.2mum wide and 0.2mum thick is buried in the SiO2. The junction point of the wining arranged on the element-isolation trench to the high-melting-point metal silicide can comparatively easily be realized when the high-melting-point metal silicide is grown selectively in an opening part obtained by selectively etching the SiO2 on the high-melting-point metal silicide which is buried in the element-isolation trench.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の多層配線技術において、特にトレ
ンチ素子分離半導体装置の多層配線に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to multilayer wiring technology for semiconductor devices, and particularly to multilayer wiring for trench isolation semiconductor devices.

〔従来の技術〕[Conventional technology]

技術の半導体装置は第2図、第3図のように、LOCO
5あるいは素子分離トレンチを含んだシリコン基板上に
、層間絶縁膜を介して配線を形成していた。
As shown in Figures 2 and 3, the technology semiconductor device is LOCO
5 or on a silicon substrate including an element isolation trench, wiring is formed via an interlayer insulating film.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、前述の従来技術におけるLOCO5およびトレ
ンチ構造は素子分離を目的として設けられたものであり
、半導体装置の高集積化、微細化が進む中での多層配線
化という観点てはシリコン基板表面の未使用部分を形成
しているたけてあった。
However, the LOCO5 and trench structure in the prior art described above are provided for the purpose of element isolation, and from the viewpoint of multilayer wiring as semiconductor devices become more highly integrated and miniaturized, they are an undeveloped area of the silicon substrate surface. There was a wall that formed the part that was used.

そこで本発明の目的とするところは、素子分離トレンチ
を配線領域として使用し、多層配線化した半導体装置を
提供することである。
SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a semiconductor device that uses an element isolation trench as a wiring region and has multilayer wiring.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による半導体装置は、素子分離トレンチの内部に
導電層を有することを特徴としている。
The semiconductor device according to the present invention is characterized by having a conductive layer inside the element isolation trench.

〔作 用〕[For production]

素子分離トレンチは、シリコン基板上に形成された深さ
が約1μmの溝に、絶縁物である二酸化シリコン(以下
5in2と称する)を充填した素子分離領域であるが、
この5in2中に導電層を形成することによって半導体
装置の一配線として作用し、またシリコン基板上の素子
を分離する。
An element isolation trench is an element isolation region in which a trench with a depth of about 1 μm formed on a silicon substrate is filled with silicon dioxide (hereinafter referred to as 5in2), which is an insulator.
By forming a conductive layer in this 5in2, it acts as one wiring of a semiconductor device and also isolates elements on the silicon substrate.

〔実 施 例〕〔Example〕

本発明の実施例について図面を用いて説明する。 Embodiments of the present invention will be described with reference to the drawings.

第1図は本発明による素子分離トレンチの断面図である
。シリコン基板11表面に設けられた溝〕2に5iOz
13を充填し、該SiO□中に導電層14を埋め込む。
FIG. 1 is a cross-sectional view of an isolation trench according to the present invention. 5 iOz in the groove]2 provided on the surface of the silicon substrate 11
13, and a conductive layer 14 is embedded in the SiO□.

本実施例の場合、素子分離トレンチの幅を約2μm1深
さ約1μmとすると、5IO2中に幅1..2μm、厚
さ0.2amの高融点金属シリサイド層を埋め込むこと
によってシート抵抗が10Ω/口程度の配線を形成でき
、MOSトランジスタのゲート電極を充分に駆動するこ
とができる。
In the case of this embodiment, if the width of the element isolation trench is about 2 μm and the depth is about 1 μm, the width is 1.5 μm in 5IO2. .. By embedding a refractory metal silicide layer of 2 μm and 0.2 am thick, a wiring with a sheet resistance of about 10 Ω/hole can be formed, and the gate electrode of the MOS transistor can be sufficiently driven.

素子分離トレンチ上に配置した配線と前述の高融点金属
シリサイドとの接合点は、素子分離トレンチに埋め込ま
れた高融点金属シリサイド上のSiO2を選択エツチン
グした後、エツチングによって得られた開口部に高融点
シリサイドを選択成長する事によって比較的容易に実現
できる。
The junction between the wiring placed on the element isolation trench and the above-mentioned high melting point metal silicide is determined by selectively etching the SiO2 on the high melting point metal silicide buried in the element isolation trench, and then etching a high-temperature layer into the opening obtained by etching. This can be achieved relatively easily by selectively growing melting point silicides.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明はシリコン基板表面に素子
分離トレンチを有する半導体装置において、該素子分離
トレンチ内部に導電層を有することによって半導体装置
の多層配線化を実現することができる。
As described above, in a semiconductor device having an isolation trench on the surface of a silicon substrate, the present invention can realize multilayer interconnection of the semiconductor device by providing a conductive layer inside the isolation trench.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による半導体装置の断面図、第2図は従
来技術によるLOGOS素子分離半導体装置の断面図、
第3図は従来技術によるトレンチ素子分離半導体装置の
断面図である。 11.21.31・・・シリコン基板 12.32・・・・・・溝 22・・・・・・・・・バースピーク 13.23.33・φ・Sigh 14・・・・・・・・・導電層 15.24.34・・・層間絶縁膜 16.25.35・・・配線 以上
FIG. 1 is a sectional view of a semiconductor device according to the present invention, FIG. 2 is a sectional view of a LOGOS element isolation semiconductor device according to the prior art,
FIG. 3 is a sectional view of a conventional trench isolation semiconductor device. 11.21.31...Silicon substrate 12.32...Groove 22...Birth peak 13.23.33・φ・Sigh 14...・Conductive layer 15.24.34...Interlayer insulating film 16.25.35...More than wiring

Claims (1)

【特許請求の範囲】[Claims]  シリコン基板表面に素子分離トレンチを有する半導体
装置において、該素子分離トレンチ内部に導電層を有す
ることを特徴とする半導体装置。
1. A semiconductor device having an isolation trench on a surface of a silicon substrate, the semiconductor device having a conductive layer inside the isolation trench.
JP20981190A 1990-08-08 1990-08-08 Semiconductor device Pending JPH0492426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20981190A JPH0492426A (en) 1990-08-08 1990-08-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20981190A JPH0492426A (en) 1990-08-08 1990-08-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0492426A true JPH0492426A (en) 1992-03-25

Family

ID=16578998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20981190A Pending JPH0492426A (en) 1990-08-08 1990-08-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0492426A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1746644A2 (en) * 1999-03-11 2007-01-24 Micron Technology, Inc. Methods of forming local interconnects and conductive lines, and resulting structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1746644A2 (en) * 1999-03-11 2007-01-24 Micron Technology, Inc. Methods of forming local interconnects and conductive lines, and resulting structure
EP1746644A3 (en) * 1999-03-11 2007-10-10 Micron Technology, Inc. Methods of forming local interconnects and conductive lines, and resulting structure

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