JPH0482233A - Die-bonding method of semiconductor element - Google Patents

Die-bonding method of semiconductor element

Info

Publication number
JPH0482233A
JPH0482233A JP19647490A JP19647490A JPH0482233A JP H0482233 A JPH0482233 A JP H0482233A JP 19647490 A JP19647490 A JP 19647490A JP 19647490 A JP19647490 A JP 19647490A JP H0482233 A JPH0482233 A JP H0482233A
Authority
JP
Japan
Prior art keywords
preform
oxide film
carrier
semiconductor element
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19647490A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Hideaki Nishizawa
秀明 西沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP19647490A priority Critical patent/JPH0482233A/en
Publication of JPH0482233A publication Critical patent/JPH0482233A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PURPOSE:To fix a semiconductor chip to a carrier by using a preform in which an oxide film does not exist on the surface. CONSTITUTION:A foillike preform 2 composed of a eutectic alloy is placed in a prescribed part on a carrier 1. An oxide film which is formed during the storage exists on the surface of the preform 2. The oxide film which has been formed on the surface is removed in an inert gas atmosphere. After the oxide film on the surface of the preform 2 has been removed in this manner, a semiconductor element 5 is placed on the preform 2 in a vacuum. Then, the preform 2 is heated and melted while the atmosphere is being kept; a eutectic reaction is caused; and the element 5 is fixed to the carrier 1 by using the preform 2 as a bonding material. When this method is used, a die-bonding operation of an MMIC whose thickness is at 100mum or lower can be executed with high reliability although it was difficult by conventional methods.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ICやLSI等の半導体素子をパッケージや
基板等に固定するダイボンディング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a die bonding method for fixing semiconductor elements such as ICs and LSIs to packages, substrates, and the like.

〔従来の技術〕[Conventional technology]

従来、ICやLSI等の半導体素子をパッケージや基板
等の担体に固定(ダイボンディング)する場合、AuS
iやAuSn等の共晶合金からなる箔状のプリフォーム
を担体と半導体素子との間に挿入し、プリフォームを溶
融させて共晶反応を起こさせ、半導体素子を担体に固定
することが行われでいる。
Conventionally, when fixing (die bonding) semiconductor elements such as ICs and LSIs to carriers such as packages and substrates, AuS
A foil-shaped preform made of a eutectic alloy such as i or AuSn is inserted between a carrier and a semiconductor element, and the preform is melted to cause a eutectic reaction, thereby fixing the semiconductor element to the carrier. It's me.

しかし、共晶合金からなるプリフォームの表面は酸化し
易く、例えば、AuSiの共晶合金ではSiOが、Au
Snの共晶合金ではS n 02等の酸化膜が、その表
面に形成してしまう。このような酸化膜を介して、半導
体素子を基板等にダイボンディングすると、その固定部
において、熱抵抗を上昇させたり、導電性を低下させる
原因になると共に、半導体素子の固定強度を低下させて
しまうことかある。
However, the surface of a preform made of a eutectic alloy is easily oxidized; for example, in a eutectic alloy of AuSi, SiO is
In the case of a Sn eutectic alloy, an oxide film such as Sn 02 is formed on its surface. Die bonding a semiconductor element to a substrate, etc. through such an oxide film causes an increase in thermal resistance and a decrease in conductivity at the fixing part, and also reduces the fixing strength of the semiconductor element. Sometimes I have to put it away.

そこで、ダイボンディング時の酸化を防止すべく、真空
雰囲気中(10−2Torr以下)あるいは数%の水素
Hを含む窒素N2等の不活性ガス中でダイボンディング
を行うことも考えられるが、このプリフォームはダイボ
ンディング時ばかりでなく、その保存中にも、はんの僅
な酸素の存在によっても酸化され、50〜100オング
ストロ一ム程度の表面酸化膜が形成されてしまう。そこ
で、ダイボンディングの際、半導体素子にこれを保持す
る保持手段を通じて振動を与えて酸化膜を破りダイボン
ディングを行うスクラブ等の手法が用いられている。
Therefore, in order to prevent oxidation during die bonding, it is possible to perform die bonding in a vacuum atmosphere (below 10-2 Torr) or in an inert gas such as nitrogen N2 containing a few percent of hydrogen H. The solder is oxidized not only during die bonding but also during storage due to the presence of a small amount of oxygen, resulting in the formation of a surface oxide film of about 50 to 100 angstroms. Therefore, during die bonding, a method such as scrubbing is used in which vibration is applied to the semiconductor element through a holding means that holds the semiconductor element to break the oxide film and perform die bonding.

〔発明か解決しようとする課題〕[Invention or problem to be solved]

しかしながら、このスクラブ法では、半導体素子が大き
くなると、半導体素子が担体上で所定の位置から動いて
しまったり、また、半導体素子が薄くなると保持手段が
半導体素子を保持しきれず、振動を与える際に保持手段
が半導体素子の表面に傷を付けてしまったりすることか
あった。更に、GaAs ICやモノリシックマイクロ
IC(MMIC)等の脆弱な半導体素子では、振動を与
えた際に半導体素子が破損するおそれがあった。
However, with this scrubbing method, when the semiconductor element becomes large, the semiconductor element may move from a predetermined position on the carrier, and when the semiconductor element becomes thin, the holding means cannot fully hold the semiconductor element, and when applying vibration, In some cases, the holding means may scratch the surface of the semiconductor element. Furthermore, with fragile semiconductor elements such as GaAs ICs and monolithic micro ICs (MMICs), there is a risk that the semiconductor elements will be damaged when vibrations are applied.

そこで、本発明は上記問題点を解決し、高品質な共晶ボ
ンディング法を提供することを目的としている。
Therefore, an object of the present invention is to solve the above problems and provide a high-quality eutectic bonding method.

〔課題を解決するための手段〕[Means to solve the problem]

上述の目的を達成するため、本発明の半導体素子のダイ
ボンディング方法は、担体上に載置された共晶合金から
なるプリフォームの表面酸化物層を実質的な無酸素雰囲
気中で除去する工程と、これに引き続いてプリフォーム
に対し、実質的な無酸素雰囲気中で半導体素子を載置し
た後、プリフォームを溶融し、共晶反応を利用して半導
体素子を担体に固定する工程とを備えたことを特徴とす
る。
In order to achieve the above object, the die bonding method for a semiconductor device of the present invention includes a step of removing a surface oxide layer of a preform made of a eutectic alloy placed on a carrier in a substantially oxygen-free atmosphere. This is followed by a step of placing a semiconductor element on the preform in a substantially oxygen-free atmosphere, melting the preform, and fixing the semiconductor element to the carrier using a eutectic reaction. It is characterized by being equipped.

〔作用〕[Effect]

本発明は上記のように構成し、共晶合金のプリフォーム
表面上の酸化膜を除去している。そのため、酸化膜を介
在させない状態で半導体チップを担体にダイボンディン
グできる。
The present invention is configured as described above, and the oxide film on the surface of the eutectic alloy preform is removed. Therefore, the semiconductor chip can be die-bonded to the carrier without an oxide film intervening.

〔実施例〕〔Example〕

以下、本発明の実施例について第1図を参照しつつ、説
明する。
Embodiments of the present invention will be described below with reference to FIG.

第1図は本発明が適用されたダイボンディングの工程順
に担体等の断面を示した図である。まず、同図(a)に
示したように、担体1上の所定箇所に共晶合金からなる
箔状のプリフォーム2が載置される。このプリフォーム
2の表面にはその保存中に形成された酸化膜3が存在し
ている。そして、同図(b)に示したように、プリフォ
ーム2の表面層がAr等の不活性ガス雰囲気(プリフォ
ーム2の表面に酸化膜が形成されない程度の実質的な無
酸素雰囲気)中で除去され、その表面に形成されていた
酸化膜3が除去される。酸化膜3の除去は、例えばプラ
ズマエツチングにより行うことができるし、スパッタエ
ツチングにより行うことも可能である。
FIG. 1 is a diagram showing cross sections of a carrier, etc. in the order of die bonding steps to which the present invention is applied. First, as shown in FIG. 2A, a foil-shaped preform 2 made of a eutectic alloy is placed at a predetermined location on a carrier 1. An oxide film 3 formed during storage is present on the surface of this preform 2. As shown in FIG. 2(b), the surface layer of the preform 2 is placed in an inert gas atmosphere such as Ar (substantially oxygen-free atmosphere to the extent that no oxide film is formed on the surface of the preform 2). The oxide film 3 formed on the surface is removed. The oxide film 3 can be removed by, for example, plasma etching or sputter etching.

このようにして、プリフォーム2表面の酸化膜が除去さ
れた後、プリフォーム2が外気に触れることがないよう
に、プリフォーム2のまわりの真空引きが行われる。そ
して、同図(c)に示したように、真空中でプリフォー
ム2上に半導体素子5か載置される。なお、上述した真
空引きは省略することも可能であり、この場合には酸化
膜除去の際の不活性雰囲気中でそのままプリフォーム2
上に半導体素子5が載置される。また、真空引きの代わ
りに、不活性ガス雰囲気を入れ替えることとしてもよく
、この場合には入れ替え後の不活性ガス雰囲気中でプリ
フォーム2上に半導体素子5か載置される。
After the oxide film on the surface of the preform 2 is removed in this way, the area around the preform 2 is evacuated so that the preform 2 does not come into contact with the outside air. Then, as shown in FIG. 2C, the semiconductor element 5 is placed on the preform 2 in a vacuum. Note that the vacuum evacuation described above can be omitted, and in this case, the preform 2 can be directly removed in an inert atmosphere during oxide film removal.
A semiconductor element 5 is placed thereon. Further, instead of evacuation, the inert gas atmosphere may be replaced, and in this case, the semiconductor element 5 is placed on the preform 2 in the replaced inert gas atmosphere.

次いで、その雰囲気(実質的な無酸素雰囲気)のままプ
リフォーム2が加熱溶融させられ、共晶反応が惹起され
て半導体素子5が担体1上にプリフォーム2を接合材と
して固定される。なお、半導体素子5は単にその自重で
プリフォーム2上に載っているだけてもよいが、プリフ
ォーム2が溶融された際に、半導体素子5はコレット等
の保持手段により担体1に対して軽く押し付けられるこ
とが好ましい。押し付けられることによって、プリフォ
ーム2と半導体素子5との密着性が増し共晶反応による
接着面積が増大する。
Next, the preform 2 is heated and melted in that atmosphere (substantially oxygen-free atmosphere), a eutectic reaction is induced, and the semiconductor element 5 is fixed onto the carrier 1 using the preform 2 as a bonding material. Note that the semiconductor element 5 may simply be placed on the preform 2 by its own weight, but when the preform 2 is melted, the semiconductor element 5 is lightly held against the carrier 1 by a holding means such as a collet. Preferably, it is pressed. By being pressed, the adhesion between the preform 2 and the semiconductor element 5 increases, and the adhesion area due to the eutectic reaction increases.

上記方法を用いることにより、従来では困難であった厚
さが100μm以下のMMICでの信頼性の高いダイボ
ンディングか可能になった。具体的には、上述した工程
を適用することにより、厚さ100μm以下の3u角サ
イズのMMICチップをボイドの発生を伴わずに高い信
頼性をもってダイボンディングできた。また、プリフォ
ーム2表面の酸化膜3を除去した後、ダイボンディング
を行っているので、プリフォーム2と半導体素子5との
界面に酸化膜の存在しなくなり、熱抵抗が低く、導電性
を高めることができた。
By using the above method, it has become possible to perform highly reliable die bonding on MMICs with a thickness of 100 μm or less, which was difficult in the past. Specifically, by applying the above-described process, it was possible to die-bond a 3U square MMIC chip with a thickness of 100 μm or less with high reliability without generating voids. In addition, since die bonding is performed after removing the oxide film 3 on the surface of the preform 2, there is no oxide film at the interface between the preform 2 and the semiconductor element 5, resulting in low thermal resistance and increased conductivity. I was able to do that.

また、厚さ450μmの5〜IC1us角サイズのLS
Iを99%以上の歩留まりでダイボンディングできた。
In addition, LS with a thickness of 450 μm and a square size of 5 to IC1us
It was possible to die bond I with a yield of 99% or more.

なお、上述した実施例においては、ブリフォム2として
厚さ50μmでSnの重量比が20%のAuSn共晶合
金(融点280℃)からなるものを用いた。
In the above-described embodiment, the Buriform 2 was made of an AuSn eutectic alloy (melting point: 280° C.) with a thickness of 50 μm and a weight ratio of Sn of 20%.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば表面に酸化膜が存
在しないプリフォームを用いて半導体チップを担体に固
定できるようになる。したがって、高品質の共晶ダイボ
ンディングを安定して行うことができる。特に、スクラ
ブすることが困難な脆弱なGaAs IC等の半導体素
子や偏平構造を有するMM I C等の半導体素子に適
用すると有効である。
As explained above, according to the present invention, a semiconductor chip can be fixed to a carrier using a preform having no oxide film on its surface. Therefore, high quality eutectic die bonding can be stably performed. It is particularly effective when applied to fragile semiconductor devices such as GaAs ICs that are difficult to scrub, and semiconductor devices such as MM ICs that have a flat structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明が適用されたダイボンディングの工程順
に担体等の断面を示した図である。 1・・・担体、2・・・プリフォーム、3・・・酸化膜
、5・・・半導体素子。
FIG. 1 is a diagram showing cross sections of a carrier, etc. in the order of die bonding steps to which the present invention is applied. DESCRIPTION OF SYMBOLS 1... Carrier, 2... Preform, 3... Oxide film, 5... Semiconductor element.

Claims (1)

【特許請求の範囲】  共晶合金からなる箔状のプリフォームを接合材として
用い、半導体素子を担体に固定する半導体素子のダイボ
ンディング方法であって、 前記担体上に載置された前記プリフォームの表面酸化物
層を実質的な無酸素雰囲気中で除去する工程と、 これに引き続いて前記プリフォームに対し、実質的な無
酸素雰囲気中で半導体素子を載置した後、前記プリフォ
ームを溶融し共晶反応を利用して、半導体素子を前記担
体に固定する工程とを備えたことを特徴とする半導体素
子のダイボンディング方法。
[Scope of Claims] A die bonding method for a semiconductor device in which a semiconductor device is fixed to a carrier using a foil-shaped preform made of a eutectic alloy as a bonding material, the preform being placed on the carrier. removing a surface oxide layer of the preform in a substantially oxygen-free atmosphere, followed by placing a semiconductor device on the preform in a substantially oxygen-free atmosphere, and then melting the preform. A method for die bonding a semiconductor device, comprising the step of fixing the semiconductor device to the carrier using a eutectic reaction.
JP19647490A 1990-07-25 1990-07-25 Die-bonding method of semiconductor element Pending JPH0482233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19647490A JPH0482233A (en) 1990-07-25 1990-07-25 Die-bonding method of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19647490A JPH0482233A (en) 1990-07-25 1990-07-25 Die-bonding method of semiconductor element

Publications (1)

Publication Number Publication Date
JPH0482233A true JPH0482233A (en) 1992-03-16

Family

ID=16358404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19647490A Pending JPH0482233A (en) 1990-07-25 1990-07-25 Die-bonding method of semiconductor element

Country Status (1)

Country Link
JP (1) JPH0482233A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149976A (en) * 2005-11-28 2007-06-14 Stanley Electric Co Ltd Eutectic bonding light-emitting device and manufacturing method therefor
JP2009010133A (en) * 2007-06-27 2009-01-15 Mitsubishi Electric Corp Profiling device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149976A (en) * 2005-11-28 2007-06-14 Stanley Electric Co Ltd Eutectic bonding light-emitting device and manufacturing method therefor
JP2009010133A (en) * 2007-06-27 2009-01-15 Mitsubishi Electric Corp Profiling device

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