JPH0480049U - - Google Patents
Info
- Publication number
- JPH0480049U JPH0480049U JP1990124652U JP12465290U JPH0480049U JP H0480049 U JPH0480049 U JP H0480049U JP 1990124652 U JP1990124652 U JP 1990124652U JP 12465290 U JP12465290 U JP 12465290U JP H0480049 U JPH0480049 U JP H0480049U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- wire
- long
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000002452 interceptive effect Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990124652U JPH0480049U (US20020051482A1-20020502-M00012.png) | 1990-11-27 | 1990-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990124652U JPH0480049U (US20020051482A1-20020502-M00012.png) | 1990-11-27 | 1990-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0480049U true JPH0480049U (US20020051482A1-20020502-M00012.png) | 1992-07-13 |
Family
ID=31872289
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990124652U Pending JPH0480049U (US20020051482A1-20020502-M00012.png) | 1990-11-27 | 1990-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0480049U (US20020051482A1-20020502-M00012.png) |
-
1990
- 1990-11-27 JP JP1990124652U patent/JPH0480049U/ja active Pending
