JPH0474863B2 - - Google Patents
Info
- Publication number
- JPH0474863B2 JPH0474863B2 JP62271137A JP27113787A JPH0474863B2 JP H0474863 B2 JPH0474863 B2 JP H0474863B2 JP 62271137 A JP62271137 A JP 62271137A JP 27113787 A JP27113787 A JP 27113787A JP H0474863 B2 JPH0474863 B2 JP H0474863B2
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- circuit board
- electrode
- protruding
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 23
- 239000010410 layer Substances 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 2
- 238000002594 fluoroscopy Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Description
【発明の詳細な説明】 〔技術分野〕 この発明は、IC実装用回路基板に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a circuit board for IC mounting.
ICをIC実装用回路基板に実装するには、たと
えば、第２図にみるように、AuやAlの細線１を
用いてIC２の電極３とIC実装用回路基板４の電
路５とを電気的に接続するというワイヤボンデイ
ングが利用されている。しかし、ワイヤボンデイ
ングでは、電極数の増加に伴つてボンデイングに
要する時間が増大するので、高密度実装や高集積
化に対応することが困難になつてきている。
To mount an IC on a circuit board for IC mounting, for example, as shown in FIG. Wire bonding is used to connect to. However, in wire bonding, the time required for bonding increases as the number of electrodes increases, making it difficult to support high-density packaging and high integration.
そこで、突起電極を用いて、ICの電極とIC実
装用回路基板の電路とを一括して電気的に接続す
るという、ギヤングボンデイング法が提案されて
いる。この方法には、ICの方に突起電極を設け
る方法と、IC実装用回路基板の方に突起電極を
設ける方法とがある。前者の方法の１つにフリツ
プチツプ法というのがある。これは、第３図ａに
みるように、IC２に突起電極（バンプ）６を設
け、これらの突起電極６を一括してIC実装用回
路基板４の各電路５に熱圧着するという方法であ
る。しかし、この方法では、ICの製造工程にお
いて、突起電極を形成するという工程を付加する
必要がある。この工程では、第３図ｂにみるよう
に、突起電極６の主な材料であるAuやはんだ等
がIC２内へ拡散するのを防ぐバリアメタル層７
や、IC−突起電極間の接合力を高める接着層８
を形成する必要があり、複雑で高価なものにな
る。図中、９はパツシベーシヨン層、１０はIC
のAl電極である。 Therefore, a gigantic bonding method has been proposed in which the electrodes of the IC and the electric paths of the IC mounting circuit board are electrically connected together using protruding electrodes. This method includes a method in which a protruding electrode is provided on the IC, and a method in which a protruding electrode is provided on the IC mounting circuit board. One of the former methods is the flip-chip method. As shown in FIG. 3a, this is a method in which protruding electrodes (bumps) 6 are provided on the IC 2, and these protruding electrodes 6 are thermocompression bonded to each electric circuit 5 of the IC mounting circuit board 4. . However, this method requires an additional step of forming protruding electrodes in the IC manufacturing process. In this process, as shown in FIG.
and an adhesive layer 8 that increases the bonding strength between the IC and the protruding electrode.
, which is complex and expensive. In the figure, 9 is the passivation layer, 10 is the IC
This is an Al electrode.
これに対し、第４図にみるように、IC実装用
回路基板４の方にペデスタルと称される突起電極
１２を形成しておき、IC２をボンデイングする
という方法（「ペデスタル法」ということもある）
も提案されている。この方法は、ICを新たに加
工する必要がなく、しかも、IC側に突起電極を
設ける方法に比べて、安価に突起電極を形成でき
るという利点がある。しかし、IC実装用回路基
板側の突起電極とICの電極との位置合わせに高
い精度が要求される上、IC実装用回路基板とIC
とを接合すると、接続部がICと基板との間に隠
れてしまうため、突起電極とICの電極との位置
合わせや接合状態を確認できないという問題点が
ある。 On the other hand, as shown in FIG. 4, there is a method (sometimes called the "pedestal method") in which a protruding electrode 12 called a pedestal is formed on the IC mounting circuit board 4 and the IC 2 is bonded. )
has also been proposed. This method has the advantage that it is not necessary to newly process the IC, and that the protruding electrode can be formed at a lower cost than the method of providing the protruding electrode on the IC side. However, high precision is required for alignment between the protruding electrodes on the IC mounting circuit board side and the IC electrodes, and the IC mounting circuit board and IC
When these are bonded together, the connection part is hidden between the IC and the substrate, so there is a problem in that it is impossible to check the alignment and bonding status between the protruding electrode and the IC electrode.
この発明は、以上のことに鑑みて、ICを実装
した後に、ICと基板上の突起電極との相対位置
を確認することができるIC実装用回路基板を提
供することを目的とする。
In view of the above, an object of the present invention is to provide a circuit board for mounting an IC on which the relative position of the IC and the protruding electrodes on the board can be confirmed after the IC is mounted.
この発明は、上記目的を達成するため、絶縁層
表面に形成された電路上に突起電極が設けられて
いて、同突起電極とICの電極とがボンデイング
されるようになつているIC実装用回路基板にお
いて、前記絶縁層表面の前記ICの外形よりも外
側の部分には、前記突起電極の形成と同時に形成
された位置決め用突起が設けられていることを特
徴とするIC実装用回路基板を要旨とする。
In order to achieve the above object, the present invention provides an IC mounting circuit in which a protruding electrode is provided on a conductor formed on the surface of an insulating layer, and the protruding electrode and an electrode of an IC are bonded. Abstract: A circuit board for mounting an IC, characterized in that a positioning protrusion formed at the same time as the formation of the protruding electrode is provided on a portion of the surface of the insulating layer outside the outer shape of the IC. shall be.
以下に、この発明を、その実施例を表す図面を
参照しながら詳しく説明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings showing embodiments thereof.
第１図ａおよびｂは、この発明にかかるIC実
装用回路基板の１実施例を表す。これらの図にみ
るように、このIC実装用回路基板１４は、絶縁
層１６の表面上に所望の電路５が形成されてい
る。各電路５のIC（半導体素子）２の電極３との
ボンデイング部分には、突起電極（「バンプ」と
もいう）１２が設けられている。各電路５の前記
ボンデイング部分は、四方から四角い空所を形成
するように臨んでいる。その１組の対角位置に臨
んでいる２つの電路５ａ，５ａは、それぞれ、側
方へ枝分かれしていてその先端に位置決め用突起
１７，１７が設けられている。これら位置決め用
突起１７，１７は、ICが実装された時に、その
外形よりも外側となるところに位置している。 FIGS. 1a and 1b show one embodiment of an IC mounting circuit board according to the present invention. As shown in these figures, in this IC mounting circuit board 14, a desired electric path 5 is formed on the surface of an insulating layer 16. A protruding electrode (also referred to as a "bump") 12 is provided at a bonding portion of each electric path 5 with an electrode 3 of an IC (semiconductor element) 2. The bonding portion of each electric circuit 5 faces from all sides so as to form a square void. The two electric circuits 5a, 5a facing the pair of diagonal positions are branched laterally, and positioning protrusions 17, 17 are provided at their tips. These positioning protrusions 17, 17 are located outside the outer shape of the IC when it is mounted.
IC実装用回路基板にボンデイング用の突起電
極を形成するには、たとえば、下記のようにして
行うが、これに限定されない。絶縁層の上に所望
のパターンで電路となる導体層を形成する。前記
パターンは、たとえば、第１図ａにみるように、
ボンデイング用の電路と位置決め用突起を形成す
るための電路からなる。この上にホトレジストを
塗布して前記導体層を覆い、ホトリソグラフイー
法により、導体層上の必要な位置にホトレジスト
の孔をあける。このとき、位置決め用突起を設け
るための孔もあける。そして、前記電路を電極と
して、それらの孔の中を電気メツキ等によりAu
等の突起電極用材料で埋めて、前記導体層の上に
突起電極と位置決め用突起を形成する。各突起電
極の相対位置は、ホトリソグラフイー工程のマス
ク精度（マスクのパターン精度）と等しく、通
常、0.1μｍ以下のいずれである。また、各突起電
極と位置決め用突起との相対位置も同様の精度で
ある。これらの精度は、ICを実装するときの位
置合わせ精度に比べて問題にならないくらい高い
レベルである。他方、電路に対する突起電極の位
置精度は、マスク位置合わせ精度に依存するた
め、1μｍ以上のオーダーのずれが生じる。 Forming protruding electrodes for bonding on a circuit board for IC mounting can be performed, for example, in the following manner, but the present invention is not limited thereto. A conductive layer serving as an electric path is formed in a desired pattern on the insulating layer. The pattern may be, for example, as shown in FIG.
It consists of an electric path for bonding and an electric path for forming positioning protrusions. A photoresist is applied thereon to cover the conductor layer, and holes are made in the photoresist at required positions on the conductor layer by photolithography. At this time, holes for providing positioning protrusions are also made. Then, using the electrical circuit as an electrode, the inside of these holes is filled with Au by electroplating or the like.
A protruding electrode and a positioning protrusion are formed on the conductor layer by filling the conductive layer with a protruding electrode material such as the like. The relative position of each protruding electrode is equal to the mask precision (mask pattern precision) of the photolithography process, and is usually 0.1 μm or less. Further, the relative positions of each protruding electrode and the positioning protrusion have similar accuracy. These accuracy levels are so high that they are not a problem compared to the alignment accuracy when mounting ICs. On the other hand, since the positional accuracy of the protruding electrode with respect to the electric path depends on the mask alignment accuracy, a deviation on the order of 1 μm or more occurs.
したがつて、ICのIC実装用回路基板への位置
合わせをICの外形と基板上の電路とで行うと、
ICの電極とIC実装用回路基板の突起電極とがず
れてしまい、電気的な接続が行えないことがあ
る。 Therefore, when aligning the IC to the IC mounting circuit board based on the IC outline and the circuit board on the board,
The electrodes of the IC and the protruding electrodes of the circuit board for IC mounting may become misaligned, and electrical connection may not be possible.
そこで、前述のごとく、実装しようとするIC
の外形よりも少し外側に、位置決め用突起（これ
は電気的接続に関与しないので、「ダミーバンプ」
である）を設けておき、この突起とICの外形と
の間隔を測定すれば、ICの電極と突起電極との
位置精度が確認できる。 Therefore, as mentioned above, the IC to be implemented is
A positioning protrusion (a "dummy bump" as it does not participate in electrical connection) is placed slightly outside the outline of the
), and by measuring the distance between this protrusion and the outer shape of the IC, the positional accuracy of the IC electrode and the protrusion electrode can be confirmed.
前記絶縁層としては、たとえば、アルミナ基板
等のセラミツク基板、ガラスエポキシ基板等の樹
脂を用いた基板などがあり、特に限定はない。導
体層の材料も特に限定はなく、たとえば、金属銅
などが用いられる。導体層の形成方法も特に限定
はなく、たとえば、メツキ・真空蒸着・スパツタ
リング等により薄膜を形成して所望のパターンを
残してエツチングするという方法で形成すること
ができる。ICの電極は、特に限定はないが、た
とえば、Al電極などが使用される。 The insulating layer may be, for example, a ceramic substrate such as an alumina substrate, a substrate made of resin such as a glass epoxy substrate, etc., and is not particularly limited. The material of the conductor layer is also not particularly limited, and for example, metal copper or the like may be used. The method of forming the conductor layer is not particularly limited either, and it can be formed, for example, by forming a thin film by plating, vacuum evaporation, sputtering, etc., and then etching it leaving a desired pattern. The electrode of the IC is not particularly limited, but for example, an Al electrode is used.
この発明において、突起電極の形成と位置決め
用突起の形成とを同時に行うのは、位置決め用突
起と突起電極との位置精度を突起電極同士の位置
精度と同程度にするためである。上記実施例で
は、ホトレジストのホトリソグラフイー工程で、
位置決め用突起と突起電極となる部分のホトレジ
ストに孔をあけることにより、位置決め用突起と
突起電極との位置精度を得ている。しかし、この
位置精度を得るためには、ホトレジストの必要な
部分にホトリソグラフイーにより孔をあけるとい
う方法を利用する必要はない。また、ホトリソグ
ラフイー工程の後、電気メツキによらず、化学メ
ツキ・真空蒸着・スパツタリング等によつて突起
電極と位置決め用突起を形成してもよく、突起電
極と位置決め用突起とを別の手段で形成してもよ
い。要するに、位置決め用突起と各突起電極との
位置精度が各突起電極相互間の位置精度と同程度
となるのであれば、上記以外のやり方でで行つて
もよいのである。 In this invention, the reason why the protruding electrodes and the positioning protrusions are formed at the same time is to make the positional accuracy between the positioning protrusions and the protruding electrodes comparable to the positional accuracy between the protruding electrodes. In the above embodiment, in the photoresist photolithography process,
By drilling holes in the photoresist at the portions that will become the positioning protrusions and protruding electrodes, the positioning accuracy of the positioning protrusions and protruding electrodes is obtained. However, in order to obtain this positional accuracy, it is not necessary to use a method of making holes by photolithography in the necessary portions of the photoresist. Further, after the photolithography process, the protruding electrodes and positioning protrusions may be formed by chemical plating, vacuum evaporation, sputtering, etc. instead of electroplating, or the protruding electrodes and positioning protrusions may be formed by another method. It may be formed by In short, as long as the positional accuracy between the positioning protrusion and each protrusion electrode is comparable to the positional accuracy between the protrusion electrodes, methods other than those described above may be used.
この発明にかかるIC実装用回路基板は、突起
電極の形成と同時に形成された位置決め用突起を
有するので、ICを実装するときに、その位置決
め用突起を利用して位置合わせ状態を確認するこ
とができる。しかも、その位置合わせ精度が高
い。IC実装後の位置合わせ状態の確認は、超音
波・赤外線顕微鏡・Ｘ線透視装置等の高価な設備
を用いる必要がなく、しかも、非破壊で行うこと
ができる。これにより、IC実装工程のスピード
向上、設備投資のコストダウンを図ることがで
き、全体として実装コストの低減を図ることがで
きる。また、位置決め用突起と突起電極の形成を
同時に行えば、工程が少なくてすみ、精度も同程
度にすることができる。 The IC mounting circuit board according to the present invention has positioning protrusions formed at the same time as the protruding electrodes are formed, so when mounting an IC, the positioning protrusions can be used to confirm the alignment state. can. Furthermore, the alignment accuracy is high. Confirming the alignment state after IC mounting does not require the use of expensive equipment such as ultrasonic waves, infrared microscopes, or X-ray fluoroscopy equipment, and can be performed non-destructively. As a result, it is possible to speed up the IC mounting process, reduce equipment investment costs, and reduce overall mounting costs. Furthermore, if the positioning protrusions and the protruding electrodes are formed at the same time, the number of steps can be reduced and the accuracy can be maintained at the same level.
なお、この発明にかかるIC実装用回路基板は、
上記実施例に限定されない。たとえば、位置決め
用突起は、実装しようとするICの対角位置に２
つ設けていたが、３つ以上でもよく、１つでもよ
い。精度をより高めるという点からは、位置決め
用突起は２つ以上設けることが好ましい。また、
その設ける位置も、ICとの間隔の計測が容易な
場所であれば、特に限定はなく、電路の上に形成
される必要もない。位置決め用突起の形状も、円
形に限らず、四角形などの多角形やＬ字形などで
あつてもよい。位置決め用突起の材料も導体であ
る必要はない。 Note that the circuit board for IC mounting according to the present invention is
It is not limited to the above embodiments. For example, the positioning protrusions should be placed at two diagonal positions of the IC to be mounted.
Although three or more were provided, it may be three or more, or one. In order to further improve accuracy, it is preferable to provide two or more positioning protrusions. Also,
The position where it is provided is not particularly limited as long as it is easy to measure the distance between it and the IC, and it does not need to be formed above the electric path. The shape of the positioning protrusion is not limited to a circle, but may be a polygon such as a quadrangle, an L-shape, or the like. The material of the positioning protrusion also does not need to be a conductor.
この発明にかかるIC実装用回路基板は、以上
のように、絶縁層表面のICの外形よりも外側の
部分には、突起電極の形成と同時に形成された位
置決め用突起が設けられているので、ICを精度
良くボンデイングすることができる。ボンデイン
グ後は、超音波、赤外線顕微鏡あるいはＸ線透視
装置などといつた高価な設備を用いずに、しか
も、破壊を行わずに、突起電極とICの電極の位
置精度が確認できる。このため、工程のスピード
向上、設備投資のコストダウンを図ることがで
き、全体的に実装コストの低減を図ることができ
る。
As described above, in the IC mounting circuit board according to the present invention, the positioning protrusion is provided on the surface of the insulating layer on the outside of the IC outline, and is formed at the same time as the protruding electrode. ICs can be bonded with high precision. After bonding, the positional accuracy of the protruding electrodes and the IC electrodes can be confirmed without using expensive equipment such as ultrasonic waves, infrared microscopes, or X-ray fluoroscopy equipment, and without causing damage. Therefore, it is possible to improve the speed of the process, reduce the cost of equipment investment, and reduce the overall mounting cost.
第１図ａはこの発明にかかるIC実装用回路基
板にICを搭載した状態を表す一部分の平面図、
第１図ｂはその搭載直前の断面図、第２図・第３
図ａ・第４図はそれぞれ従来のボンデイングのや
り方を表す一部分の側面図、第３図ｂはIC側に
形成する突起電極の１例を表す断面図である。
２…IC、３…ICの電極、５，５ａ…電路、１
２…突起電極、１４…IC実装用回路基板、１６
…絶縁層、１７…位置決め用突起。
FIG. 1a is a partial plan view showing a state in which an IC is mounted on a circuit board for IC mounting according to the present invention;
Figure 1b is a sectional view just before installation, Figures 2 and 3
Figures a and 4 are partial side views showing conventional bonding methods, and Figure 3b is a sectional view showing an example of a protruding electrode formed on the IC side. 2...IC, 3...IC electrode, 5,5a...electrical circuit, 1
2... Projection electrode, 14... Circuit board for IC mounting, 16
...Insulating layer, 17...Positioning protrusion.
Claims (1)
設けられていて、同突起電極とICの電極とがボ
ンデイングされるようになつているIC実装用回
路基板において、前記絶縁層表面の前記ICの外
形よりも外側の部分には、前記突起電極の形成と
同時に形成された位置決め用突起が設けられてい
ることを特徴とするIC実装用回路基板。1. In a circuit board for IC mounting, in which a protruding electrode is provided on the electric conductor formed on the surface of the insulating layer, and the protruding electrode and the electrode of the IC are bonded, the IC on the surface of the insulating layer is provided. A circuit board for IC mounting, characterized in that a positioning protrusion formed at the same time as the formation of the protruding electrode is provided on a portion outside the outer shape of the IC mounting circuit board.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62271137A JPH01112743A (en) | 1987-10-27 | 1987-10-27 | Ic packaging circuit board |
| DE3817600A DE3817600C2 (en) | 1987-05-26 | 1988-05-24 | Method of manufacturing a semiconductor device with a ceramic substrate and an integrated circuit |
| FR8806997A FR2617335B1 (en) | 1987-05-26 | 1988-05-26 | CERAMIC CONNECTION SUBSTRATE PROVIDED WITH CONNECTION PROTUBERANCES TO THE INTEGRATED CIRCUIT PELLET |
| US07/504,028 US5126818A (en) | 1987-05-26 | 1990-04-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62271137A JPH01112743A (en) | 1987-10-27 | 1987-10-27 | Ic packaging circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01112743A JPH01112743A (en) | 1989-05-01 |
| JPH0474863B2 true JPH0474863B2 (en) | 1992-11-27 |
Family
ID=17495831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62271137A Granted JPH01112743A (en) | 1987-05-26 | 1987-10-27 | Ic packaging circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01112743A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005347299A (en) | 2004-05-31 | 2005-12-15 | Shinko Electric Ind Co Ltd | Method for manufacturing built-in chip substrate |
-
1987
- 1987-10-27 JP JP62271137A patent/JPH01112743A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01112743A (en) | 1989-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7161242B2 (en) | Semiconductor device, semiconductor device substrate, and manufacturing method thereof that can increase reliability in mounting a semiconductor element | |
| KR100595885B1 (en) | Wiring structure on semiconductor substrate and method of fabricating the same | |
| JP3258764B2 (en) | Method for manufacturing resin-encapsulated semiconductor device, external lead-out electrode and method for manufacturing the same | |
| EP0690490B1 (en) | Method of making a flip chip using electrically conductive polymers and dielectrics | |
| KR100264479B1 (en) | Structure of bump electrode and method of forming the same | |
| US4466181A (en) | Method for mounting conjoined devices | |
| US6236112B1 (en) | Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate | |
| JP2001127240A (en) | Method of manufacturing semiconductor device | |
| JP2002134545A (en) | Semiconductor integrated circuit chip, board and their manufacturing method | |
| TW201407737A (en) | Hybrid wiring board with built-in stopper, interposer and build-up circuitry | |
| US11315848B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| US6687989B1 (en) | Method for fabricating interconnect having support members for preventing component flexure | |
| JP2001156203A (en) | Printed wiring board for mounting semiconductor chip | |
| JPH09129669A (en) | Electric connection structure between semiconductor chip and substrate | |
| JP2951882B2 (en) | Semiconductor device manufacturing method and semiconductor device manufactured using the same | |
| JPS62230027A (en) | Manufacture of semiconductor device | |
| JPH0425038A (en) | Semiconductor device and manufacture of the same and electronic circuit utilizing the semiconductor device | |
| JPH0474863B2 (en) | ||
| JPH0922912A (en) | Semiconductor device and manufacture thereof | |
| JP2002151801A (en) | Circuit board structure and its manufacturing method | |
| JP2002231765A (en) | Semiconductor device | |
| JP3598189B2 (en) | Chip size package, its manufacturing method, and its mounting alignment method | |
| JPH0410635A (en) | Flip chip package mounting | |
| JPH0786340A (en) | Connection of semiconductor element | |
| JP2002064177A (en) | Semiconductor element and its manufacturing method |