JPH0471242A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0471242A
JPH0471242A JP18263890A JP18263890A JPH0471242A JP H0471242 A JPH0471242 A JP H0471242A JP 18263890 A JP18263890 A JP 18263890A JP 18263890 A JP18263890 A JP 18263890A JP H0471242 A JPH0471242 A JP H0471242A
Authority
JP
Japan
Prior art keywords
chip
ceramic substrate
forceps
finger
bed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18263890A
Other languages
Japanese (ja)
Inventor
Mamoru Sasaki
Tomoaki Takubo
Chiaki Kikuchi
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18263890A priority Critical patent/JPH0471242A/en
Publication of JPH0471242A publication Critical patent/JPH0471242A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To easily mount a chip, even in the case where the size of a chip is approximate to the size of the bed of a package, by forming at least one or more recessed parts, on the inner peripheral part of a finger having an electrode group connected with the chip.
CONSTITUTION: A ceramic package is constituted by laminating the following; a first ceramic substrate 51, a second ceramic substrate 52, a third ceramic substrate 53, and a hermetic seal metal layer 54. On an exposed part in an aperture part of the second ceramic substrate 2, a step part whose thickness is different from the other parts is formed in a finger part 7. Two of the step part 10 are formed at the nearly central part of the finger part 7. After a chip 2 is mounted on a bed part 1 by using a retaining tool like a forceps, a little position correction for wire bonding and the like is performed. Since the step part 10 is formed, the forceps or the like can be easily moved in a narrow space where the size difference between the bed part 1 and the chip 2 is little. Hence the workability of chip position correction using a forceps or the like is remarkably improved.
COPYRIGHT: (C)1992,JPO&Japio
JP18263890A 1990-07-12 1990-07-12 Semiconductor device Pending JPH0471242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18263890A JPH0471242A (en) 1990-07-12 1990-07-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18263890A JPH0471242A (en) 1990-07-12 1990-07-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0471242A true JPH0471242A (en) 1992-03-05

Family

ID=16121798

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18263890A Pending JPH0471242A (en) 1990-07-12 1990-07-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0471242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH073140U (en) * 1993-06-01 1995-01-17 日本碍子株式会社 Packages for electronic devices
JP2009220556A (en) * 2008-03-18 2009-10-01 Samsung Electro Mech Co Ltd Method of manufacturing insulating sheet, metal laminate using the same, and method of manufacturing printed circuit board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH073140U (en) * 1993-06-01 1995-01-17 日本碍子株式会社 Packages for electronic devices
JP2009220556A (en) * 2008-03-18 2009-10-01 Samsung Electro Mech Co Ltd Method of manufacturing insulating sheet, metal laminate using the same, and method of manufacturing printed circuit board

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