JPH0468561A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPH0468561A
JPH0468561A JP18228990A JP18228990A JPH0468561A JP H0468561 A JPH0468561 A JP H0468561A JP 18228990 A JP18228990 A JP 18228990A JP 18228990 A JP18228990 A JP 18228990A JP H0468561 A JPH0468561 A JP H0468561A
Authority
JP
Japan
Prior art keywords
connected
pad
ground
edge
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18228990A
Inventor
Takatoshi Kuzumoto
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP18228990A priority Critical patent/JPH0468561A/en
Publication of JPH0468561A publication Critical patent/JPH0468561A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To control the voltage variation of an inner power source voltage caused by load variation without increasing chip size by providing a pad which takes out an internally generated voltage generated by an internal power source voltage generating circuit to the outside, providing a capacitor on a lead terminal and connecting the capacitor between the pad and a ground.
CONSTITUTION: An LSI chip 2 is provided with a pad 11 which is connected with a VDD generating circuit 8 as a pad 10 which is connected with a VBB generating circuit 7 as an internal power source voltage generating circuit. The pads 10 and 11 are connected with lead terminals 3 and 4, respectively. Therefore, a chip capacitor C1 is connected with the pad 10 by one edge through the lead terminal 3 and is connected with a ground by the other edge through a ground terminal 13. A chip capacitor C2 is connected with the pad 11 by one edge through the lead terminal 4 and is connected with the ground by the other edge through a ground terminal 14.
COPYRIGHT: (C)1992,JPO&Japio
JP18228990A 1990-07-09 1990-07-09 Semiconductor storage device Pending JPH0468561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18228990A JPH0468561A (en) 1990-07-09 1990-07-09 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18228990A JPH0468561A (en) 1990-07-09 1990-07-09 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPH0468561A true JPH0468561A (en) 1992-03-04

Family

ID=16115682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18228990A Pending JPH0468561A (en) 1990-07-09 1990-07-09 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPH0468561A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7085872B2 (en) * 1997-09-26 2006-08-01 Rambus, Inc. High frequency bus system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7085872B2 (en) * 1997-09-26 2006-08-01 Rambus, Inc. High frequency bus system
US7519757B2 (en) 1997-09-26 2009-04-14 Rambus Inc. Memory system having a clock line and termination
US7523246B2 (en) 1997-09-26 2009-04-21 Rambus Inc. Memory system having memory devices on two sides
US7523244B2 (en) 1997-09-26 2009-04-21 Rambus Inc. Memory module having memory devices on two sides
US7523247B2 (en) 1997-09-26 2009-04-21 Rambus Inc. Memory module having a clock line and termination

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