JPH0464988A - Fifo memory - Google Patents

Abstract

PURPOSE:To improve efficiency for transferring a data between data processors having different data bus width by providing a function to match the respective data bus width of the data processors connecting a FIFO memory to a data input / output port. CONSTITUTION:When data D0-D15 are inputted, a row decoder 4 decodes the address data of high-order (m) bits of a write pointer 2, and one row of a mem ory cell 1 having (2<m>X2<n>X8) bits. A column decoder 10 decodes low-order (n) bits, and one column is selected. On the other hand, those data are inputted to a column decoder 12 as well, and the adjacent column is selected after increas ing the address by +1. A write control signal and the data D0-D15 are written in the selected memory area. In this case, when the address value of the write pointer 2 is increased only by 2 and a write operation is repeated N times, the data of (2XNX8) bits is written in the memory cell 1 and the address data value is turned to be (2XN). Therefore, the difference of the address data value between write pointers 2 and 3 becomes (2XN) and the data can be read from the memory cell 1.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a FIFO memory used as a buffer memory when transferring data between data processing devices, and more specifically, to a FIFO memory that is used as a buffer memory when transferring data between data processing devices. F suitable for application to data transfer means between data processing devices having
This relates to IFO memory.

[Conventional technology]

Conventionally, in a FIFO memory used for data transfer between data processing bags, the data input port and the data output port have the same number of data bits. Therefore, if the data bus widths of the data processing devices that perform data transfer are different, for example, a data processing device with a data bus width of 8 bits (hereinafter referred to as an 8-bit processing device) and a data processing device with a data bus width of 16 bits are used. When transferring data to a 16-bit processing device (hereinafter referred to as a 16-bit processing device), the following two techniques have been adopted.

The first technology is FI with 8 bits of input/output data pits.
One FO memory is used, the input port of this FIFO memory is connected to the 8-bit data output port of the 8-bit processing device, and the output port of the FIFO memory is connected to the upper or Data is transferred by connecting to either lower 8-bit data input port.

The second technique uses two FIFO memories with 8-bit input/output data pits, and connects each input port of these two FIFO memories to the 8-bit data output port of an 8-bit processing device. The output ports of each FIFO memory are connected to the first and lower 8-bit data input ports 1 to 1 of the 16-bit data input ports of the 16-bit processing device for data transfer.

[Problem to be solved by the invention]

However, in the first technique, when data is supplied from the FIFO memory to the 16-bit processing device,
Since only the upper or lower 8 bits of the 16-bit data bus are used, data transfer takes time and high-speed data processing is not possible.

In addition, in the second technique, 1
When transferring 6-bit data to a 16-bit processing device,
It is necessary to distribute the two 8-bit data output from the 8-bit processing device to two FIFO memories and write them.Furthermore, after writing one of the two 8-bit data to one FIFO memory, the other 8
Before writing the bit data to the other FIFO memory,
It is necessary to perform exclusive control to prevent the 16-bit processing device from reading new 16-bit data, and to perform this exclusive control, a logic circuit must be added, which increases the number of parts. In order to transfer data between data processing devices having different data bus widths, there are problems such as the need to use a large circuit board.

The present invention has been made in view of the above, and an object of the present invention is to provide an excellent FIFO memory that can efficiently transfer data between data processing devices having different data bus widths.

[Means to solve the problem]

In order to solve the above problem, the FIFO according to claim 1
The memory is formed of 2n' rows x 2' columns (2n x 2' columns).
” A memory cell having a memory capacity of ×k) bits, a (m+n) bit write pointer that increases the write address to this memory cell by N increments, and a (m+n) bit write pointer that increases the read address from the memory cell by 1.
n) A bit paste pointer, a (N x k) bit data input line, a k bit data output line, and N bits for writing (Nxk) bit data input from the data input line into the memory cell. The data input circuit is characterized by comprising a data input circuit, and a data output circuit that outputs 1-bit data read from the memory cell to the data output line.

Further, the FIFO memory according to claim 2 has 2” rows×2°
a memory cell having a memory capacity of (2" x 2n x k) bits formed from a column; a line pointer of (m + n) bits for incrementing the write address of this memory cell -\ by 1; An (m+n)-bit read pointer that increments the read address from the cell by N, a k-bit data input line, and an (N×k)-bit data output line. a data input circuit for writing one bit of data into the memory cell; and a data input circuit for writing one bit of data into the memory cell (N
The device is characterized in that it includes N data output circuits that output X k ) bits of data to the first data output line.

[Effect]

In the FJFO memory according to claim 1 having the above-mentioned configuration, for a write operation, among the address data held in the write pointer, the data of the m-bits of ``-'' is first decoded, and 2n'X2' ×k)
One of the 2n' rows in the bit memory cells is selected, and then the lower n bits of data are decoded and -
11. N columns are selected from the selected row.

The N pins in the memory cells selected in this way are
The data area contains (N×k
) bit data is written through N input circuits. After the main write operation is performed, the value of the write pointer is increased by N.

On the other hand, for the read operation, among the at1nos data held in the read pointer, the upper m bits of data are first decoded, and the 2" row of the (2" x 2 x k) bit memory cells is decoded. One row is selected from among the rows, and then the lower n bits of data are decoded, and one column is selected from the selected row.

Bit data is read into one of the memory cells selected in this way and is output from the data output line via the output circuit. After the main read operation is performed, the value of the read pointer is increased by 1.

In the FIFO memory according to claim 2, in response to a write operation, among the address data held in the write pointer, first m-bit data of the 1st order is decoded, and data of (2n'×2n×k) bits is decoded. 2 in the memory cell
One row is selected from n' rows, and then the lower n bits of data are decoded to
Column is selected.

Into one bit data area in the memory cell selected in this way, the bit data inputted from the data input line is written via the input circuit. After the main write operation is performed, the value of the write pointer is increased by 1.

On the other hand, among the address data held in the read pointer for the read operation, first the upper m bits of data are decoded, and the data in the 2n' rows of the (2m x 2n x k) bit memory cells One row is selected, then the lower n bits of data are decoded, and N columns are selected from the selected row.

Data is read out to N pins 1 in the memory cell selected in this way, and is outputted from the data output line via the output circuit. After the main read operation is performed, the value of the read pointer is increased by N.

〔Example〕

Hereinafter, one embodiment of the FIFO memory according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the FIFO memory according to the invention as claimed in claim 1, and FIG.
1 is a circuit diagram showing the configuration of an embodiment of a FIFO memory according to the described invention; FIG.

Note that the same components in FIG. 1 and FIG. 2 are given the same reference numerals.

The FIFO memory shown in FIG. 1 includes a 16-bit data input port and an 8-bit data output port. The FIFO memory shown in FIG. 2 has an 8-bit data input port and a 16-bit data output port.

In the following description, in order to facilitate understanding of the present invention, the configuration of the FIFO memory shown in FIG. 1 will be explained first, then the operation of the FIFO memory shown in FIG. The configuration of the FIFO memory shown in FIG. 2 will be explained, and finally, the operation of the FIFO memory shown in the same figure will be explained.

First, the configuration of the FIFO memory shown in FIG. 1 will be explained. In FIG. 1, I is a memory cell, 2n' rows×
Formed from 2n columns (2n' x 2n x 8 (k-8))
It has a memory capacity of bits. 2 is a write pointer as a (m+n)-bit ring counter, which increments the write address to the memory cell I by 2 (N=2). 3 is a read pointer as a ring counter of (m+n) bits, and the above memory cell 1
The read address is increased by one. 1
5 is data D.

~D7 data input line, 16 is data D, ~DI5 data input line, in this example (N x k) - 2 x 8 = 1
It handles 6-bit 1- input data. I7 is a data output line, which carries 8 (k=8) bits of data D0~
It outputs D7. 9, If is 2 (N=2)
16-bit data D is input from the data input lines 15 and 16 through the data input circuits. -Dl, is written into the memory cell 1.

Reference numeral 13 denotes an output circuit which outputs 8-bit data read from the memory cell 1 to the data output line 17. 4 and 5 are row decoders, 6 is an arbitration circuit, 7 is a write control signal, and 8 is a read control signal. Among these, the arbitration circuit 6 has an arbitration function so that the memory cell l is not accessed from the input port and the output port at the same time. We are prepared.

Next, the operation of the FIFO memory shown in FIG. 1 will be explained. The write pointer 2 indicates a writable memory address of the memory cell 1. The read pointer 3 indicates a readable memory address of the memory cell 1. Therefore, from the memory address indicated by write pointer 2 to read pointer 3
If the value of the memory address indicated by is subtracted and the difference is a positive value, it is understood that data that can be transferred from the input port to the output port exists in the FIFO memory.

In the following explanation, it is assumed that the initial values of the memory addresses indicated by write pointer 2 and read pointer 3 are both "0". Here, 16-bit data D is received from a 16-bit processing device (not shown) connected to the input port. -D
A write operation when l6 is input to the input circuit 9 and the input circuit 11 will be described.

In this case, the address data of the upper m bits of the line I pointer 2 is decoded by the row decoder 4, and the row decoder 4 decodes the address data of the (2" x 2" x 8) bits of memory cells
Select one of m rows.

On the other hand, the address data of the lower n bits is column decoded by the column decoder 10.
is decoded to select one column from the selected row. The address data of the lower n bits is also input to the column decoder 12, and after incrementing the address by +1 in this column decoder I2, this column decoder selects the column next to the one column selected by the column decoder IO. do. Together with the write control signal 7 supplied to the arbitration circuit 6, the write control signal 7 is sent to the two 8-bit data storage areas in the memory cell 1 selected by the first row and second column thus selected.
Two pieces of 8-bit data D0 to DI6 input from data input line 15 and data input line 16 are written via input circuit 9 and input circuit 11.

After the main write operation is performed, the address value of write pointer 2 is increased by 2. When the write operation described above is repeated N times, memory cell 1 has (2XN
X8) bit data is written and write pointer 2
The address data value of is (2XN). Here, since the difference obtained by subtracting the address data value of read pointer 3 from the address value of write pointer 2 is (2XN), the 8-bit processing device (not shown) connected to output port I It becomes possible to read and output data.

In this case, the address data of the read pointer 3 at the 3rd m bit is decoded by the row decoder 5.
Select one of the rows.

On the other hand, the address data of the lower n bits of the read pointer 3 is decoded by the column decoder 14.
4 selects one column from the selected row. The 8-bit data D in the memory cell 1 is thus selected by a specific row and column. -D7 is read together with the read control signal 8, and is outputted from the data output line 17 via the output circuit 13 to the -V8Lt processing device.

After the main read operation is performed, the value of the read pointer 3 is increased by 1. ” When two consecutive read operations are repeated (2XN) times, the data from memory cell 1 to (2X
NX8) bit data is read, and the address value of the read pointer 3 becomes (2XN). Here, the difference obtained by subtracting the address value of read pointer 3 from the address value of write pointer 2 is 0, so the 8
This means that the bit processing device has read all the data written in memory cell 1.

In this way, in the FIFO memory shown in FIG. 1, the 16-bit data written in the memory cell 1 can be read out as data of 8 bits 1 to 1.

Next, the structure of the FIFO memory not shown in FIG. 2 will be explained. In Figure 2, 1 is a memory cell, 2 m
It is formed from rows x 2" columns (2n"x2゛x8 (k=
It has a memory capacity of 8)) bits. 32 is (m+
n) A write pointer as a bit ring counter, which increments the write address to the memory cell 1 by 1. 33 is a read pointer as a (m+n)-bit switching counter, which increments the read address of the memory cell I by 2 (N2). 24 is a data input line, 8-bit data D.

-D is input. 25 is data D. -D
7 is a data output line, 26 is a data output line for data D8 to DI5, and in this embodiment, (N x k) = 2 x 8 - 16.
Bit output data is handled.

18 is a data input circuit, which receives 8-bit data D input from the data input line 24; -I]7 is written into the memory cell 1. 20. 22 is an output circuit, and 16-bit data D read from the memory cell 1. -D +5 is output to the data output line 25.26. 4 and 5 are row decoders, 6 is an arbitration circuit, 7 is a write control signal, and 8 is a read control signal. Among these, the arbitration circuit 6 is designed to prevent the memory cell I from being accessed simultaneously from the input port 1- and the output port. It has a mediation function.

Next, the operation of the FIFO memory shown in FIG. 2 will be explained.

The write pointer 32 indicates an address that can be written to the memory cell l, and the read pointer 33 indicates an address that can be read from the memory cell l. In this case, if the address value indicated by the read pointer 33 is subtracted from the address value indicated by the write pointer 32 and the difference is a positive value, there is data in the FIFO memory that can be transferred from the input port to the output port. It shows that

In the following explanation, write pointer 32, read pointer 3
It is assumed that the initial value of the address indicated in both of the three cases is "0".

8-bit data D from an 8-bit processing device (not shown) connected to the input port. -D7 is input, the address value of the 1st m bit of the write pointer 32 is decoded by the row decoder 4, and the row decoder 4 is (2'''×2n×
8) Select one of the 2'' rows of memory cell 1 of bits.

On the other hand, the address value of the lower n bits is decoded by a column decoder I9, and the column decoder I9 selects one column from the selected row.

The 8-bit data area in the memory cell 1 selected by the first row and first column thus receives the 8-bit data D input from the data input line 24 along with the write control signal 7.

~D7 is written via the input circuit 18.

After the main write operation is performed, the address value of the write pointer 32 is incremented by one. When the above write operation is repeated N times, memory cell l has (NX8)
The bit data is written, and the value of the write pointer 32 becomes N. Here, since the difference obtained by subtracting the address value indicated by the read pointer 33 from the address value indicated by the write pointer 32 is N, the 16-bit processing device (not shown) connected to the output boat selects the memory cell 1. It is possible to read data from. Therefore, the address value of the upper m bits of the read pointer 33 is decoded by the row decoder 5, and the row decoder 5
1 in 2n' row of memory cell 1 of 2" x B) bits
Select a row. On the other hand, the address value of the lower n bits is decoded by the column decoder 2I, and by the column decoder 21,
One column is selected from the one row selected above, and further,
The address value of the lower n bits is input to the column decoder 23, incremented by +1, and then decoded. selected.

In this way, the 8-bit data in the memory cell 1 selected by the specific 1st row and 2nd column is transferred to the read control signal 8.
The 16 bits 1 to 1 are output from the data output line 25 and the data output line 26 via the output circuit 20 and the output circuit 22 to the processing device.

After the main read operation is performed, the address value of the read pointer 33 is increased by 2. When the above read operation is repeated (N/2) times, memory cell 1 (
NX8) bit data is read, and the address value of the read pointer 33 becomes N. Here, since the difference obtained by subtracting the address value of the read pointer 33 from the address value of the write pointer 32 is 0, the 1
This means that all data written in memory cell 1 has been read out by the 6-bit processing device.

The present invention is not limited to the embodiments described above, and various changes can be made without departing from the spirit thereof.

For example, in the embodiment of FIG.
All 2n column lines of the memory cell 1 are input to , but the even numbered column lines are supplied to the input circuit 9 and the odd numbered column lines are supplied to the input circuit 11. The lower address of (n-1) bits omitting the least significant bit of the write pointer 2 of m+n) bits is supplied to the column decoder 10 and the column decoder I2, and furthermore, the column decoder 10 and the column decoder I2 Based on the decoded address value, the two 8 bits supplied from data input line 15 and data input line 16
The bit data is transferred to the memory via an 8-bit data line in one of the 2ni columns outputted from the input circuit 9 and an 8-bit data line in one column of the 2'-1 column outputted from the input circuit 11. It is also possible to supply it to cell 1.

In addition, in the embodiment of FIG. 2, the output circuit 20.22
All 2n column lines of the memory cell 1 are input to , but the even-numbered column lines are supplied to the output circuit 20 and the odd-numbered column lines are supplied to the output circuit 22. The (n-1) bit lower order address, omitting the least significant bit of the m+n) bit read pointer 33, is supplied to the column decoder 21 and the column decoder 23, and is further decoded by the column decoder 21 and the column decoder 23. Based on the address value, the output circuit 20 outputs 8-bit data from the data output line 25 via the 8-bit data line in one of the 2''-1 columns of memory cells, and the output circuit 22 outputs 8-bit data from the memory It is also possible to output 8-bit data from the data output line 26 via an 8-pitch data line in one column of cells 1 to 2''-1.

〔Effect of the invention〕

As described above, according to the FIFO memory of the present invention, the data input/output ports of this FIFO memory are matched to the respective data bus widths of the data processing devices to which this FfFO memory is connected, so that different data bus widths can be handled. It is possible to transfer data between data processing devices that have the following functions at high speed and efficiently.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are FIF in one embodiment of the present invention.
FIG. 2 is a circuit block diagram of an O memory. I... Memory cell, 2.32... Write pointer, 3.33... Read pointer, 7... Lyle control signal, 8... Read control signal, 9, 1 13°15° 17゜1.1 20゜16゜25゜8...Input circuit, 22...Output circuit, 24...Data input line, 26...Data output line.

Claims (2)

[Claims] (1) Formed from 2^m rows x 2^n columns (2^m x 2
A memory cell having a memory capacity of ^n×k) bits, a (m+n) bit write pointer that increases the write address to this memory cell by N increments, and a (m+n) bit write pointer that increases the read address from the memory cell by 1. ) bit read pointer, (N x k) bit data input line, k bit data output line, and (N x k) bit data input from the above data input line to the above memory cell. A FIFO memory comprising: a data input circuit; and a data output circuit that outputs k-bit data read from the memory cell to the data output line. (2) Formed from 2^m rows x 2^n columns (2^m x 2
A memory cell having a memory capacity of ^n×k) bits, a (m+n)-bit line pointer that increases the write address to this memory cell by 1, and a (m+n) bit line pointer that increases the read address from the memory cell by N. )-bit read pointer, a k-bit data input line, an (N×k)-bit data output line, and a data input circuit that writes the k-bit data input from the data input line into the memory cell; A FIFO comprising: N data output circuits that output (N×k) bits of data read from the memory cell to the data output line.
memory.