JPH0457283A - Dynamic ram - Google Patents

Abstract

PURPOSE:To prevent trouble of fetching a different address even when skew is generated between column address strobe signals by providing a function to fetch the address signal only into the column address strobe signal falling down first. CONSTITUTION:The address is fetched only for an inverted CAS signal which falls down first among plural inverted CAS signals. Even when skew is generat ed between the inverted CAS signals, an address is fetched only for an inverted CAS signal S1, and the address is not fetched for an inverted CAS signal S2. In a block to input the inverted CAS2, the address B is designated as it is. Thus, even when skew is generated between the inverted CAS signals, the dynamic RAM is operated without any trouble.

Description

[Detailed description of the invention] [Industrial application field] This invention relates to dynamic RAM.

[Conventional technology]

FIG. 3 is a simple configuration diagram of a conventional dynamic RAM (DRAM) having 16 input/output signals.

In the figure, the row AtoV Nustrobe signal, CASI
, CAS2 is a column address strobe signal,
6 is an input/output signal. FIG. 4 is a dynamic chart of signals of the dynamic RAM in FIG. 3, where Add is an address given from the outside, int, RAx int,
The CA takes that address and uses DRAli! This is an internally generated signal. Up to 1 megabit DRAM, input/output signals were mainly 1 or 4, but DRAM with 4 bits or more has not only 1 or 4 input signals, but also many input/output signals such as 8.16. It is thought that products with input/output signals of

Next, the operation will be explained. DRA with the configuration shown in Figure 3
In M, 16 Ilo are divided into blocks of 8 each,
The stones are common to each block, and the hemp signals are different for each block, in this example CASI and CAS2. By doing this, when only 6 guns are brought down, the machines 101 to 8 of the block on the left side of K will operate, and when only CAS2 is brought down, only the machines 109 to 6 of the right block J will operate. . In other words, it also operates as a DRAM having eight 110s. When CASll and CAS2 are brought down at the same time, steps 101 to 16 operate.

The key point here is to bring down CASI and CAS2 at the same time, but when inputting multiple signals to the DRAM from the outside, there will always be cases where one signal falls earlier or later than the other. , a time difference, or skew, occurs. If skew occurs, a problem may occur in which different addresses are taken in by CASI and CAS2, as shown in Figure 4. Capture address B with CAS 1 and capture address C with CAS 2. Since skew also occurs in multiple address signals input from the outside, it is thought that the above-mentioned problem tends to occur even more.

[Problem to be solved by the invention]

Since the conventional dynamic RAM is configured as described above, there is a problem that if there is a skew between the signals, each CAS signal takes in a different address.

This invention was made to solve the above-mentioned problems, and its purpose is to obtain a dynamic RAM that does not cause any problems even if there is a skew between the lines. [Means for solving the problems] The dynamic RAM according to the present invention is configured such that among a plurality of dwarf signals, an address is taken in only for the first signal that falls, and addresses are not taken in for all signals that fall thereafter.

[Operation] The dynamic RAM of the present invention has a function of capturing an address signal only for the column address strobe signal that falls first, so even if a skew occurs between the column address strobe signals, a different address can be captured. No problems will occur.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Although FIG. 1 is a simple configuration diagram of the dynamic RAM of the present invention, the configuration itself is exactly the same as that of the conventional example shown in FIG. 3. Further, FIG. 2 is a timing chart of each signal in the present invention.

Here, W is a row address strobe signal;
A, 1rlt, and CA are signals generated inside the dynamic RAM by taking in the address.

Next, I will explain the operation of one embodiment of the present invention. Conventionally, multiple τ signals each had the function of taking in an address. I am trying to capture buttress only for the dwarf signal. Therefore, even if a skew occurs between the hemp signals shown in FIG.
``The signal does not take in an address, and address B is specified as is in the block to which CAS2 is input.

By doing this, the dynamic RAM can operate without problems even if there is a skew between CAS signals, and can also be changed to have 8 Ilo like the conventional example.
The rel you get.

〔Effect of the invention〕

As described above, according to the present invention, only the first falling column address strobe signal among a plurality of column address strobe signals is provided with the function of taking in the address signal, so a skew occurs between the column address strobe signals. Malfunctions can be prevented even if the

[Brief explanation of drawings]

Fig. 1 is a simple configuration diagram of a dynamic RAM having 16 input/output signals according to an embodiment of the present invention, Fig. 2 is a timing chart of each signal in Fig. 1, and Fig. 3 is a diagram of the conventional 16 input/output signals. FIG. 4 is a timing chart of each signal in FIG. 3. In the figure, RAS is the row address strobe signal, CA
SI, CAS2 is the column atv Nustrobe signal, l1
01 to 16 are input/output signals, Add is an address given from the outside, and int, RA, int, and CA are signals generated inside the DRAM by taking in the addresses. In each figure, the same reference numerals indicate the same or equivalent parts. RAJj-ff131 Straw-7゛1self4tnT,R
A, DRAM-1ffiIa5int, CA' Figure 2 Figure 8 Figure 4

Claims (1)

[Claims] 1. A dynamic RAM having a plurality of input/output signals and a plurality of column address strobe signals (■ signals), which is characterized in that only one (■) signal that falls first takes in a column address.