JPH0454723A - Output circuit - Google Patents

Output circuit

Info

Publication number
JPH0454723A
JPH0454723A JP2165045A JP16504590A JPH0454723A JP H0454723 A JPH0454723 A JP H0454723A JP 2165045 A JP2165045 A JP 2165045A JP 16504590 A JP16504590 A JP 16504590A JP H0454723 A JPH0454723 A JP H0454723A
Authority
JP
Japan
Prior art keywords
turned
fet
pull
output signal
high level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2165045A
Other languages
Japanese (ja)
Other versions
JP2853280B2 (en
Inventor
Nobuyuki Hirakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2165045A priority Critical patent/JP2853280B2/en
Publication of JPH0454723A publication Critical patent/JPH0454723A/en
Application granted granted Critical
Publication of JP2853280B2 publication Critical patent/JP2853280B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the production of spike noise to a power supply by connection a circuit composed of a parallel circuit made up of an element whose resistance is changed with a current and a capacitive element in parallel with a driving control stage.
CONSTITUTION: A current flows selectively to either of driving FETs 21, 22 by giving complementary input signals respectively to each gate of the driving FETs 21, 22. With the FET is turned on and the FET 22 is turned off, a pull-up FET 26 is turned on and a pull-down FET 27 is turned off, and an output signal goes to a high level. Conversely, with the FET 21 is turned off and the FET 22 is turned on, the pull-up FET 26 is turned off and the pull-down FET 27 is turned on, and the output signal goes to a high level. When the output signal is changed from a low level to a high level, the pull-up FET 26 and the pull-down FET 27 are not simultaneously turned on. Conversely when the output signal is changed from a high level to a low level, the FETs 26, 27 are not simultaneously turned on.
COPYRIGHT: (C)1992,JPO&Japio
JP2165045A 1990-06-22 1990-06-22 Output circuit Expired - Fee Related JP2853280B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2165045A JP2853280B2 (en) 1990-06-22 1990-06-22 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2165045A JP2853280B2 (en) 1990-06-22 1990-06-22 Output circuit

Publications (2)

Publication Number Publication Date
JPH0454723A true JPH0454723A (en) 1992-02-21
JP2853280B2 JP2853280B2 (en) 1999-02-03

Family

ID=15804789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2165045A Expired - Fee Related JP2853280B2 (en) 1990-06-22 1990-06-22 Output circuit

Country Status (1)

Country Link
JP (1) JP2853280B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06285612A (en) * 1993-04-02 1994-10-11 Ochi Chuzosho:Kk Method and apparatus for producing spheroidal graphite cast iron
GB2313725A (en) * 1996-05-31 1997-12-03 Ebrahim Bushehri A loading arrangement for a logic gate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06285612A (en) * 1993-04-02 1994-10-11 Ochi Chuzosho:Kk Method and apparatus for producing spheroidal graphite cast iron
GB2313725A (en) * 1996-05-31 1997-12-03 Ebrahim Bushehri A loading arrangement for a logic gate
GB2313725B (en) * 1996-05-31 1998-04-08 Ebrahim Bushehri A circuit arrangement for a logic gate

Also Published As

Publication number Publication date
JP2853280B2 (en) 1999-02-03

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