JPH0443453A - Inter-processor communication system - Google Patents

Abstract

PURPOSE:To improve data transfer capacity by providing a common control means which controls the connection of a matrix switch in accordance with the output of an information transmission detection means. CONSTITUTION:A transmission-side processor adds flag synchronous information, opposite address information, control information and error control information to information to be transferred, and assembles them into a frame so as to transmit it. A transfer destination is identified from opposite address information as to frame information transmitted from the processor and it is transferred to an opposite processor through the matrix switch. In such cases, a synchronous pattern, namely, the frame which does not include data is individually and periodically transmitted to the processor while connection by the matrix switch 4 is cut. Thus, it becomes unnecessary to transmit and receive the frame which does not include data, and the transfer of invalid data becomes unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data transfer from one processor to one or more processors. The present invention is particularly suitable for use in systems such as packet switching equipment that need to transfer large amounts of data information.

The present invention is an inter-processor communication method in which multiplex communication is performed between multiple processors using a predetermined protocol, and by connecting the processors with an IJ switch, a large amount of data can be transmitted without being limited by the transfer distance. It enables data transfer.

[Conventional technology]

As a method for communicating between processors, a bus type method has conventionally been generally used. FIG. 5 shows a block diagram of a conventional bus-type interprocessor communication system, and FIG. 6 shows its operation sequence.

The processors 11-1 to 11-n are each connected to the bus arbiter circuit 12 via a control line, and are connected to each other via an address/data line 13.

Each of the processors 11-1 to 11-n sends a transmission request REQ to the bus arbiter circuit 12 via a control line when they wish to communicate. The bus arbiter circuit 12 sorts out conflicts among transmission requests from a plurality of processors, controls allocation of bus usage rights, and returns a transmission acceptance ACK to the processor 11-1 selected under this control via a control line. The processor 11-1 to which the right to use the bus is assigned,
The partner processor number and transfer information are sent to the address/data line 13.

Each of the processors 11-1 to 11-n also takes in the information when the processor numbers match.

The receiving processor 11-J returns a normal reception status if the received information is normal, and returns an abnormal reception status to the transmitting processor 11-1 if the received information is incorrect. The transmitting processor 11-1 performs reprocessing when the abnormal reception status returns, and releases the communication request RIEQ when the normal reception status returns.

[Problem to be solved by the invention]

However, in the bus-type inter-processor communication system, the transfer capacity of the bus is determined by [clock frequency]X'C bit width], and there is a drawback that increasing the clock frequency limits the transfer distance. In a practical system using TTL, the maximum clock frequency is about IOM)lz, and in this case, the line length of the bus is limited to within several tens of cm. Therefore, when the bit width is set to 64 bits, the limit of transfer capacity is about 640 Mb/s, and due to line length restrictions, boat fishing is limited to communication between processors within the same unit. .

When extending the transfer distance between processors to several tens of meters, the clock frequency is limited to several MHz or less, and the number of connection cables increases, so the bit width must be 16 to 32. Limited to bits.

For this reason, the transfer capacity of the bus is limited to about 100 and several tens of Mb/s, for example, 4 to 5 M)+2×32 bits.

In addition, due to the current driving ability of the bus driver, the number of elements such as processors that can be connected to one bus is limited to about 20, so if you want to increase the number of processors that can be connected,
It was necessary to branch out the basic bus to a branch bus with lower transfer capacity.

In this way, the bus-type interprocessor communication method is useful for interprocessor coupling in areas where the overall throughput is small, such as when transferring information between a small number of processors or when coupling processors with a small amount of information transfer. Although this method was effective, as processor processing power has increased in recent years, a problem has arisen in that the transfer capacity is insufficient.

For example, in the field of data communications, packet switching equipment traditionally has low processor processing power, and can handle several hundred packets per packet.
The processing capacity was only 10 seconds or less, with an average packet length of about 100 bytes. Therefore, even when 64 or so processors are combined, the transfer capacity is 48Mb/s (3Mb/s).
Hz x 16 bits) and had sufficient transfer capacity. However, when attempting to configure a high-speed packet switch by combining dozens of high-performance processors that can process thousands of packets with an average packet length of 200 to 300 bytes in 7 seconds or more, the transfer distance The length of the bus is approximately several tens of meters, and the total throughput is required to be several hundred Mb/s or more, which poses the problem of exceeding the transfer capacity of the bus.

Another problem with bus-type inter-processor communication is that it is not possible to determine whether a call can be received on the receiving side based on the bus access sequence.

That is, even if the inter-processor communication buffer of the processor on the receiving side becomes full, unless an error is detected on the bus, the receiving side accepts the communication unconditionally, resulting in the buffer being overwritten.

Conventionally, methods to solve this problem include methods such as the sending processor checks whether there is an empty buffer in the receiving processor prior to transmission, or the receiving processor sends a response indicating acceptance or rejection back to the transmitting side. There is also. However, in either case, there is a problem in that software processing and bus access are required to determine whether transmission is possible or not before inter-processor communication.

The present invention solves the above problems and makes it possible to transfer a large amount of data without being limited by the transfer distance by connecting a large number of high-performance processors, and in addition, bus access software processing that determines whether or not an incoming call can be received between the processors. The purpose is to provide an inter-processor communication method that does not require .

[Means to solve the problem]

The inter-processor communication method of the present invention is an inter-processor communication method in which a plurality of processors synchronize and perform multiplex communication according to a predetermined protocol. Information transmission detection means is provided between each processor to detect the transmission of information from that processor and to detect the other party, and information transmission detection means that detects the transmission of information from that processor and detects the other party, and information transmission detection means that detects the transmission of information from that processor and detects the other party. The present invention is characterized by comprising means for transmitting synchronization information to the processor when the processor is in use, and common control means for controlling the connections of the matrix switches in accordance with the output of the information transmission detecting means.

Between the matrix switch and each processor, buffer means for temporarily storing information to be transmitted via the matrix switch, and means for detecting an abnormality in information received via the IJ switch are provided. ,
It is preferable that the common control means includes means for retransmitting information from a buffer means provided between the transmission source processor and the matrix switch based on the output of the means for detecting an abnormality.

As a protocol used for communication between processors, it is desirable to use a protocol that performs multiple transfer including delivery confirmation of transfer data, transfer error control, retransmission flow control in case of loss of transfer data, and other functions.

It is desirable to add flag synchronization information, partner address information, control information, and error control information necessary for protocol communication to the information sent and received by the processor, and process the information in a frame format. At this time, it is desirable that the information transmission detection means be configured to detect the transmission frame by detecting the synchronization flag.

[For production]

The sending processor adds flag synchronization information to the information to be transferred,
The destination address information, control information, and error control information are added, assembled into a frame, and sent. Regarding the frame information sent from the processor, the transfer destination is identified from the destination address information, and the frame information is transferred to the destination processor via the matrix switch. The overall throughput of inter-processor communication can be increased by adding more matrix switches, for example, if the line speed is 6. iMb/s
By combining four 32x32 unit matrix switches, interprocessor communication with a total throughput of several Gb/s can be realized on a 64x64 scale.

However, if one matrix switch is used and multiple transfers are performed, there will be a time when the link between opposing processors is disconnected. In particular, when using a protocol that includes acknowledgment of delivery of transferred data, transfer error control, retransmission flow control in the event of lost transferred data, etc., the processor between the sending and receiving devices will detect whether there is no response due to an abnormality on the other side, and if the sent or received data is In the latter case, frames containing no data are generally transmitted and received periodically.

Therefore, in the present invention, while the connection by the matrix switch is broken, a 1 synchronization pattern, that is, a frame containing no data, is periodically sent to the processor. This eliminates the need to send and receive frames that do not contain data, and eliminates the need to transfer invalid data.

Further, since the state between the matrix switch and each processor can be monitored by the common control means, it is possible to determine whether or not a call can be received without requiring processing by the processor. At this time, there is no need to transmit/receive information on whether or not the call can be received via a matrix switch, and retransmission control can be performed via the common control means. However, retransmission control can also be performed between processors using their communication protocols.

The idea of using switches to increase data transfer capacity has been around for a long time. However, in the past, it has been common to control the switch using processor software.

In this case, it is necessary for the processor to manage complicated procedures associated with the information transfer process, such as confirmation of delivery of the transfer information, error checking, and retransmission processing in the event of an error in the transfer information. This results in the complexity of the program and a reduction in the processing power of the processor. Furthermore, a dedicated control interface device is required for data transfer between processors, which increases the amount of hardware and increases costs.

In contrast, the present invention applies control information of LAPD and other standard protocols to the opening/closing control of switches. At this time, the device can be made smaller and more economical by using a general-purpose protocol processing LSI.

〔Example〕

FIG. 1 is a block diagram showing an inter-processor communication system according to an embodiment of the present invention.

The central processing units 1-1 to 1-n include a protocol processing unit 2-1.
~2-n are individually connected and each constitutes one processor. These plurality of processors perform multiplex communication according to a predetermined protocol while being synchronized by protocol processing units 2-1 to 2-n.

Here, the feature of this embodiment is that a plurality of processors are connected via a matrix switch 4, and between this matrix switch 4 and each processor, processor corresponding parts 3-1 to 3-n are provided, respectively. A common control section 5 controls the connection of the IJ switch 4 according to the outputs of the processor corresponding sections 3-1 to 3-n. An information sending detection means that detects the sending of information and detects the destination thereof, and sends synchronization information to the processor when the processor is waiting for reception and the connection with the destination through the matrix switch 4 is broken. a buffer means for temporarily storing information to be transmitted via the matrix switch 4; and a means for detecting an abnormality in information received via the matrix switch;
The present invention includes means for retransmitting information from a buffer means provided between the transmission source processor and the matrix switch 4 based on the output of the means for detecting an abnormality.

The protocol processing units 2-1 to 2-n perform multiple processing of delivery confirmation of transferred data, transfer error control, retransmission when transferred data is lost, and other procedural controls, and at the time of transmission, the central processing units 1-1 to l, respectively. Flag synchronization information, partner address information, control information, and error control information are added to the transfer information from -n, assembled into a frame, and sent to the processor corresponding units 3-1 to 3-n, respectively. At this time, the protocol processing units 2-1 to 2-0 simultaneously transmit and receive information to and from one or more processors by performing multiple processing.

The pro-sensor support units 3-1 to 3-n synchronize the flags of transmitted and received frames, and when receiving a transmitted frame from the corresponding protocol processing unit, detect the start and end of packet transmission, and transmit the other party address information of the frame. To analyze. Further, while the processor is waiting for reception and no reception data arrives from the other processor, it sends a flag synchronization pattern to the corresponding protocol processing units 2-1 to 2-n.

The common control unit 5 performs routing control based on the destination address information detected by the processor corresponding units 3-1 to 3-n, and sets the connection of the matrix switch 4.
A frame transmission instruction signal is sent back to the processor corresponding unit that allows transmission.

FIG. 2 shows the frame structure.

The protocol processing units 2-1 to 2-n add flag synchronization information F1 partner address information A1 control information C and error control information FC3 to the information to be transferred supplied from the corresponding central processing units 1-1 to l-n. A frame is generated and sent. It also receives a frame in this format and sends the information (2) to the corresponding central processing units 1-1 to l-n.

FIG. 3 shows the operation sequence.

The processor attempting to communicate (the originating processor)
A frame containing flag synchronization information F1, destination address information A1, control information C1, information I to be transferred, and error control information FC3 is sent to a processor support unit (originating side support unit) provided corresponding to the processor. The sending side response department is
By detecting flag synchronization, frame transmission is confirmed, the other party's address information is read, and the other party's address is sent to the common control unit. At this time, the frame is temporarily stored.

The common control unit sorts out conflicts among transmission requests from a plurality of processors and sequentially performs connection processing.

That is, the common control unit stores switch information in the form of a table, and searches this table when a transmission request from the processor arrives. As a result of this search, if the other processor is not in communication, the table is rewritten, the matrix switch is set, and a frame sending instruction signal is returned to the corresponding processor corresponding section. When the processor corresponding section receives the frame sending instruction signal, it sends out the stored frame.

The receiving side response unit outputs the normal reception status if the reception information is normal, and the abnormal reception status if the reception information is incorrect or the frame cannot be received because the reception buffer is full, via the common control unit. Return it to the sender's corresponding department. The originating side response unit releases the connection request REQ when the normal reception status returns, and performs retransmission processing when the abnormal reception status returns. Upon receiving the release of the connection request REQ from the originating side corresponding unit, the common control unit releases the switch and changes the switch information table.

FIG. 4 is a block diagram showing in detail an example of the processor corresponding section and the common control section.

The processor support unit 3 includes flag synchronization units 31, 32, and 33.
．． 38, a partner address information reading section 34, a memory writing section 35, a buffer memory 36, a memory reading section 37, and a control section 39.

The flag synchronization unit 33 detects the flag synchronization information F included in the frame from the protocol processing unit 2, confirms the transmission of the frame, notifies the control unit 39 of this, and transmits the frame to the other party address information reading unit 34. supply to. The other party address information reading unit 34 reads the other party address information A in the frame and sends it to the control unit 39. The memory writing unit 35 writes the frame into the buffer memory 36. The memory reading unit 37 reads the frame from the buffer memory 36 and sends it to the flag synchronization unit 38. The flag synchronization unit 38 performs flag synchronization on the frame and sends it to the madrisk switch 4.

The control unit 39 sends a transmission request RεQ to the common control unit 5 in accordance with the notification from the flag synchronization unit 33, and
The common control unit 5 is notified of the other party address information received from the other party address information reading unit 34, and the memory writing unit 35
instructs temporary storage of frames. Furthermore, upon receiving the frame sending instruction signal from the common control section 5, the control section 39 instructs the memory reading section 37 to read the frame.

The flag synchronization unit 31 detects the arrival of a frame from the matrix switch 4 using a synchronization flag, and transfers this to the flag synchronization unit 32. Further, the flag synchronization unit 31 temporarily stores the received frame and determines whether it is correct or incorrect.
This is notified to the control unit 39.

When a frame arrives from the flag synchronization unit 31 , the flag synchronization unit 32 adds flag synchronization information to the frame and transfers it to the processor processing unit 2 . Further, when the processor is waiting for reception and no frame arrives from the other processor, it sends a flag synchronization pattern to the protocol processing section 2.

The common control unit 5 includes a contention control unit 51, a partner address register 52, a frame sending instruction unit 53, and a switch opening/closing unit 54.
, a microprocessor 56 and a common memory 57, which are connected to a bus 55.

The conflict control unit 51 performs conflict management for connection requests REQ from − or more processor-compatible units. The destination address register 52 stores destination address information from the processor corresponding section. The frame sending instruction unit 53 sends a sending request RE.
A frame transmission instruction signal is sent to the processor corresponding unit that issued Q and is permitted to transmit. The switch opening/closing section 54 performs connection setting and release control of the matrix switch 4. The common memory 57 stores the connection state of the matrix switch 4. The microprocessor 56 is
Control these operations.

In the above description, an example has been described in which the protocol processing section is provided within the processor, but the present invention can be implemented in the same manner even if the protocol processing section is provided outside the processor.

Regarding the procedure processing by the protocol processing unit, the HDLC procedure in combiator communication, token bus, token ring, and other methods in local area network (LAN), and integrated service digital network (IS) are used.
Broad OS I for Layer 2 procedural control in
(Open System rnter-conne
Any processing may be used, such as one based on the data link layer concept of ction).

[Effects of the Invention] As described above, the inter-processor communication system of the present invention can connect a large number of high-performance processors and transfer a large amount of data without being limited by the transfer distance.

In addition, delivery confirmation, error checking for forwarded information, and retransmission processing in the case of an error in forwarding information can be executed outside the processor.
There is no need to determine whether or not a call can be received between processors before starting communication, and the processors are not made aware of complicated procedures associated with information transfer processing. Therefore, inter-processor communication can be performed without causing a decrease in the processing capacity of the processors.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an inter-processor communication system according to an embodiment of the present invention. FIG. 2 is a diagram showing the frame structure. FIG. 3 is a diagram showing an operation sequence. FIG. 4 is a block diagram showing in detail an example of a processor corresponding section and a common control section. FIG. 5 is a block diagram of a conventional bus-type inter-processor communication system. FIG. 6 is a diagram showing an operation sequence of a conventional example. 1.1-1~1-n...Central processing unit, 2.2-1~
2-n...Protocol processing unit, 2.3-1 to 3-n...
・Processor compatible part, 4...Matrix switch, 5
... Common side [B, 11-1 to 1l-n... Processor, 12... Bus arbiter circuit, 13... Address/data line, 31.32.33.38... Flag synchronization section, 34... Partner address information reading unit, 35... Memory writing unit, 36... Buffer memory, 37...
Memory reading unit, 39... Control unit, 51... Conflict control unit, 52... Partner address register, 53... Frame sending instruction unit, 54... Switch opening/closing unit, 55...
...Bus, 56...Microprocessor, 57...
common memory. Patent applicant: Nippon Telegraph and Telephone Corporation -1. Representative Patent Attorney Nao Takashi Ide Frame Structure Figure 2

Claims (1)

[Claims] 1. In an inter-processor communication method in which a plurality of processors communicate according to a predetermined protocol while synchronizing with each other, the plurality of processors are connected via a matrix switch, and the matrix switch and There is an information sending detection means between each processor that detects the sending of information from that processor and detects the other party, and the processor is waiting for reception and is disconnected from the other party by the matrix switch. an inter-processor communication system, comprising: means for occasionally sending synchronization information to the processor; and common control means for controlling connection of the matrix switch according to an output of the information sending detection means. 2. Buffer means for temporarily storing information to be transmitted via the matrix switch and means for detecting an abnormality in information received via the matrix switch are provided between the matrix switch and each processor, respectively. 2. The inter-processor communication system according to claim 1, wherein the common control means includes means for retransmitting information from a buffer means provided between a transmission source processor and the matrix switch based on the output of the abnormality detecting means. .