JPH0440538A - Memory access system - Google Patents

Abstract

PURPOSE:To equalize the heating value in each line of a printed board on which a memory element is mounted by controlling a part of an address but for instructing the memory element and changing a mounting position instructed by the address bit, in accordance with a mounting state of the memory element. CONSTITUTION:Signals (INS-a,b,c,d) (1) for showing mounting states (1/4 mount ing, 1/2 mounting, full mounting) of a memory element 1 are provided, and by this signal (2), a part (SELa - d -0,1 bit) (2) of an address bit for specifying a mounting position of the memory element 1 is controlled. Also, a mounting position shown by a part (SELa - d -0,1 bit) (2) of the address bit to the mem ory element is changed in accordance with the mounting states (1/4 mounting, 1/2 mounting, full mounting) of the memory element 1 shown by the mounting state discriminating signal (INS-a,b,c,d) (1). In such a way, the access state to the memory element 1 is dispersed with regard to the mounting position, and the heating value is also equalized.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology and Problems to be Solved by the Invention Means for Solving the Problems Actions Examples Effects of the Invention [Summary] Storage devices, e.g. The mounting position of a memory element mounted on a printed circuit board, for example, a package, is determined by a part of the address bits (SEL-a-
Regarding the method of accessing by changing the mounting position shown in cl), it is possible to mount multiple memory elements (packages) in order to equalize the amount of heat generated on the entire printed board, for example, with respect to the cooling path. In the constructed storage device (printed board), a signal aNs-a+ indicating the mounting state of the memory element
b+c+d)■ is provided, and the mounting state identification signal (INS
-a, bl C, d) ■ Part of the address bits (SELa =
d-0,1 bits), and part of the address bits (SELa ”-d-0,1 bits) for the memory element.
The mounting position indicated by the bit) is determined by the mounting state identification signal (I
NS-a+ bl C1d) Change according to the mounting state of the memory element indicated by ■ (1/2 mounting, 1/4 mounting, ~),
For example, the configuration is such that memory elements adjacent in the address direction are not accessed at the same time.

[Industrial application field]

The present invention provides a method for determining the mounting position of a memory element, for example, a package, of a storage device, for example, mounted on a printed board.
The present invention relates to a method for accessing a memory element by changing a mounting position indicated by a part of address bits for accessing the memory element.

With recent high-density packaging of storage devices, in storage devices in which memory elements, such as packages, are mounted on a printed board, the amount of heat generated on the printed board continues to increase.

However, since there is a limit to the amount of cooling air supplied from a mechanism that cools the printed circuit board, such as an air cooling fan, when viewed from the passage through which the cooling air flows, It is required that the amount of heat generated is as uniform as possible.

[Prior art and problems to be solved by the invention] FIG. 3 is a diagram illustrating a conventional memory access method, and (a)
shows a configuration example, and (bl) to (b3) show the relationship between the mounting state and the access address.

When a storage device (for example, a printed board) is constructed by arranging a plurality of memory elements (packages, hereinafter abbreviated) in the word direction, in the conventional method, for example, the structure is as shown in Fig. (a). Ru.

That is, for example, the upper 4 bits (SELI~4-0.I BIT, SEI, ad-
0, I BIT (hereinafter referred to as BIT)
is assigned to the mounting position of the memory element 1 on the printed circuit board 2, and the lower bit is assigned to, for example, a cell within the memory element 1.

Therefore, in the conventional method, the mounting state on the printed board 2 is 1 as shown in FIGS. (bl) to (b3).
When changing from /4 implementation → 1/2 implementation → full implementation, the implementation is performed sequentially in the address direction, that is, the word direction, and due to the locality of the address distribution of the program, for example, in the illustrated implementation state, the above 5ELa to When d-0,1 bits are constant, horizontally adjacent memory elements (1-0, 2-0,
~) may be accessed.

Here, if the air flow from the cooling mechanism (not shown) to the printed board 2 is on the left side, for example, in the case of full mounting, the amount of heat generated in a specific horizontal line will increase, and the There is a problem in that the temperature of the memory element in the line increases, which may reduce the reliability of the memory device.

This problem is caused by part of the address bits (SELL to 4-0.1 bits) that indicate the mounting position of the memory element 1.

5ELa to d-0, 1 bit) is not related in principle to the bit position.

As a technique for equalizing the access frequency to the memory element 1 and equalizing the amount of heat generated, in addition to the method described above, there is, for example, the method described in Japanese Patent Application Laid-open No. 53-52322, "Storage device j, etc., but the central processing Instead of the lower bits of the address bits sent from the device (CPU), for example, the higher bits select the memory element 1, and the higher the bits, the more the above 5ELa=d-
If the bits corresponding to the 0 and 1 bits are fixed, the memory elements 1 on the same horizontal line are likely to be accessed successively, and the above problem is not solved.

In view of the above-mentioned conventional drawbacks, the present invention provides a storage device that includes, for example,
The purpose of the present invention is to provide a memory access method that can equalize the amount of heat generated by the entire printed board, for example, with respect to a cooling path when accessing a memory element mounted on a printed board. be.

[Means to solve the problem]

FIG. 1 is a diagram explaining the present invention in detail, (a) to (
c) shows the relationship between the address bit and the mounting position of the memory element in I/4 mounting, 1/2 mounting, and full mounting, respectively.

The above problems are solved by a memory access method configured as follows.

In a storage device configured by mounting a plurality of memory elements 1, signals (INS-a, b, C1d) that indicate the mounting state of the memory elements 1 (1/4 mounted, 1/2 mounted, fully mounted) are provided. and the mounting state identification signal (INS-a, blcld
) Part of the address bits that specifies the mounting position of the memory element 1 (SELa = d-0, 1 bit)
(2) controls the mounting position indicated by part (SELa = d-0, 1 bit) of the address bits (SELa = d-0, 1 bit) for the memory element by the mounting state identification signal (INS-a+b+c+
d) The mounting state of the memory element 1 indicated by ■ (1/4 mounting,
1/2 implementation, full implementation), for example, Fig. 1(a)
The structure is configured to be changed as shown in ~(c).

[Effect]

That is, according to the present invention, when the memory element 1 is mounted on the printed board 2, the memory elements 1-a, 2-a, 3a, 4
-a, or memory element 1-b, 2-b, 3-b
, 4-b.

Mounting state identification signals lN5-a, lN5-b, and ~2 are provided that are turned on when ~, etc. are mounted.

A starting signal (Go) and an operation code (
OP-CODE) (IJ-TO/RAI) ), 5E
LL ~ 4-0.1 bit signal, 5ELa -d-0
+1 If there is an access with the hit signal ■, the memory elements (1-a, 2-al 3a, 4-a
) 1 is mounted, only the lN5a is turned on, and the addresses (1-0 to 4-0) shown in FIG. 1(a) are assigned to each memory element 1.
) is assigned.

At this time, the number of memory elements 1 mounted on the printed board 2 is small, so the amount of heat generated does not pose much of a problem.

However, in 1/2 implementation, memory elements (1-a, 2-a,
3-a, 4a, 1-b, 2-b, 3-b, 4-b)
is mounted, the mounting state identification signals lN5-a and rNs-b of the present invention are turned on, so that among the address bits indicating the memory element 1, the above 5ELa=d-0 , 1-bit signal ■,
Addresses (10, 2-1, 3-0, 4-1, 1-) as shown in FIG. 1(b) are assigned to each memory element 1.
1, 2-0, 3-1, 4-0) are assigned.

That is, in the case of the present invention, the 5ELa-d-0, 1 bit signal (2) is, for example, "00", and the memory element 1 designated by the address bit is the memory element (1-0, 2-0, 3).
-0゜4-0) Even if 1 is specified, the printed board 2
In the above example, as shown in FIG. 3(b), the memory elements I function to be allocated as memory elements I of different lines.

As a result, the access state to the memory element 1 is distributed with respect to the mounting position, and the amount of heat generated is also made uniform.

Similarly, when fully implemented, each memory element (1
-0 to 4-3) 1 are assigned addresses as shown in the diagram (c), the access state to the memory element 1 is distributed with respect to the mounting position, and the amount of heat generated is also made uniform.

As described above, in the present invention, the mounting state identification signal l indicating the mounting state of the memory element is determined according to the mounting state of the memory element.
N5-a, lN5-b, ~■ are part of the address bits that specify the memory element (SEL-a=61.2)
(2) The mounting position indicated by the address bit can be changed by controlling , the maximum amount of heat generated in each line in the storage device (printed board) can be suppressed, and the reliability of the storage device can be improved.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram for explaining the present invention in detail, and FIG.
The figure shows an embodiment of the present invention, in which the mounting state identification signals ~9 lN5-a, b, c, when the memory element 1 is mounted on the printed board 2 on which the memory element 1 is mounted are d■ is provided, and a part of the address bits (S
A means for controlling the EL-a-d-0, 1 bits) and changing the mounting position on the printed board 2 of the memory element 1 indicated by the address bit is necessary to carry out the present invention. It is a means. Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, the memory access method of the present invention will be explained using the embodiment shown in FIG. 2 while referring to FIG.

In this embodiment, among the addresses for the memory element 1 mounted on the printed board 2, an address bit (S
ELa to d-0, 1 bits) (1) will be explained using a method in which the above-mentioned mounting state identification signals IN5-a, b, C, d (1) are controlled.

First, in this embodiment, a central processing unit (not shown) is used.
Of the address bits sent from the CPU), the two bits shown in the figure, bits 5ELL to 4-0.1, indicate the mounting position in the horizontal direction, and the two pins of 5ELa-d-01■ indicate the mounting position in the vertical direction. The mounting position shall be indicated.

Furthermore, as described above, in the present invention, the memory elements (1-a, . . .
4-a, ~, I-d, ~4-d) A mounting state identification signal rNs-a+b+c+d■ is provided when 1 is mounted.

Therefore, in the I/4 implementation shown in Figure 1(a),
The mounting state identification signal lN5-a becomes 'ON°, and the first
In the case of 1/2 mounting shown in Figure 1(b), the mounting state identification signals lN5-a, b■ are turned on'', and Figure 1(c)
) All the implementations shown in
b + C + d■ turns on.

If the above 5ELL~4-0.1 bin 1~ (in this expression, 0 bit is the upper bit of the address and 1 bit is the lower pinpoint) is "00", then (1a) as shown in the figure
The memory element 1 is mounted at the position of ~(1-d), and the memory element 1 is
'', the memory element 1 is mounted at each of the illustrated positions (2-a) to (2-d) (the same applies hereinafter).

Accordingly, the above 5ELa-d-0+ 1 hit ■ is “o
o" Te is located at the positions (1-a) to (4-a) shown in the figure.
01'', the memory elements 1 are mounted in the illustrated positions (1-b) to (4-b) (the same applies hereinafter), respectively.

In this embodiment, this 5ELa''d-0, 1 bit signal ■ is used as the mounting state identification signal lN5-a, b, c,
The signal controlled by d) is decoded by a decoder 30 of the memory control signal generating circuit 3, so that the corresponding memory element 1 on the printed board 2 is selected.

As mentioned above, the activation signal (G
O), Opcode (OP-CODE), 5ELI
~ 4-0.1 bit signal, 5ELa ``d-0, 1 bit signal ■ When access is made, as shown in the figure, SEE, 1 ~ 40.1 bit signal is sent to the decoder (DECODER). ) 30, the horizontal mounting position on the printed circuit board 2 is the same as in the conventional method shown in FIG. 3(a).

However, in the present invention, in the memory access control circuit 4, the above-mentioned 5ELa=d-0, 1 bit signal ■ is the above-mentioned mounting state identification signal lN5-at b, C+ of the present invention.
Controlled by d■.

Here, rrNv J 41a~ is determined when the output of the AND circuit (8ND) 42a~ to which the mounting state identification signals lN5-a, b, C1d■ are inputted is 1°, the rlNV J 41a~ 5ELa entered in
= d-0, 1 bit signal ■ is inverted and the above decoder (
DECODER) 30.

Therefore, as shown in FIG. 1(a), in the case of 1/4 mounting, only the mounting state identification signal lN5-a is "on", so which of the logical product circuits l5(AND) 42a~ is is not activated, so the 5ELa"d-0, 1 bit signal (2) is sent to the decoder (DECODEI+) 30 without being inverted by rINV J 41a~, as shown in FIG. 1(a). For the memory element 1 mounted as shown in the figure, the addresses (1-0) to
(4-0) is assigned.

Next, as shown in FIG. 1(b), in the case of I/2 mounting, since the mounting state identification signals lN5-a and b are 'on', an AND circuit (AND) 42a is installed. 5ELa-d-1
The pit signal ■ is inverted and the decoder
)30.

As a result, the mounting position (1-a) of the printed board 2, (
For the memory element 1 of 1-b), the 5ELa=d-
Since the 0 and 1 bit signals ■ are not subject to any control, the addresses shown in the figure (1-0), (1-1
) (corresponding to addresses '00' and '01°, respectively) are assigned.

Mounting position of the printed board 2 (2-a), (2-b)
As mentioned above, since the 5ELa=d-1 bit signal ■ is inverted, the corresponding mounting position (2-a)
, (2b), address °01', '0
0' will be assigned, and the mounting position (2-a)
, (2-b) are assigned addresses (21) and (2-0) (corresponding to addresses '01' and '00', respectively) as shown in FIG. 1(b).

Similarly, the AND circuits (AND) 42b and 42d are not activated and the AND circuit (AND) 42c is activated, so that the input 5EL-a to d- Since the 5EL-a-d-1 bit signal ■ inputted as 0 p 0 bit signal is inverted, the mounting position (3-a) of the printed board 2,
For (3b), the address of the side (3-0),
(3-1) is assigned, mounting position (4-a),
For (4-b), the inverted address (4-1)
, (4-0) is allocated.

In the same way, as shown in FIG. 1(c), when fully mounted, the mounting state identification signal lN5-ab, c
, d■ is 'on°, so the logical product circuit (AND)
As a result of energizing 42a, 42b, lN5-d, and 42d, the mounting positions of the printed board 2 (2-a) to (2-d)
, 5ELa=d-1 bit signal ■ is inverted, and mounting position N of printed board 2 (3-a) ~ (3-d)
, the 5ELa-d-0 bit signal ■ is inverted, and the 5ELa-d-0.1 bit signal ■ is inverted for the mounting positions (4-a) to (4-d) of the printed board 2. The signal is inverted and input to each decoder (DECODER) 30.

As a result, each mounting position (1-
a) ~(1-d), (2-a) ~(2-d)
~(4-a) ~(4d) will be assigned the addresses shown in FIG. 1(c).

Therefore, even if consecutive addresses are input from a central processing unit (CPU) (not shown), for example, when viewed from the horizontal memory element 1,
Adjacent memory elements 1 will no longer be accessed, and for example, the amount of heat generated will be equalized for lateral cooling, and the temperature of memory elements 1 in a particular line will not become particularly high. The credibility of the device can be improved.

In the above embodiment, address bit S E L
a~d-0. The 1-bit signal ■ is used as the mounting state identification signal l
Although the example has been explained in which control is performed using N5a+b+c+d■, the address bits 5ELL to 4-0.1 bit signals may be configured to be controlled using mounting state identification signals lN5-a, b, c, d■. Needless to say, this is not the case.

In this way, the present invention provides mounting state identification signals lN5-a, b, C1 d■ when the memory element 1 is mounted on the printed board 2 on which the memory element 1 is mounted, and lN5-a, b, c, d■, part of the address bits for memory element 1 (for example, 5E
(L-a = d-0.1 bit)
The feature is that the mounting position above has been changed.

〔Effect of the invention〕

As described above in detail, the memory access method of the present invention allows the mounting position of a memory element mounted on a printed circuit board, for example, a package, to be determined by an address bit for accessing the memory element. In order to change and access the mounting position indicated by a part, signals indicating the mounting state of the memory element (INS-a, b, C1
d) Provide the mounting state identification signal (INS-a, INS-a,
b, c, d) Part of the address bits that specifies the mounting position of the above memory element (SELa = d-0
．． 1 bit) ■, and part of the above address bits (SELa to dO.1 bit) ■ for the memory element.
The mounting position indicated by the mounting state identification signal (INS-a,
b. c, d) Change according to the mounting state of the memory element indicated by ■ (1/2 implementation, I/4 implementation, ~), for example, so that adjacent memory elements in the address direction are not accessed at the same time. As a result, the heat generation amount corresponding to the cooling path on the storage device, specifically the printed board, is equalized, suppressing the temperature rise of the memory element mounted on the printed board, and reducing the temperature of the memory device. This has the effect of improving reliability of the storage device.

42a-d are logical product circuits (AND).

■ is the mounting state identification signal (INS-a, bl C, d)
+■ is part of the address bits (SELa~d-0,1
) Same signal.

1-a to 4-d are mounting positions.

1-0 to 4-3 indicate assigned addresses, respectively.

Or

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the present invention in detail. FIG. 2 shows an embodiment of the present invention, and FIG. 3 is a diagram illustrating a conventional memory access method. In the drawings, 1 is a memory element, and 2 is a printed board. 3 is a memory control signal generating circuit 30 which is a decoder (DEC:0DER). 4 is a memory access control circuit. 41a"d is an inverting circuit rlNV.

Claims (1)

[Claims] In a storage device configured by mounting a plurality of memory elements (1), a signal (INS-a, INS-a,
b, c, d) ([1]), and the mounting state identification signal (INS-a, b, c, d) ([1]
]) controls a part of the address bits (SELa to d-0, 1 bits) ([2]) that specify the mounting position of the memory element (1), and controls part of the address bits for the memory element. (S.E.
The mounting position indicated by the La to d-0, 1 bits) ([2]) is determined by the mounting state identification signal (INS-a, b, c, d) (
[1]) A memory access method characterized in that the memory element (1) is accessed by changing the mounting state of the memory element (1) shown in [1]).