JPH04369250A - Mounting structure of semiconductor device - Google Patents

Mounting structure of semiconductor device

Info

Publication number
JPH04369250A
JPH04369250A JP3171693A JP17169391A JPH04369250A JP H04369250 A JPH04369250 A JP H04369250A JP 3171693 A JP3171693 A JP 3171693A JP 17169391 A JP17169391 A JP 17169391A JP H04369250 A JPH04369250 A JP H04369250A
Authority
JP
Japan
Prior art keywords
semiconductor element
conductive member
wiring
substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3171693A
Other languages
Japanese (ja)
Inventor
Toshihiro Kimura
俊広 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP3171693A priority Critical patent/JPH04369250A/en
Publication of JPH04369250A publication Critical patent/JPH04369250A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48475Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48491Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being an additional member attached to the bonding area through an adhesive or solder, e.g. buffer pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

PURPOSE:To improve heat radiation and lower the cost of mounting for a semiconductor device, by reducing an occupied mounting area of the semiconductor device. CONSTITUTION:In a mounting structure, a semiconductor device 13 fixed on a board 11 is sealed after electrodes 13a and 13b of the semiconductor device 13 are electrically connected to wiring leads 12a to 12c located on the board 11. Moreover, a conducting member 25, which functions as a sealing dam ring and as a wire bonding pad and is connected electrically to one wiring lead 12c on the substrate 11, is bonded so as to enclose the peripheral part of the semiconductor device 13.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、基板上に固着した半導
体素子と基板上の配線間をボンディングワイヤにて接続
し、全体を樹脂材等により封止するチップオンボードタ
イプの半導体素子の実装構造に関する。
[Industrial Application Field] The present invention relates to the mounting of a chip-on-board type semiconductor device, in which a semiconductor device fixed on a substrate and wiring on the substrate are connected using bonding wires, and the whole is sealed with a resin material or the like. Regarding structure.

【0002】0002

【従来の技術】従来、この種の半導体素子の実装構造と
しては、図11および図12に示すものが知られている
。同図において、11はセラミック,ガラスエポキシ,
紙・フェノール等からなる基板であり、基板11の上面
には部品実装のための配線12a〜12cが形成されて
いる。また、半導体素子13の配線との接合部分および
ワイヤボンディング部分などを除く基板11上の非半田
付け領域は、ソルダーレジストと称するコーティング層
15により保護されている。半導体素子13は配線12
aに連なる素子取付部12a1に半田14によって接合
される。さらに半導体素子13の上面に設けた電極13
a,13bは、配線12b,12cに半田16により接
合したボンディングパッド17a,17bにワイヤ18
a,18bによって接合される。基板11上には、半導
体素子13およびボンディングパッド17a,17bを
取り囲むように配置した合成樹脂性のダムリング19が
接着剤により固着されている。ダムリング19の内側に
は、エポキシ樹脂,フェノール樹脂,ウレタン樹脂,シ
リコン樹脂などの比較的粘度の高い樹脂材20が充填さ
れ、これにより半導体素子13を封止する。
2. Description of the Related Art Hitherto, as a mounting structure of this type of semiconductor element, one shown in FIGS. 11 and 12 is known. In the same figure, 11 is ceramic, glass epoxy,
The board 11 is made of paper, phenol, etc., and wires 12a to 12c for mounting components are formed on the top surface of the board 11. Further, the non-soldered areas on the substrate 11, excluding the joint portions of the semiconductor element 13 with the wiring and the wire bonding portions, are protected by a coating layer 15 called a solder resist. The semiconductor element 13 is the wiring 12
It is joined by solder 14 to the element attachment portion 12a1 continuous to a. Further, an electrode 13 provided on the upper surface of the semiconductor element 13
a, 13b are wires 18 connected to bonding pads 17a, 17b which are connected to wirings 12b, 12c by solder 16.
a, 18b. A synthetic resin dam ring 19 is fixed on the substrate 11 with an adhesive, and is arranged so as to surround the semiconductor element 13 and bonding pads 17a and 17b. The inside of the dam ring 19 is filled with a relatively high viscosity resin material 20 such as epoxy resin, phenol resin, urethane resin, silicone resin, etc., thereby sealing the semiconductor element 13.

【0003】0003

【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体素子の実装構造では、半導体素子と配
線間の電気的導通をとるボンディングパッドを半導体素
子の周囲に配設する構造になっているため、以下に述べ
る問題点がある。 (a)ダムリングを含めた半導体素子全体の実装面積が
大きくなり、基板の実装密度を上げることが困難である
。 (b)ダムリングの放熱性が悪く、素子温度が上昇し、
加熱し易い。 (c)温度上昇に伴い封止用樹脂材から半導体素子に特
性劣化などのダメージを与えるおそれがある。 (d)ボンディングパッド等の部品数が多くなり、実装
工数も増加する。 (e)ワイヤの方向が制限される。
[Problems to be Solved by the Invention] However, in such a conventional semiconductor element mounting structure, bonding pads are arranged around the semiconductor element to provide electrical continuity between the semiconductor element and wiring. Therefore, there are the following problems. (a) The mounting area of the entire semiconductor element including the dam ring becomes large, making it difficult to increase the mounting density of the board. (b) The heat dissipation of the dam ring is poor and the element temperature rises.
Easy to heat. (c) As the temperature rises, there is a risk that the sealing resin material may cause damage such as deterioration of characteristics to the semiconductor element. (d) The number of components such as bonding pads increases, and the number of mounting steps also increases. (e) The direction of the wire is restricted.

【0004】本発明の目的は、半導体素子の占有実装面
積を小さくできるとともに、放熱性を向上し、実装の低
コスト化を可能にした半導体素子の実装構造を提供する
ことにある。
An object of the present invention is to provide a mounting structure for a semiconductor element that can reduce the mounting area occupied by the semiconductor element, improve heat dissipation, and reduce the cost of mounting.

【0005】[0005]

【課題を解決するための手段】実施例である図1および
図9に対応づけて本発明の半導体素子の実装構造を説明
すると、本発明は、基板11上に半導体素子13を固着
し、この半導体素子13の電極13a,13bと基板1
1上の配線12a〜12c間を電気的に接続した後封止
する半導体素子の実装構造に適用される。そして、上記
目的は、基板11上の一部の配線12aと電気的に接続
され、かつ封止用ダムリングおよびワイヤボンディング
パッド機能を兼ねた導電部材25を半導体素子11の外
周囲を取り囲むようにして基板上に固着することにより
、達成できる。また、本発明は、導電部材30を半導体
素子11の電極に対応した数に電気的に分離することに
より、上記目的を達成できる。
[Means for Solving the Problems] The mounting structure of a semiconductor element of the present invention will be explained in conjunction with FIGS. 1 and 9, which are embodiments. Electrodes 13a, 13b of semiconductor element 13 and substrate 1
The present invention is applied to a mounting structure of a semiconductor element in which the wirings 12a to 12c on the wiring board 1 are electrically connected and then sealed. The above purpose is to surround the outer periphery of the semiconductor element 11 with a conductive member 25 that is electrically connected to a part of the wiring 12a on the substrate 11 and also serves as a sealing dam ring and a wire bonding pad. This can be achieved by fixing it onto the substrate. Further, the present invention can achieve the above object by electrically separating the conductive members 30 into a number corresponding to the electrodes of the semiconductor element 11.

【0006】[0006]

【作用】導電部材25,30が素子封止用のダムリング
およびワイヤボンディングパッドを兼ねるから、ボンデ
ィングパッドを別に設ける必要がなくなり、占有実装面
積の縮小化,実装の低コスト化が可能になる。また、導
電部材30を半導体素子の電極数に応じて電気的に分離
することにより、占有実装面積の縮小化,低コスト化を
さらに向上できる。
[Operation] Since the conductive members 25 and 30 serve as a dam ring for element sealing and a wire bonding pad, there is no need to separately provide a bonding pad, making it possible to reduce the occupied mounting area and lower the cost of mounting. Moreover, by electrically separating the conductive member 30 according to the number of electrodes of the semiconductor element, it is possible to further reduce the occupied mounting area and reduce costs.

【0007】[0007]

【実施例】−第1の実施例− 図1〜図4は、本発明による半導体素子の実装構造の第
一の実施例を示すもので、図1は全体の縦断面図、図2
は封止樹脂およびコーティング材を取り除いた上面図、
図3はその外観図、図4は配線パターンとコーティング
層により形成される半田付け部のパターン図である。
[Embodiment] - First Embodiment - Figures 1 to 4 show a first embodiment of a mounting structure for a semiconductor element according to the present invention.
is a top view with the sealing resin and coating material removed;
FIG. 3 is an external view thereof, and FIG. 4 is a pattern diagram of a soldering portion formed by a wiring pattern and a coating layer.

【0008】図1〜図3において、図11および図12
と同一の部分には同一符号を付して説明する。11は基
板、12a〜12cは基板11上に形成された配線、1
3は基板11に実装される半導体素子、15は基板11
の非半田付け領域を保護するソルダーレジストからなる
コーティング層であり、このコーティング層により、半
導体素子13の実装に必要な半田付けパターンを形成す
る。例えば、図4に示すように配線12aの素子接合部
12a1上に矩形の半田付けパターン21を,配線12
bのボンディングパッド接合部12b1上に矩形の半田
付けパターン22を,配線12cの導電部材接合部12
c1上には半田付けパターン21,22を外周から取り
囲むように配線12aと12cを結ぶ線を中心にして対
称に配列した凹状の半田付けパターン23a,23bを
それぞれ形成する。
In FIGS. 1 to 3, FIGS. 11 and 12
The same parts will be described with the same reference numerals. 11 is a substrate, 12a to 12c are wirings formed on the substrate 11, 1
3 is a semiconductor element mounted on the substrate 11; 15 is the substrate 11;
This is a coating layer made of solder resist that protects the non-soldering area of the semiconductor element 13, and forms a soldering pattern necessary for mounting the semiconductor element 13. For example, as shown in FIG.
A rectangular soldering pattern 22 is placed on the bonding pad joint 12b1 of the wiring 12c, and a rectangular soldering pattern 22 is placed on the conductive member joint 12 of the wiring 12c.
Concave soldering patterns 23a and 23b are formed on c1, respectively, so as to surround the soldering patterns 21 and 22 from the outer periphery and are arranged symmetrically about the line connecting the wirings 12a and 12c.

【0009】このようにした基板11の半田付けパター
ン21上、すなわち配線12aの素子接合部12a1上
には半導体素子13が半田14により接合され、半田付
けパターン22上,すなわち配線12bのボンディング
パッド接合部12b1上にはボンディングパッド17a
が半田16により接合され、さらに半田付けパターン2
3a,23b上、すなわち導電部材接合部12cには半
田24により四角筒状の導電部材25が接合される。
The semiconductor element 13 is bonded with solder 14 on the soldering pattern 21 of the substrate 11, that is, on the element bonding portion 12a1 of the wiring 12a, and the semiconductor element 13 is bonded on the soldering pattern 22, that is, on the bonding pad of the wiring 12b. A bonding pad 17a is provided on the portion 12b1.
are joined by solder 16, and further solder pattern 2
A square cylindrical conductive member 25 is joined by solder 24 to the conductive member joining portion 12c on the conductive member 3a and 23b.

【0010】導電部材25は、半導体素子13を樹脂封
止するためのダムリングと、半導体素子13のワイヤボ
ンディングに用いられるボンディングパッドの両方の機
能を備えるもので、アルミニウム,鉄,銅等の金属材か
らなり、そして半導体素子13およびボンディングパッ
ド17aを外周囲から包囲する大きさの四角筒状に成形
される。また、導電部材25の内面側上縁にはワイヤボ
ンディング用の段部25aが形成されており、この段部
25aと半導体素子13の他方の電極13b間はワイヤ
18bにより接続される。さらに半導体素子13の一方
の電極13aとボンディングパッド17a間はワイヤ1
8aにより接続される。
The conductive member 25 has the functions of both a dam ring for resin-sealing the semiconductor element 13 and a bonding pad used for wire bonding of the semiconductor element 13, and is made of metal such as aluminum, iron, copper, etc. It is formed into a rectangular cylindrical shape with a size that surrounds the semiconductor element 13 and bonding pad 17a from the outer periphery. Further, a step 25a for wire bonding is formed on the upper edge of the inner surface of the conductive member 25, and the step 25a and the other electrode 13b of the semiconductor element 13 are connected by a wire 18b. Further, a wire 1 is connected between one electrode 13a of the semiconductor element 13 and the bonding pad 17a.
8a.

【0011】半導体素子のワイヤボンディングが完了し
たあとの導電部材25の内側には、図1に示すように封
止用の樹脂材20を充填して半導体素子13を完全に封
止する。このとき、充填される樹脂材20は粘度が高い
ため、導電部材25の半田付けされない部分26(図2
参照)から流れ出すことがなく、その部分26も樹脂材
20によって密封されるから、半導体素子の封止は確実
になる。
After the wire bonding of the semiconductor element is completed, the inside of the conductive member 25 is filled with a sealing resin material 20, as shown in FIG. 1, to completely seal the semiconductor element 13. At this time, since the resin material 20 filled has a high viscosity, the portion 26 of the conductive member 25 that is not soldered (FIG.
Since the part 26 is also sealed by the resin material 20, the semiconductor element can be reliably sealed.

【0012】このように本実施例の半導体素子の実装構
造においては、半導体素子13を樹脂封止する導電部材
25が半導体素子の一方のボンディングパッドを兼ねる
から、図11,図12に示す従来の実装構造に比較して
一方のボンディングパッドを省略できる。これに伴い一
方のボンディングパッドの設置エリアが不要になるから
、図2および図12からも明らかなように従来と同じ実
装設計ルールであっても、導電部材25の大きさが一方
のボンディングパッドを省略したことにより得られる面
積に相当する分小さくなり、半導体素子全体の実装面積
を縮小できる。これにより基板上への半導体素子の実装
密度を向上できる。
As described above, in the semiconductor element mounting structure of this embodiment, the conductive member 25 for resin-sealing the semiconductor element 13 also serves as one bonding pad of the semiconductor element. Compared to the mounting structure, one of the bonding pads can be omitted. As a result, the installation area for one of the bonding pads becomes unnecessary, so as is clear from FIGS. 2 and 12, even if the mounting design rules are the same as in the past, the size of the conductive member 25 is larger than that of one of the bonding pads. The size is reduced by an amount equivalent to the area obtained by omitting it, and the mounting area of the entire semiconductor element can be reduced. This makes it possible to improve the mounting density of semiconductor elements on the substrate.

【0013】導電部材25は、アルミニウム等の熱伝導
率の高い金属から成形されているため、半導体素子13
で発生した熱を効率良く放射することが出来る。また、
封止樹脂20は熱膨張係数が大きく、外部環境の温度変
化により大きな熱応力を発生するが、封止樹脂20を取
り囲む導電部材25は機械的強度が大きく(変形しにく
く)、かつ樹脂に比し熱膨張係数が小さいため、封止樹
脂20の横方向の延びを制限し、その熱応力を抑制でき
る。その結果、半導体素子等への熱応力による影響を低
減できる。
Since the conductive member 25 is molded from a metal with high thermal conductivity such as aluminum, the semiconductor element 13
The heat generated can be efficiently radiated. Also,
The sealing resin 20 has a large coefficient of thermal expansion and generates large thermal stress due to temperature changes in the external environment, but the conductive member 25 surrounding the sealing resin 20 has high mechanical strength (does not easily deform) and has a high mechanical strength compared to the resin. Since the coefficient of thermal expansion is small, the lateral extension of the sealing resin 20 can be restricted and its thermal stress can be suppressed. As a result, the influence of thermal stress on semiconductor elements and the like can be reduced.

【0014】導電部材25はダムリングとボンディング
パッドの両方の機能を備えることにより、専用のボンデ
ィングパッドなどの部品数および実装工数を低減できる
。また、導電部材25は半導体素子13の周囲のいずれ
の位置からでもボンディングパッドとして機能するから
、半導体素子とのワイヤボンディングの自由度が大きく
なり、実装設計および製造工程が容易になる。さらに、
導電部材25は、アルミニウム,鉄,銅等の金属材から
簡単に加工できるため、安価に製造できる。
Since the conductive member 25 functions as both a dam ring and a bonding pad, the number of components such as dedicated bonding pads and the number of mounting steps can be reduced. Moreover, since the conductive member 25 functions as a bonding pad from any position around the semiconductor element 13, the degree of freedom in wire bonding with the semiconductor element is increased, and the packaging design and manufacturing process are facilitated. moreover,
The conductive member 25 can be easily manufactured from metal materials such as aluminum, iron, copper, etc., and therefore can be manufactured at low cost.

【0015】図2から明らかなように一方のボンディン
グパッドが省略されることにより、ダムリングとしての
導電部材の容積を従来のものより小さくできるから、半
導体素子を封止する樹脂量を削減できる。特に封止樹脂
量の削減は、イオン含有率の低いエポキシ,シリコン樹
脂などの高価な樹脂を用いた場合、コスト面からも有効
となる。さらに、半導体素子がトランジスタの場合、そ
のエミッタなどがワイヤボンディングされる導電部材の
電位は接地電位となるため、トランジスタ周囲を外来ノ
イズ等からシールドすることができる。
As is clear from FIG. 2, by omitting one of the bonding pads, the volume of the conductive member as a dam ring can be made smaller than that of the conventional one, so the amount of resin for sealing the semiconductor element can be reduced. In particular, reducing the amount of sealing resin is effective from a cost perspective when using expensive resins such as epoxy and silicone resins with low ion content. Further, when the semiconductor element is a transistor, the potential of the conductive member to which the emitter and the like are wire-bonded is the ground potential, so that the area around the transistor can be shielded from external noise and the like.

【0016】−第2の実施例− 図5および図6は、本発明の第2の実施例を示すもので
、図5は全体の縦断面図、図6は半導体素子実装部分の
配線パターンの平面図である。図5および図6において
、第1の実施例で示す図1および図4と同一の部分には
同一の符号を付してその説明を省略し、異なる部分を重
点的に述べる。第1の実施例と異なる点は、図6に示す
ように基板表面をコーティングするソルダーレジスト用
のコーティング層15により、配線12aの素子接合用
半田付けパターン21,配線12bのボンディングパッ
ド接合用半田付けパターン22、配線12c導電部材接
合用半田付けパターン23a,23bを形成した後、半
田付けパターン23a,23bおよび配線12a,12
bと直交する部分A,Bのコーティング層15上に導電
性の印刷ペーストにより接合パターン26をエンドレス
に形成し、そして、接合パターン26上には、図5に示
すように半田27によって導電部材25を接合したとこ
ろにある。なお、接合パターン26と導電部材25との
接合は半田のみに限らず、導電性の接着剤などでも良い
-Second Embodiment- FIGS. 5 and 6 show a second embodiment of the present invention. FIG. 5 is a longitudinal cross-sectional view of the whole, and FIG. 6 is a diagram of a wiring pattern of a semiconductor element mounting part. FIG. In FIGS. 5 and 6, the same parts as in FIGS. 1 and 4 shown in the first embodiment are given the same reference numerals, and the explanation thereof will be omitted, and different parts will be mainly described. The difference from the first embodiment is that, as shown in FIG. 6, a coating layer 15 for a solder resist coats the surface of the substrate, so that a soldering pattern 21 for connecting the wiring 12a to the element and a soldering pattern 21 for joining the bonding pad to the wiring 12b are formed. After forming the pattern 22, the wiring 12c and the soldering patterns 23a and 23b for joining conductive members, the soldering patterns 23a and 23b and the wiring 12a and 12 are formed.
A bonding pattern 26 is endlessly formed using a conductive printing paste on the coating layer 15 in the portions A and B perpendicular to the direction B, and a conductive member 25 is formed on the bonding pattern 26 by solder 27 as shown in FIG. It is located where the . Note that the bonding between the bonding pattern 26 and the conductive member 25 is not limited to solder, but may also be conducted using a conductive adhesive or the like.

【0017】このような第2の実施例においては、接合
パターン26によって導電部材25の下端縁を基板表面
に隙間なく完全に接合することが出来る。これに伴い封
止用樹脂20に粘度の低い樹脂材を用いても樹脂が導電
部材から外部へ流出することがないほか、基板表面と導
電部材との接合部分から水分が侵入したり、不純物や塵
埃等が侵入したりするのを完全に防止できる。
In the second embodiment, the lower edge of the conductive member 25 can be completely bonded to the substrate surface by the bonding pattern 26 without any gaps. Accordingly, even if a resin material with low viscosity is used as the sealing resin 20, the resin will not leak out from the conductive member, and moisture will not enter from the joint between the substrate surface and the conductive member, and impurities and It can completely prevent dust from entering.

【0018】−第3の実施例− 図7は、本発明の第3の実施例を示す縦断面図である。 図7において、図5と同一符号は同一部分を表わし、同
一構成になっている。そして、図5と異なる点は、半導
体素子を樹脂封止に代えて気密封止構造にしたところに
ある。すなわち、基板11の表面に接合パターン26お
よび半田27により接合した導電部材25の開口端には
、平板状のリッド28が半田29等により接合され、こ
れによって導電部材25内の半導体素子13を気密封止
している。
-Third Embodiment- FIG. 7 is a longitudinal sectional view showing a third embodiment of the present invention. In FIG. 7, the same reference numerals as in FIG. 5 represent the same parts and have the same configuration. The difference from FIG. 5 is that the semiconductor element is hermetically sealed instead of resin-sealed. That is, a flat lid 28 is bonded to the open end of the conductive member 25 which is bonded to the surface of the substrate 11 by a bonding pattern 26 and solder 27 using solder 29 or the like. It's sealed.

【0019】このような第3の実施例においては、リッ
ド28を導電部材25の開口端面に接合することで簡単
に気密封止することができるほか、封止用樹脂がないた
め、半導体素子への熱応力の問題がなくなり、水分等の
侵入を防止できる。また、半導体素子の周囲および上部
を導電部材とリッドにより完全にシールドすることによ
り、外来ノイズの侵入を防止するシールド効果をより向
上できる。
In the third embodiment, the lid 28 can be easily hermetically sealed by bonding it to the open end surface of the conductive member 25, and since there is no sealing resin, there is no possibility of sealing the semiconductor element. This eliminates the problem of thermal stress and prevents moisture from entering. Moreover, by completely shielding the periphery and upper part of the semiconductor element with the conductive member and the lid, the shielding effect for preventing the intrusion of external noise can be further improved.

【0020】−第4の実施例− 図8および図9は、本発明の第4の実施例を示す縦断面
図および全体の外観図である。図8および図9において
、第1の実施例に示す場合と同様に基板11に形成した
配線12aの素子接合部12a1上には半導体素子13
が半田14により接合されている。また、ダムリングと
ボンディングパッドを兼ねる導電部材30は、基板11
上の半導体素子13の外周囲を取り囲む四角筒状に成形
されている。この導電部材30は、絶縁材30c,30
dにより半導体素子13の電極13a,13bに対応し
た2つの導電部分30a,30bに電気的に分離されて
いる。
-Fourth Embodiment- FIGS. 8 and 9 are a longitudinal sectional view and an overall external view showing a fourth embodiment of the present invention. In FIGS. 8 and 9, a semiconductor element 13 is placed on an element bonding portion 12a1 of a wiring 12a formed on a substrate 11 in the same manner as in the first embodiment.
are joined by solder 14. Further, the conductive member 30 that also serves as a dam ring and a bonding pad is connected to the substrate 11.
It is formed into a rectangular cylinder shape surrounding the outer periphery of the upper semiconductor element 13. This conductive member 30 includes insulating materials 30c, 30
d into two conductive portions 30a and 30b corresponding to the electrodes 13a and 13b of the semiconductor element 13.

【0021】基板11の表面には、導電部分30a,3
0bの下面形状と同一の接合パターン32a,32bが
導電性の印刷ペーストにより形成されており、このうち
接合パターン32aは基板11上の配線12bと電気的
に接続され、接合パターン32bは基板11上の配線1
2cと電気的に接続される。また、接合パターン32a
上には一方の導電部分30aが半田33等により接続さ
れ、接合パターン32b上には他方の導電部分30bが
半田33等により接合される。そして、半導体素子13
の電極13aと導電部分30a間はワイヤ18aにより
接続され、半導体素子13の電極13bと導電部分30
b間はワイヤ18bにより接続される。
The surface of the substrate 11 has conductive portions 30a, 3
Bonding patterns 32a and 32b, which have the same shape as the bottom surface of 0b, are formed using conductive printing paste. Of these, the bonding pattern 32a is electrically connected to the wiring 12b on the substrate 11, and the bonding pattern 32b is connected to the wiring 12b on the substrate 11. wiring 1
It is electrically connected to 2c. In addition, the bonding pattern 32a
One conductive portion 30a is connected on top with solder 33 or the like, and the other conductive portion 30b is connected on top of the bonding pattern 32b with solder 33 or the like. And the semiconductor element 13
The electrode 13a of the semiconductor element 13 and the conductive portion 30a are connected by a wire 18a, and the electrode 13b of the semiconductor element 13 and the conductive portion 30a are connected by a wire 18a.
b is connected by a wire 18b.

【0022】このような第4の実施例においては、第1
の実施例と同様な作用効果が得られるほか、導電部材3
0が半導体素子の全ての電極をワイヤにて接続できるボ
ンディングパッドの機能を有するから、従来のようにボ
ンディングパッドを別に設ける必要がなくなる。これに
伴い導電部材の容積がさらに小さくなり、半導体素子の
実装面積もさらに減少し、半導体素子の実装密度を向上
できる。
[0022] In such a fourth embodiment, the first
In addition to obtaining the same effects as in the embodiment, the conductive member 3
Since 0 has the function of a bonding pad that can connect all the electrodes of the semiconductor element with wires, there is no need to separately provide a bonding pad as in the conventional case. Accordingly, the volume of the conductive member is further reduced, the mounting area of the semiconductor element is also further reduced, and the mounting density of the semiconductor element can be improved.

【0023】−第5の実施例− 図10は、本発明の第5の実施例を示す縦断面図である
。図10において、第5図と同一の部分には同一符号を
付してその説明を省略し、第5図と異なる部分を重点的
に述べる。図10からも明らかなように、この実施例に
おける特徴部分は、導電部材25Aの外周面に基板11
上の他の配線へのワイヤボンディング用段部25bを形
成し、この段部25bを利用して、基板11上の他の配
線12dに接合したボンディングパッド34との間をワ
イヤ35により接続できるようにしたところにある。
-Fifth Embodiment- FIG. 10 is a longitudinal sectional view showing a fifth embodiment of the present invention. In FIG. 10, parts that are the same as those in FIG. 5 are given the same reference numerals, and their explanations will be omitted, and parts that are different from those in FIG. 5 will be mainly described. As is clear from FIG. 10, the feature of this embodiment is that the substrate 11 is attached to the outer peripheral surface of the conductive member 25A.
A step 25b for wire bonding to other wiring on the substrate 11 is formed, and this step 25b can be used to connect the wire 35 to the bonding pad 34 bonded to the other wiring 12d on the substrate 11. It's located where I left it.

【0024】したがって、第5の実施例においては、第
2の実施例に示す場合と同様な作用効果が得られるほか
、導電部材25Aを基板上の他の素子用配線へのボンデ
ィングパッドとしても使用できる。つまり、ワイヤボン
ディングによる他配線へのワイヤ結線が可能になること
によって、空中配線によるジャッパ線あるいは素子への
接続配線に利用することができる。
Therefore, in the fifth embodiment, in addition to obtaining the same effects as those shown in the second embodiment, the conductive member 25A can also be used as a bonding pad to wiring for other elements on the substrate. can. In other words, since it becomes possible to connect wires to other wirings by wire bonding, it can be used for connection wiring to jumper wires or elements using aerial wiring.

【0025】なお、上記各実施例では、ダムリングおよ
びボンディングパッドを兼ねる導電部材を金属で成形す
る場合について述べたが、これに限定されない。例えば
絶縁材からなる母材表面にカーボンフィラー,Agフィ
ラー,メッキなどの導電層を形成する構造のものでも良
い。特にボンディングパッドに相当する必要部分にメッ
キなどの導電層を施してボンディングパッド兼用のダム
リングを成形することは容易であり、導電部材の低コス
ト化が図れる。また、第4の実施例では、導電部材を電
気的に2つに分離する場合について述べたが、その電気
的分離数は実施例のものに限定されない。
[0025] In each of the above embodiments, a case has been described in which the conductive member serving as the dam ring and the bonding pad is molded from metal, but the present invention is not limited to this. For example, it may have a structure in which a conductive layer such as carbon filler, Ag filler, or plating is formed on the surface of a base material made of an insulating material. In particular, it is easy to form a dam ring that also serves as a bonding pad by applying a conductive layer such as plating to a necessary portion corresponding to a bonding pad, and the cost of the conductive member can be reduced. Further, in the fourth embodiment, a case has been described in which the conductive member is electrically separated into two parts, but the number of electrical separations is not limited to that in the embodiment.

【0026】[0026]

【発明の効果】以上説明したように本発明によれば、素
子の封止用ダムリングとワイヤボンディングパッドの両
方の機能を有する導電部材を利用して半導体素子を実装
できるようにしたので、別構造のボンディングパッドが
不要もしくは削減することができ、このことによって占
有実装面積の小さい高密度実装が可能になるとともに、
ボンディングパッドなどの実装部品数および実装工数が
削減され大幅なコスト低減ができる。また、導電部材の
放熱性が良好となり、半導体素子の信頼性が向上し、樹
脂封止タイプのものであっても半導体素子に加わる熱応
力を低減できる。さらに、導電部材は半導体素子の外周
囲を包囲する構造になっているから、ワイヤボンディン
グの自由度が広がり、実装設計が容易になる。また、導
電部材を半導体素子の電極数に対応して電気的に複数に
分離することにより、半導体素子用のワイヤボンディン
グパッドが不要になり、実装面積の縮小化および高密度
実装をさらに向上できる。
[Effects of the Invention] As explained above, according to the present invention, a semiconductor device can be mounted using a conductive member that functions as both a dam ring for device sealing and a wire bonding pad. Bonding pads in the structure can be eliminated or eliminated, which enables high-density mounting with a small footprint, and
The number of components to be mounted such as bonding pads and the number of mounting steps are reduced, resulting in significant cost reductions. Further, the heat dissipation of the conductive member is improved, the reliability of the semiconductor element is improved, and even if the semiconductor element is of a resin-sealed type, thermal stress applied to the semiconductor element can be reduced. Furthermore, since the conductive member has a structure that surrounds the outer periphery of the semiconductor element, the degree of freedom in wire bonding is increased and mounting design is facilitated. Further, by electrically separating the conductive member into a plurality of parts corresponding to the number of electrodes of the semiconductor element, wire bonding pads for the semiconductor element are no longer necessary, and the mounting area can be reduced and high-density packaging can be further improved.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の第1の実施例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.

【図2】第1の実施例における実装構造の一部を取り除
いて示す上面図である。
FIG. 2 is a top view showing the mounting structure in the first embodiment with a part removed.

【図3】第1の実施例における実装構造の外観図である
FIG. 3 is an external view of the mounting structure in the first embodiment.

【図4】第1の実施例における配線パターンとコーティ
ング層により形成される半田付け部のパターン図である
FIG. 4 is a pattern diagram of a soldering portion formed by a wiring pattern and a coating layer in the first embodiment.

【図5】本発明の第2の実施例を示す縦断面図である。FIG. 5 is a longitudinal sectional view showing a second embodiment of the invention.

【図6】第2の実施例における実装部分の配線パターン
図である。
FIG. 6 is a wiring pattern diagram of a mounting portion in a second embodiment.

【図7】本発明の第3の実施例を示す縦断面図である。FIG. 7 is a longitudinal sectional view showing a third embodiment of the present invention.

【図8】本発明の第4の実施例を示す縦断面図である。FIG. 8 is a longitudinal sectional view showing a fourth embodiment of the present invention.

【図9】第4の実施例における実装構造の外観図である
FIG. 9 is an external view of a mounting structure in a fourth embodiment.

【図10】本発明の第5の実施例を示す縦断面図である
FIG. 10 is a longitudinal sectional view showing a fifth embodiment of the present invention.

【図11】従来の半導体素子の実装構造を示す縦断面図
である。
FIG. 11 is a vertical cross-sectional view showing a conventional semiconductor element mounting structure.

【図12】従来の実装構造の一部を取り除いて示す上面
図である。
FIG. 12 is a top view showing a conventional mounting structure with a part removed.

【符号の説明】[Explanation of symbols]

11  基板 12a〜12c  配線 13  半導体素子 13a,13b  電極 17a,17b  ボンディングパッド18a,18b
  ワイヤ 20  封止樹脂 25,30  導電部材 30c,30d  絶縁材
11 Substrates 12a to 12c Wiring 13 Semiconductor elements 13a, 13b Electrodes 17a, 17b Bonding pads 18a, 18b
Wire 20 Sealing resin 25, 30 Conductive member 30c, 30d Insulating material

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  基板上に半導体素子を固着し、この半
導体素子の電極と前記基板上の配線間を電気的に接続し
た後封止する半導体素子の実装構造において、前記基板
上の一部の配線と電気的に接続され、かつ封止用ダムリ
ングおよびワイヤボンディングパッド機能を兼ねた導電
部材を前記半導体素子の外周囲を取り囲むようにして前
記基板上に固着したことを特徴とする半導体素子の実装
構造。
1. A semiconductor element mounting structure in which a semiconductor element is fixed on a substrate, and electrodes of the semiconductor element and wiring on the substrate are electrically connected and then sealed. A semiconductor element, characterized in that a conductive member that is electrically connected to wiring and also serves as a sealing dam ring and a wire bonding pad is fixed on the substrate so as to surround the outer periphery of the semiconductor element. Implementation structure.
【請求項2】  導電部材が半導体素子の電極に対応し
た数に電気的に分離されていることを特徴とする請求項
1記載の半導体素子の実装構造。
2. The semiconductor device mounting structure according to claim 1, wherein the conductive members are electrically separated into a number corresponding to the electrodes of the semiconductor device.
JP3171693A 1991-06-17 1991-06-17 Mounting structure of semiconductor device Pending JPH04369250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3171693A JPH04369250A (en) 1991-06-17 1991-06-17 Mounting structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3171693A JPH04369250A (en) 1991-06-17 1991-06-17 Mounting structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04369250A true JPH04369250A (en) 1992-12-22

Family

ID=15927941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3171693A Pending JPH04369250A (en) 1991-06-17 1991-06-17 Mounting structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04369250A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621242A (en) * 1994-05-16 1997-04-15 Samsung Electronics Co., Ltd. Semiconductor package having support film formed on inner leads

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6266650A (en) * 1985-09-19 1987-03-26 Fujitsu Ltd Package for semiconductor device
JPS6251748B2 (en) * 1983-01-25 1987-10-31 Meiwa Sangyo

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251748B2 (en) * 1983-01-25 1987-10-31 Meiwa Sangyo
JPS6266650A (en) * 1985-09-19 1987-03-26 Fujitsu Ltd Package for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621242A (en) * 1994-05-16 1997-04-15 Samsung Electronics Co., Ltd. Semiconductor package having support film formed on inner leads

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