JPH04359338A - Electronic apparatus for business - Google Patents

Abstract

PURPOSE:To shorten the wait time to start by increasing the inspection speed of the operation of a RAM which is executed at the time of initialization for power-on of an electronic apparatus for business. CONSTITUTION:The overall area of a RAM 5 to be inspected is preliminarily divided into plural, for example, 16 areas having the same capacity. First, a RAM access means 2 writes prescribed test data in a start area Aa in accordance with the control of a RAM diagnosing means 1. Next, a DMA(direct memory access) means 3 repeatedly directly transfers contents of preceding areas to following areas from the start area Aa to a last area Dd through intermediate areas Ab to Dc. Finally, a deciding means 4 compares contents, which the RAM access means 2 reads out of the last area Dd, with first test data to decide match/unmatch.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to office electronic equipment that is equipped with a circuit board or memory board that is detachable from or to the main body of the equipment, or a connecting means such as a connector for an expansion circuit board or memory board. Regarding.

0002

[Prior Art] Office electronic equipment includes color image forming devices such as dot printers, electrostatic printers or electrostatic copying machines, and digital copying machines, communication devices such as facsimiles and computer communications, offset printing machines, etc. Document creation devices such as DTP (desktop printers) and word processors, AV information recording and playback devices such as VTRs and VDRs that record and play back information as sounds or images on tapes, disks, display devices that display information, and video printers that create hard copies. Equipment, so-called calculators, electronic notebooks, computers, EWS
There are a wide variety of information processing devices such as

[0003] These office electronic devices are one-board (
With the exception of devices that have a fixed circuit board for miniaturization, such as calculators with a single board (single board), in order to facilitate inspection, assembly, and maintenance, single board or e.g.
Multiple boards (substrates) separated into a control board equipped with a control circuit consisting of U and its peripheral elements, a memory board equipped with relatively large capacity ROM and RAM, etc. are connected to the main body of the device via respective connectors. It is configured to be removably attached.

[0004] If the scale becomes even larger, the control board will become
A main control board with a main CPU that controls the entire device, and one or more sub-CPUs that share and control the operations and conditions of each part according to instructions from the main CPU. It can be separated from the control board, and additional circuit boards are available as options to expand specifications and increase speed.

[0005] Memory boards also include replacement and expansion ROM boards that store fixed data such as programs for changing or expanding functions and different character fonts, and expansion RAM boards for expanding memory capacity. There are two types of devices: one is to attach them directly to the device body, and the other is to have a support board attached to the device body so that a plurality of comparatively small ROM boards and RAM boards can be attached thereon.

[0006] Circuit boards and ROMs containing these control boards
If a memory board, such as a RAM board, is not properly installed or becomes loose over time, it may become inoperable or cause an error. Therefore, it goes without saying that inspection is required at the time of installation, but also every time the equipment is turned on. In addition to initial settings, the installed RAM was checked for operation.

[0007] Furthermore, in order to repair and maintain equipment, it is necessary to record initial settings such as various conditions and constants, usage time of the equipment, frequency of use, types of accidents that have occurred, and settings that have been changed during repairs. However, instead of being a document format that requires human intervention and is easily lost, automatic recording is now possible, and data is recorded in non-volatile memory that retains data even when the power is turned off. The nonvolatile memory is generally accessed by the CPU of the control board on which it is mounted.

[0008]

[Problem to be solved by the invention] However, RAM
Conventional RAM operation checks, in which test data is written and read out, and the read data is checked to determine whether it matches the test data, are not a problem as long as the RAM has a small capacity. As the performance of devices increases and the capacity of RAM increases, the time required for writing, reading, and matching judgment cannot be ignored, and the initial time from when the operator turns on the power until it is ready for use is increasing. It's starting to feel like a long time.

[0009] Furthermore, if an abnormality is found after inspecting the operation of the RAM, and if it is not possible to identify the board or element of the RAM that is abnormal, it is necessary to remove all the boards and inspect them, or to remove the abnormal board. Inspecting each of the above RAM elements required time on the factory side as well, making it extremely difficult to provide on-site service. Therefore, it has been desired to identify an abnormal RAM board so that at least the board can be replaced.

[0010] Even if it is possible to discover or identify an abnormality caused by the installation of a circuit board or memory board by some method, it is difficult to detect or identify the possibility of an abnormality before it occurs. It was impossible to do so.

[0011] Furthermore, if the circuit board or memory board (hereinafter also referred to as "board") in which an abnormality has occurred or is likely to occur can be identified, and its part name, abbreviation, part number, etc. However, in order to replace the identified board, it is necessary to refer to the maintenance manual or read the notation on the board to find the board to be replaced, which takes time.

[0012] Furthermore, since the non-volatile memory that records initial settings and usage history is accessed by the CPU of the mounted board, if an abnormality occurs in the CPU or its peripheral circuits and the control board needs to be replaced. Because it is not possible to read the data recorded in non-volatile memory,
There was a problem in that the data could not be transferred to the nonvolatile memory on the new control board, resulting in the loss of valuable records.

[0013] The present invention has been made in view of the above points, and it is possible to speed up the operation inspection of the RAM to shorten the initial time, or to detect the occurrence or fear of occurrence of a failure to enable quick response processing. Another object of the present invention is to provide an office electronic device in which the contents stored in the installed nonvolatile memory are not lost even if a failure occurs in the control board.

[0014]

[Means for Solving the Problems] In order to achieve the above-mentioned object, the first invention provides an office electronic device equipped with a mounting means for mounting a removable RAM board.
A RAM access means for writing and reading data into and from the RAM on the mounted RAM board, and a determining means for comparing the data written by the RAM access means and the data read after writing to determine whether they match or do not match. , direct memory access means that directly transfers the contents from any area of RAM to another area of the same capacity without going through the CPU, and direct memory access that writes test data to the start area of RAM using RAM access means. The means repeatedly directly transfers the test data from the start area to the intermediate areas of the same capacity, and finally transfers it to the last area, and then the judgment means writes the data read from the last area and the initial start area. A RAM diagnostic means is provided for controlling the test data so as to compare it with the loaded test data and determine whether it matches or does not match.

[0015] A second aspect of the present invention is, in an office electronic device equipped with a plurality of connectors to which removable RAM boards are respectively installed, board determination means for performing an operation test on the installed RAM boards to determine whether or not the RAM boards are installed. , and a propriety display means for displaying propriety for each RAM board according to the result determined by the board discriminator.

[0016] The third invention is an electronic office equipment equipped with a connector for attaching a removable circuit board or a memory board, in which a plurality of connectors each consisting of a pair of connection pins and a connection socket constituting the connector are provided. Of these, at least two sets of connectors at both ends of the connector or near both ends are used as detection connectors, and the length of the connection portion is shorter than that of the other connectors, and these detection connectors are connected to a circuit board or memory. A connection determining means for determining whether or not the board is connected when the board is installed, and a possibility display means for displaying whether or not the connection is possible for each circuit board or memory board according to the result determined by the connection determining means are provided. It is something.

[0017] In the second or third aspect of the invention, it is preferable that the availability display means be provided on the circuit board, the memory board, the RAM board, or in the vicinity of each connector.

[0018] The fourth invention is a CP that controls the operation of equipment.
Office electronics having one or more control boards equipped with U, at least one of which is equipped with a non-volatile memory for storing data such as initial setting values and usage history accessed by the CPU. In equipment, when a failure occurs in a control board equipped with nonvolatile memory, or a control board equipped with nonvolatile memory, a new one equipped with the failed control board and nonvolatile memory is installed. An auxiliary connector is provided to allow the control board or other control boards to be connected to each other, and when the failed control board is connected to a new control board or other control board via the auxiliary connector, the faulty control board The control board on which the nonvolatile memory is mounted is provided with means for making the nonvolatile memory of the controller accessible by the CPU of a new control board or another control board.

[0019]

[Operation] In the first invention, under the control of the RAM diagnostic means,
The RAM access means writes the test data to the start area, and the direct memory access means directly transfers the contents from the start area to the next intermediate area sequentially via intermediate areas of the same capacity, and finally the last directly transferred data. The contents read by the RAM access means from the area,
The determining means compares the test data with the original test data and determines whether they match or do not match, thereby determining whether or not all areas of the RAM are operating normally.

[0020] According to the direct memory access means that directly transfers data without going through the CPU, data can be moved much faster than the method of reading the contents using the RAM access means and writing them to other areas. In the first invention, since the data match/mismatch judgment only needs to be made once, the RAM operation check can be performed in an extremely short time.

[0021] In a second aspect of the present invention, the board determining means performs an operation test on the mounted RAM board to determine whether or not it is possible.
In accordance with the result, the acceptability display means displays the acceptability for each RAM board (it may be possible to display only accept or fail boards), so that the operator can easily identify the RAM board in which the abnormality has occurred.

[0022] In the third invention, the connecting portions of the two sets of detection connectors at or near both ends of the connector to which the circuit board or memory board is attached are formed to be shorter than the other connectors. If the insertion is insufficient,
The detection connector may not connect even if other connectors are connected. Therefore, if the connection determination means determines that the detection connectors at both ends of the connector are connected,
This means that the other connectors are securely connected, and the acceptability display means displays the acceptability for each circuit board or memory board according to the determination, so it is easy to check if the connections are insufficient or may be connected. can be specified.

[0023] In the second or third invention, for example, LE
A device for indicating availability consisting of a light emitting diode (D) or the like is provided on the circuit board, memory board, RAM board, or (
Since the connector is located near each connector (to which a board is attached), the board to be reattached or replaced can be found at a glance.

[0024] In the fourth invention, when a control board equipped with non-volatile memory fails, the failed control board is removed, a new control board equipped with non-volatile memory is replaced, and the failed control board is replaced with an auxiliary connector. Connect the board to the new or other control board. The CPU of the connected new control board or other control board can read the contents of the non-volatile memory of the failed control board through the means that makes it accessible and write them to the non-volatile memory of the new control board. , data such as initial setting values and usage history will not be lost.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic diagram showing the internal mechanism of a laser printer which is an embodiment of these inventions. Around the photosensitive drum 10, which rotates counterclockwise as shown by the arrow, there are a charging charger 11, a writing unit 12, a developing unit 13, a transfer charger 14,
Cleaning units 15 are arranged respectively.

The surface of the photosensitive drum 10 is first uniformly charged by a charging charger 11, and then a beam modulated by image data from a writing unit 12 and deflected in the main scanning direction forms a spot. main scanned,
An electrostatic latent image is formed. The electrostatic latent image is developed by the developing unit 13 and converted into a visualized toner image, and then the toner image is transferred by the transfer charger 14 onto a sheet of paper conveyed along the route shown by the dashed line. be done.

The toner and charge remaining on the photosensitive drum 10 are removed by the cleaning unit 15, and the removed toner is collected by the cleaning unit 15.

The paper is fed by the paper feed roller 19 from the paper stack 18 on the paper feed cassette 17, and after it comes into contact with the registration roller pair 20 and is temporarily stopped, the paper is written on the photoreceptor by the writing unit 12. The toner image is transferred to the transfer charger 14 by a pair of registration rollers 20 at a timing that matches the image on the drum 10.

The paper onto which the toner image has been transferred is conveyed to the fixing unit 21, pressed against the heated fixing roller 21a by the pressure roller 21b, and fixed by the heat and pressure. The paper is transported to output port 2.
3 and is discharged onto the paper discharge tray 24.

FIG. 3 is a block diagram showing an example of the control section of this laser printer. The controller 30 is a main microcomputer (hereinafter referred to as "CPU") 31
, a ROM 32 that stores necessary programs, constant data, character fonts, etc., a RAM 33 that stores temporary data and patterns, etc., an I/O 34 that controls input and output of commands and data, and an I/O 34 that stores the necessary programs, constant data, character fonts, etc. CP via
Consists of an operation panel 35 connected to U31 and an internal interface (I/F) 36, which are connected to each other by a data bus,
Connected via address bus, etc. Also, a host machine 48 that outputs print commands, character data, and image data.
is also connected to the CPU 31 via the I/O 34.

[0032] The engine driver 40 is a sub CPU 41
, a ROM 42 that stores the necessary programs and constant data, and a RAM 43 that stores temporary data.
and an I/O 44 that controls data input/output, and are connected to each other via a data bus, an address bus, etc.

The I/O 44 is connected to the internal interface 36 of the controller 30, and inputs video signals from the controller 30 and the states of various switches on the operation panel 35, and sends status signals such as image clock and paper end to the controller 30. Output to. Also, this I/
O44 is a printer engine 4 which is a printing means.
It is also connected to the writing unit 12 and other sequence equipment groups 46 that make up the writing unit 5, and various sensors 47.

The controller 30 receives print commands, character codes, and image data from the host machine 48, edits those codes and data, and stores the character codes in the ROM.
32 into a dot pattern necessary for image writing, and stores the dot patterns of those characters and images (hereinafter collectively referred to as "images") in a VRAM (video RAM) area in RAM 33. Leave it there.

When the image clock is input together with the ready signal from the engine driver 40, the controller 30
The dot pattern stored in the AM area is output to the engine driver 40 via the internal interface 36 serially or in parallel as a video signal synchronized with the image clock.

[0036] The engine driver 40 is connected to the controller 3
0, the writing unit 12 of the printer engine 45 and the sequence equipment group 46 are controlled,
Video signals necessary for image writing are input from the controller 30 and output to the writing unit 12, and signals indicating the status of each part of the engine are input from the sensors 47 and processed, and necessary information and error signals are sent to the controller. Output to 30.

FIG. 4 is a perspective view showing an example of a CNTR (controller) board, which is a control board on which the controller 30 shown in FIG. 3 is mounted. This CNTR board 37
is R consisting of the CPU 31 and a group of elements arranged in 4 rows and 5 columns.
OM 32, RAM 33 consisting of a group of elements arranged in 8 rows and 2 columns on two optional RAM boards 38a and 38b, I/O 34, I/F 36 (
It mainly consists of the following (Fig. 3), and also includes various ICs and a power element consisting of a three-terminal regulator that inputs DC power from the outside and supplies 5V constant voltage power to each element on the CNTR board 37. .

The I/O 34 and I/F 36 are composed of various connectors CN1 to CN7. The engine driver 40 and the operation panel 35 (Fig. 3) are attached to the connector CN1, and an optional IC card (not shown) is attached to the connector CN2. Communication terminals RS232C (serial) and Centronics (parallel), which are connected to external devices such as the host machine 48, are connected to connectors CN5 and CN6, and an option board mounting section (not shown) is connected to connector CN7. RAM boards 38a and 38b are attached to connectors CN3 and CN4, respectively. The operation of this CNTR board 37 has already been explained with reference to FIG. 3, so a description thereof will be omitted.

FIG. 1 is a functional block diagram showing a first embodiment of a laser printer according to the first invention. This first embodiment is comprised of a RAM diagnosis means 1, an access means 2, a direct memory access (direct transfer or direct memory access: hereinafter referred to as "DMA") means 3, a determination means 4, and a RAM 5. The RAM5 is
For example, it consists of four blocks A, B, C, and D each having a capacity of 1M bytes, and each block A to D is an area a having a capacity of 256K bytes divided into four equal parts.
, b, c, and d, the RAM 5 is composed of 16 areas each having the same capacity (256 Kbytes).

Here, it is assumed that the four blocks A to D are placed on four removable RAM boards A to D (not shown), and the area Aa of block A is the start area and the area of block D is Let Dd be the last area, and the other areas Ab to Dc be intermediate areas. The start, middle, and last areas only need to have the same capacity, and may be composed of any number of RAM elements (ICs).

First, the RAM diagnostic means 1 instructs the RAM access means 2 to write and store test data previously stored in a ROM (not shown) in the entire start area Aa. The size of the test data does not need to be 256 Kbytes, and test data of 1 Kbyte or, for example, 0.5, 1, or 2 bytes may be repeatedly written depending on the register capacity of the CPU.

The RAM diagnostic means 1 then instructs the DMA means 3 to DMA the contents of the start area Aa to the intermediate area Ab, and then to DMA the contents of the intermediate area Ab to the intermediate area Ac. If this is repeated 15 times, R
The test data that passed through the entire area of AM5 is the last area D.
It is stored in d.

Finally, the RAM diagnosis means 1 instructs the determination means 4 to compare the contents of the last area Dd read (by the RAM access means 2) with the test data written in the start area Aa, and determine whether they match or do not match. Let them judge. If they match, everything in the RAM 5 is normal, and if they do not match, it is known that there is an abnormality somewhere in the RAM 5.

Conventional RAM diagnosis involves the CPU reading test data from the ROM, writing it into the area to be diagnosed, and then reading out the written contents and comparing them with the original test data to determine whether they match or do not match. The presence or absence of an abnormality in that area was diagnosed using this method. In order to diagnose the entire RAM 5 using this method, ROM reading, RAM writing, RAM reading, and data judgment were required 16 times each.

On the other hand, in this first embodiment, the RAM
To diagnose the entire area of 5, it takes 1 ROM read, 1 RAM write, 1 data judgment, and 15 DMA.
Furthermore, since the data transfer by DMA is performed in a much shorter time than the data read/write cycle via the CPU, the diagnostic time for the entire RAM 5 is greatly shortened. This tendency becomes more noticeable as the capacity of the RAM increases and the number of areas increases.

[0046] If an abnormality is discovered at the end of the diagnosis,
In the conventional method, the area where the abnormality has occurred is specified (actually, even the address), but in this embodiment, the area cannot be specified. However, the occurrence of an abnormality is extremely rare, and no abnormality is recognized in most cases, so the advantage of significantly shortening the diagnosis time is great, and the disadvantage of not being identified is hardly a problem.

In the unlikely event that a discrepancy occurs between the contents of the last area Dd and the original test data and it is necessary to identify the RAM board or RAM element with the abnormality, it is necessary to check the contents of the last area Dd again in order from the start area Aa or the last area. D
By checking the contents of each area in reverse order from d and identifying an abnormal area, it is possible to identify the RAM board on which that area is mounted. If it is necessary to further identify the RAM element, the identified abnormal area can be further subdivided and the RAM element can be identified using the same procedure.

[0048] When the RAM capacity is large and there are many areas, the contents of the last areas Ad, Bd, and Cd of each block except the last area Dd are checked to identify the abnormal block, and then the identified block is checked. Checking each area within the block will shorten the identification time. Alternatively, the identification time can be further shortened by dividing the entire RAM area into two, checking the central area, for example, Bd, and repeating the process of further dividing the area on the abnormal side into two.

FIG. 5 is a perspective view showing a CNTR (controller) board of a second embodiment of the laser printer according to the second invention, and the same parts as the CNTR board shown in FIG. 4 are designated by the same reference numerals. The explanation will be omitted. This second embodiment includes a plurality of (two) connectors CN3 and CN4 to which removable RAM boards 38a and 38b are attached, respectively, and performs an operation test (diagnosis) of the RAM boards 38a and 38b to determine whether or not they are compatible. A CPU 31 and a DMA element 26 constituting a board determining means for making a determination, and an LED 27 that is an acceptability display means for indicating acceptability for each RAM board.
It consists of a and 27b.

The CPU 31 corresponds to the RAM diagnosis means 1, RAM access means 2, and determination means 4 shown in FIG.
The MA element 26 is also an IC incorporating a DMA circuit corresponding to the DMA means 3. Further, the RAM boards 38a and 38b are each equipped with blocks A and B and blocks C and D shown in FIG. 1, which are made up of RAM elements arranged in 8 rows and 1 column.

Therefore, in the first embodiment, if the contents of the last area Dd of the RAM 5 (corresponding to the RAM 33 of the second embodiment) match the original test data, it can be left as is; if they do not match, the operation panel 35 (Fig. 3
) displays the RAM abnormality on the display section of the CPU3.
1 checks the contents of the final area Bd of block B of RAM 5 on the RAM board 38a, and if they match, the LE
D27b is lit to indicate that there is an abnormality on the RAM board 38b, and if there is a mismatch, the LED 27a is lit to indicate that there is an error on the RAM board 38a.

[0052] In this way, when an operator or a service person who knows that an abnormality has occurred in the RAM by looking at the display section of the operation panel 35 opens the front or top cover (not shown) of the laser printer and looks at the CNTR board 37, , L
By lighting up the ED, you can immediately find the RAM board that should be replaced.

FIG. 6 is a perspective view showing a CNTR (controller) board of a third embodiment of the laser printer according to the third invention, and the same parts as the CNTR board shown in FIGS. 4 and 5 are designated by the same reference numerals. The explanation will be omitted. 7 and 8 are partially enlarged views of the connectors CN3 and CN4 shown in FIG. 6, FIG. 7 is a cross-sectional view of the socket and plug of the connector CN, and FIG. 8 is a plug consisting of a socket and a pattern on the RAM board 38. FIG.

In this third embodiment, as shown in FIG. 6, the LEDs 28a and 28b, which are the enable/disable display means for displaying the enable/disable of each RAM board (memory board), are mounted on the RAM boards 38a, 38b, respectively. As shown in FIG.
1a and 51z in series via a resistor Rd.

As shown in FIGS. 7 and 8, connector C
N is composed of a connector 50 consisting of a plurality of plugs 51 and sockets 52, and each plug 51a to 51z is connected to a (circuit) on the base plate 53 of the RAM board 38.
formed by a pattern. Each plug 51a-5
The sockets 52a to 52z corresponding to 1z are made of elastic metal pieces, one end of which is fixed to the socket cover 54 independently, and the other end is connected to the base plate of the RAM board 38 between the bottom surface 54b of the socket cover 54 and the bottom surface 54b of the socket cover 54. 53
and the corresponding plugs 51a to 51z thereon are elastically clamped.

The sockets 52a to 52z are of the same size, but the plugs 51a and 51z that constitute the detection connectors 50a and 50z at both ends of the connector (or in the vicinity thereof) are
It is formed to be slightly shorter (by Δ) than the other plugs 51b to 51y. Therefore, the length of the connection between the plug 51 and the socket 52 until the connector CN stops is shorter by Δ in the detection connectors 50a and 50z than in the other connectors 50b to 50y.

[0057] Socket 5 of detection connectors 50a and 50z
Since a DC voltage is applied to 2a and 52z from the DC power supply 55 of the device, if any one of the detection connectors 50a and 50z has a poor connection, L also serves as a connection determination means.
ED28 does not light up. Conversely, if the LED 28 is lit, the detection connectors 50a and 50z are connected together, so the other connectors 50b to 50b, which have longer connection parts,
50y is definitely connected.

As described above, RAM board 3 which is a memory board
8, and an example in which the LED 28, which is a means for indicating availability, is provided on the board has been described.
1a and 51z may be shorted together. Also, connector C
Since it is sufficient to provide at least two detection connectors at both ends of N or in the vicinity thereof, it goes without saying that the present invention can be applied not only to memory boards but also to control boards, expansion circuit boards, and the like.

As shown in FIGS. 5 and 6, for each circuit board or memory board such as a RAM board or ROM board, means for checking the operation or connection and indicating whether or not the operation or connection is possible is provided, such as LEDs 27 and 28. If it is provided on each substrate or board, or near the connector CN on the device main body side, it is possible to find at a glance a board that has a mounting defect or an abnormality and must be remounted or replaced.

9 and 10 are circuit diagrams showing the control board and its connections in a fourth embodiment of the laser printer according to the fourth invention, FIG. 9 is a circuit diagram in a normal state, and FIG. 10 is a circuit diagram showing a nonvolatile memory. FIG. 2 is a circuit diagram showing connections for accessing the nonvolatile memory when a failure occurs in the control board on which the control board is mounted.

In FIG. 9, a control board 60 is a main control board equipped with a main CPU 61 that controls the operation of the entire laser printer, and control boards 70 and 80 each control the operation of each part according to instructions from the main CPU 61. The control board 70 includes a non-volatile memory 78 for storing data such as initial setting values and usage history accessed by the CPU 71, and its peripheral circuits. A multiplexer 7
7 is installed.

In FIG. 10, a control board 70b is the one in which the CPU 71 or its peripheral circuit of the control board 70 shown in FIG. 9 has failed, and a control board 70n is a new control board installed in place of the failed control board 70b. The control board 70n and the control board 70 have exactly the same structure and have the same function. Control board 70b, 70
The code of each part mounted on n is given a subscript b,
Components shown with a suffix n and attached with a reference numeral without a subscript mounted on the control board 70, for example, the CPU 71 and the CPU 71b, are the same, and the CPU 71n is of the same type.

[0063] Furthermore, this fourth embodiment is shown in FIGS. 9 and 10.
As shown in , the control board 70 (and 70n) and the control board 80 have an auxiliary connector 76 (and 76n) and an auxiliary connector 86 are provided on the control board 70 (and 70n) and the control board 80, respectively. During normal operation, the control boards 60, 70, and 80 are connected to the main body of the device through main body connectors 65, 75, and 85, respectively, and are supplied with power of, for example, DC5V from the DC power supply 55, and the control boards are connected to each other by data bus, address bus, etc. are connected by.

In FIG. 9, the control board 60 is, for example, a board for the controller 30 (FIG. 3), and includes a CPU 61, a memory (MEM) 62 consisting of a ROM 32 and a RAM 33, an I/O 34, and an internal interface 36. A serial communication port (hereinafter referred to as “COM”) that supports
) 63 and a main body connector 65, the operation of which has already been explained and will therefore be omitted.

The control board 70 is, for example, the engine driver 4.
0 (FIG. 3) and the CPU 71 which is the CPU 41.
A common power supply for the memory 72 consisting of ROM 42 and RAM 43, which are peripheral circuits, the main body connector 75, the auxiliary connector 76, the non-volatile memory 78 and the multiplexer 77, which is its peripheral circuit, and the control board 70. The engine driver 40 is composed of a backflow blocking diode D and a resistor R provided on the Vcc side of DC5V, and a description of the original function of the engine driver 40 will be omitted.

The control board 80 is a control board that controls, for example, an input section and a display section (not shown) that constitute the operation panel 35 (FIG. 3), and includes a CPU 81 and its peripheral circuits such as a memory 82, COM 83, and I/O 84. , consists of a main body connector 85 and an auxiliary connector 86, and its original function is to output operator instructions input from the input section by the CPU 81, memory 82, and COM 83 to the control board 60, and to output messages input from the control board 60 to the display section. to be displayed.

Peripheral circuits for accessing nonvolatile memory 78 will be explained below. I on the control board 70
As shown in FIG. 9, /O74 is an I/O for the CPU 71 to access the nonvolatile memory 78 during normal operation, and is connected to the input terminals A1, A2, A3 of the multiplexer 77 and the output terminal DO of the nonvolatile memory 78. are connected to each other.

As shown in FIG. 10, the I/O 84 on the control board 80 connects the auxiliary connector 86 and the failed control board 7.
When the auxiliary connector 76b of 0b is connected, the CPU
81 to access the nonvolatile memory 78b.
O, and the input terminals B1 and B2 of the multiplexer 77b
, B3 and the output terminal DO of the nonvolatile memory 78b, but normally, as shown in FIG. 9, the auxiliary connector 86 and the auxiliary connector 76 are separated and therefore do not function.

[0069] The nonvolatile memory 78 is
The multiplexer 77, which is a means for making it accessible from the PU, has two sets of input terminals A1, A2, A3 and B1, B2, B3 each having three terminals, and a set of output terminals Y1, Y2. , Y3, and the select terminal S is “
When it is “H”, it is connected to terminals A1 to A3, and when it is “L”, it is connected to terminals B1 to A3.
The input signals of B3 are selected and outputted from terminals Y1 to Y3.

The nonvolatile memory 78 may be a battery-backed RAM, but in this fourth embodiment, an EEPR
OM, for example, use commercial product 9346, multiplexer 7
Terminal CK connected to output terminals Y1 and Y2 of 7, respectively.
, CS is the control signal input terminal, output terminal Y3
The terminal DI connected to is the input terminal for the specified address and serial data, and the terminal DO connected to I/O 74 (and I/O 84 when the auxiliary connector is connected) is the output terminal for the read serial data. It is.

As shown in FIG. 9, when the auxiliary connector 76 is not connected, the power supply for the multiplexer 77 and the nonvolatile memory 78 is the same power supply Vcc as the CPU 71, etc.
through diode D and multiplexer 7
Terminal S of No. 7 is held at "H" via resistor R. Therefore, input terminals A1 to A3 become active and signals from I/O 74 are input to input terminals CK, CS, and DI of nonvolatile memory 78, and serial data from output terminal DO is input to I/O 74. , the CPU 71 is accessing the nonvolatile memory 78.

However, if an abnormality occurs in either the CPU 71 of the control board 70 equipped with the non-volatile memory 78, the memory 72, COM 73, I/O 74 of its peripheral circuits, or the main body connector 75, the control board 70 breaks down. In this case, the faulty control board 70b is removed and replaced with a new control board 70n of the same type, but if the non-volatile memory 78b on the control board 70b cannot be accessed, the stored contents will be lost. .

Since the non-volatile memory 78b itself is normal, if the non-volatile memory 78b is installed in advance through the IC socket provided on the control board 70, the non-volatile memory 78b
Although it is possible to remove b and attach it to the control board 70n,
When a nonvolatile memory is inserted into or removed from an IC socket, there is a risk that the memory contents may be destroyed by static electricity or the like, or the pins may be bent or the memory may be inserted in the wrong direction, leading to an accident in which the memory contents cannot be recovered.

[0074] Also, if only the nonvolatile memory is provided on a separate board and connected to the main body, there is no risk of such troubles or being affected by failures of other circuits on the mounted board, but in order to prevent noise, It is necessary to arrange it close to the control board equipped with the CPU to be accessed, which is difficult in terms of cost and space.

In this fourth embodiment, if the control board 70 fails, the power to the printer body is turned off, the failed control board 70b is removed, and the main body connector 75b is disconnected, as shown in FIG. Connect the auxiliary connector 76b to the auxiliary connector 86 of the control circuit 80 while keeping the connection. A new control board 7 is installed in place of the removed control board 70b.
Attach 0n.

If the power of the printer body is turned on in this state, the control boards 60, 70n, and 80 will be in the normal on state, and the multiplexer 77b and nonvolatile memory 78b of the control board 70b will be connected via the auxiliary connectors 86, 76b. The common power supply Vcc of the control board 80 is supplied to the CPU.
71b, I/O74b and other circuits have a diode Db.
acts as a backflow blocker and remains off since no power is supplied. Furthermore, since the terminal G (ground) of the nonvolatile memory 78b and the terminals G and S of the multiplexer 77b are connected to the ground of the control board 80 via the auxiliary sockets 86 and 76b, the terminal S of the multiplexer 77b is Input terminal B1 is held at “L”
~B3 becomes active, and the CPU 81 can access the nonvolatile memory 78b via the I/O 84.

When the CPU 61 is started in accordance with a program for transcribing the contents of the non-volatile memory stored in advance in the memory 62 (ROM constituting the control board 60), the main CPU 61 instructs the CPU 81 to transfer the contents of the non-volatile memory 78b. , and instructs the CPU 71n of the new control board 70n to write the content into the nonvolatile memory 78n.

When the program for transcribing the contents is finished, turn off the power to the printer body again, disconnect the auxiliary connector 76b of the failed control board 70b from the auxiliary connector 86 of the control board 80, and remove the control board 70b. , the printer continues to store and retain the contents of the initial setting values and past usage history in the non-volatile memory, and returns to a normal operating state.

FIGS. 11 and 12 are circuit diagrams showing the control board and its connections in a fifth embodiment of the laser printer according to the fourth invention, and FIG. 11 is a circuit diagram in a normal state, and FIG.
is a circuit diagram showing a connection for accessing nonvolatile memory when a failure occurs in the control board equipped with nonvolatile memory, and the same parts as in the fourth embodiment are given the same reference numerals and explained. The subscripts b and n of the reference numerals are also used in the same manner.

This fifth embodiment is similar to the fourth embodiment (FIG. 10).
While the nonvolatile memory 78b of the failed control board 70b was accessed by the CPU 81 of the other control board 80, as shown in FIG.
A new control board 90n CPU of the same type that was replaced with b.
91n, and the original function of the control board 90 on which the non-volatile memory 98 is mounted is the same as that of the control board 70 of the fourth embodiment, so a description thereof will be omitted.

The portion that accesses the nonvolatile memory 98 will be explained below. The control board 90 includes a CPU 71, a memory 72, and a COM 7 of the control board 70 (FIG. 9), respectively.
3, I/O 74, main body connector 75, non-volatile memory 7
8, CPU 91, memory 92, C similar to diode D
It is composed of an OM 93, an I/O 94, a main body connector 95, a nonvolatile memory 98, a diode D, an auxiliary connector 96, an OR circuit 97, diodes D1 to D3, and resistors R1 to R4.

In place of the multiplexer 77 in the fourth embodiment, which was a means for making the nonvolatile memory accessible by the CPU of another control board, in the fifth embodiment, the auxiliary connector 96 is used to make the nonvolatile memory accessible by the CPU of the new control board. It has become a means of making it possible.

As shown in FIG. 11, the I/O 94 on the control board 90 uses the non-volatile memory 9 when the CPU 91 is operating normally.
8, and is an I/O for accessing nonvolatile memory resistors R1 to R through diodes D1 to D3, respectively.
Control signals, designated addresses, and serial data are output to the input terminals CK, CS, and DI pulled down by 3, and the serial data from the output terminal DO is input via the OR circuit 97.

Since the other input terminal of the OR circuit 97 is grounded together with the G terminal of the nonvolatile memory 98 via the pull-down resistor R4, the output terminal D is connected to the I/O 94.
Input the O serial data as is. Further, a common power supply Vcc is supplied to the nonvolatile memory 98 through a diode D. Terminals a to d, f of the auxiliary connector 96
, g are each terminal CK, CS, DI of the nonvolatile memory 98,
They are connected to DO, G, and Vcc, respectively, and the terminal e is connected to an input terminal pulled down by a resistor R4 of an OR circuit 97.

In this fifth embodiment, if the control board 90 fails, the power to the printer body is turned off, the failed control board 90b is removed, and the main body connector 95b is disconnected, as shown in FIG. While still connected, the auxiliary connector 96b is connected via the connection cable 99 to the auxiliary connector 96n of the newly installed control board 90n in place of the removed control board 90b.

Since the auxiliary connectors 96b and 96n are male and female, it is impossible to connect them directly.The auxiliary connector 99b connected to the auxiliary connector 96b of the failed control board 90b and the auxiliary connector of the new control board 90n. A connecting cable 99 is required, which has connectors 99n connected to connectors 96n at both ends. Terminal a of connector 99b
~d, f, g are connected to the terminals a~c, e~f of the connector 99n by cables, respectively, as shown in FIG.
Terminal e of connector 99b and terminal d of connector 99n are each disconnected.

[0087] Therefore, the nonvolatile memories 78b, 78
The terminals CK, CS, DI, G, and Vcc of the new control board 90n are connected in parallel to the I/O 9 of the new control board 90n.
Serial data output from both terminals DO of the non-volatile memories 78b and 78n, which are connected to the three output terminals of the 4n, the ground, and the common power supply Vcc, is ORed by an OR circuit 97n and input to the I/O 94n. do.

[0088] If the power of the printer body is turned on in this state, the control boards 60 and 90n will be in the normal on state.
The common power supply Vcc of the control board 90n is supplied to the nonvolatile memory 98b of the control board 90b via the connection cable 99, but the CPU 91b, I/O 94b, and OR circuit 97
b Diode Db acts as a backflow blocker for other circuits, and since power is not supplied, they remain in the off state,
The CPU 91n uses the nonvolatile memory 9 via the I/O 94n.
8b and 98n can be accessed simultaneously.

When the CPU 91n is started via the main CPU 61 in accordance with a program for transcribing the contents of the non-volatile memory stored in advance in the memory 92n of the control board 90n (the ROM constituting it), first the failed control board 90b is In order to read the contents of the nonvolatile memory 98b, the CPU 91n simultaneously accesses the two nonvolatile memories 98b and 98n via the I/O 94n, and the OR circuit 97n connects each terminal D of the nonvolatile memories 98b and 98n.
I/
The CPU 91n stores the ORed data in the memory 92 (its RAM).

In this case, since the non-volatile memory 98n is new and has nothing recorded therein, the contents of the non-volatile memory 98b are stored in the memory 92 itself. Just to be sure, before connecting the connection cable 99 to the auxiliary connector 96n of the control board 90n, connect the nonvolatile memory 98
It is even better if n is cleared.

Next, the CPU 91n writes the contents of the non-volatile memory 98b stored in the memory 92 to the non-volatile memories 98b and 98n simultaneously via the I/O 94n, and then writes the initial setting value to the new non-volatile memory 98n. This means that data such as information and usage history have been transcribed. The contents of the original non-volatile memory 98b remain unchanged.

When the program for transcribing the contents is finished, turn off the power to the printer again, and then connect the connection cable 9.
9 from the auxiliary connector 96n of the control board 90n and remove the control board 90b, the printer will continue to store and retain the initial settings in the non-volatile memory, the conventional usage history, etc., and will operate normally. return to the state.

In this way, in the fifth embodiment, when the control board on which nonvolatile memory is mounted breaks down, by connecting it to a new control board of the same type via the connection cable, the old and new nonvolatile memories can be replaced. Since the circuit is accessed simultaneously and the contents are transcribed, the circuit becomes simple, and since no other control board is required, it can also be applied to a one-board case in which all elements are mounted on one board.

As explained above, in the fourth and fifth embodiments according to the fourth invention, even if the control board on which non-volatile memory is mounted breaks down, it is possible to use the normal control board without having to insert or remove the non-volatile memory. The board can be replaced safely and easily in much the same way as replacing the board. Further, although the case where a failure occurs has been described, the present invention can also be applied to a case where the control board is replaced for version upgrade.

[0095]

As explained above, according to the present invention, it is possible to speed up the operation inspection of the RAM and shorten the initial time, or to detect the occurrence or possibility of failure and to quickly respond to the problem. Alternatively, it is possible to provide an office electronic device in which the contents stored in the mounted nonvolatile memory are not lost even if a failure occurs in the control board.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing a first embodiment of a laser printer according to the first invention.

FIG. 2 is a schematic configuration diagram showing an example of an internal mechanism of a laser printer that is an embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a control system of the laser printer shown in FIG. 2;

FIG. 4 is a perspective view showing an example of a board of the controller shown in FIG. 3;

FIG. 5 is a perspective view showing an example of a CNTR (controller) board of a second embodiment according to the second invention.

FIG. 6 is a perspective view showing an example of a CNTR board of a third embodiment according to the third invention.

7 is a schematic cross-sectional view showing an example of a connector of the CNTR board shown in FIG. 6. FIG.

8 is a schematic plan view of the connector shown in FIG. 7. FIG.

FIG. 9 is a circuit diagram showing an example of the connection of a control board group in a fourth embodiment according to the fourth invention.

10 is a circuit diagram showing an example of connections of a group of control boards in case the control board mounted with the nonvolatile memory shown in FIG. 9 breaks down; FIG.

FIG. 11 is a circuit diagram showing an example of connections of a control board group in a fifth embodiment according to the fourth invention.

12 is a circuit diagram showing an example of connections of a group of control boards in case the control board mounted with the nonvolatile memory shown in FIG. 11 breaks down; FIG.

[Explanation of symbols]

1 RAM diagnostic means
2 RAM access means 3 DMA (direct memory access) means 4
Judgment means 5, 33, 43 RAM
26 DMA element (DMA means) 27a, 27b LED (approval display means) 28, 28
a, 28b LED (connection judgment means, availability display means) 31 Main CPU (RAM diagnosis means, RAM access means, judgment means, board reversal means) 34, 44, 74, 84, 94 I/O 37 CN
TR (controller) board 38a, 38b RAM
Board (memory board) 50 connector
50a,
50z Detection connector 51 Plug (connection pin)
52 Socket (connection socket) 60, 70, 80, 90 Control board
61 Main CPU 71, 81, 91 Sub CPU
76, 86 Auxiliary connector 77 Multiplexer (means for making it accessible by the CPU of another control board) 78, 98 Non-volatile memory 96 Auxiliary connector (means for making it accessible by the CPU of the new control board) CN1 to CN7 Connector

Claims (5)

[Claims] 1. An office electronic device equipped with a mounting means for mounting a removable RAM board, comprising a RAM access means for writing and reading data to and from a RAM on the mounted RAM board, and the RAM access means. a determination means for comparing the data written by the user with the data read after writing and determining whether they match or do not match; direct memory access means for direct transfer; and said RAM access means
The test data is written in the start area of M, and the test data is directly transferred sequentially from the start area to intermediate areas of the same capacity by the direct memory access means, and finally transferred to the last area. RAM diagnostic means is provided for controlling the test data to compare the data read from the last area by the determination means with the test data initially written in the start area to determine whether they match or do not match. Office electronics. 2. In an office electronic device equipped with a plurality of connectors to which removable RAM boards are respectively mounted, a board determination means for performing an operation test on the mounted RAM board to determine whether or not it is possible to perform an operation test, and the board 1. An office electronic device characterized by comprising: a propriety display means for displaying propriety or disapproval for each of the RAM boards according to a result determined by the determination means. 3. In an office electronic device equipped with a connector for attaching a removable circuit board or memory board, one of the plurality of connectors each consisting of a pair of connection pins and a connection socket constituting the connector. Both ends of the connector or at least two sets of connectors near both ends are formed as detection connectors so that the length of the connection portion thereof is shorter than that of the other connectors, and these detection connectors are connected to the circuit board or the memory. connection determining means for determining whether or not the board is connected when the board is attached; and a possibility display means for displaying whether or not the connection is possible for each circuit board or memory board according to the result determined by the connection determining means. An office electronic device characterized by being provided with. 4. The office electronic device according to claim 2 or 3, wherein the enable/disable means is provided on the circuit board, the memory board, or the RAM board, or in the vicinity of each of the connectors. Office electronics. 5. It has one or more control boards equipped with a CPU that controls the operation of the device, and at least one of the control boards stores and stores data such as initial setting values and usage history that are accessed by the CPU. In office electronic equipment equipped with non-volatile memory, if a failure occurs on the control board on which the non-volatile memory is mounted, or on the control board and other control boards, the control board on which the non-volatile memory is mounted is An auxiliary connector is provided to allow the failed control board to be connected to a new control board equipped with non-volatile memory or another control board when a failure occurs, and the failed control board is connected to the failed control board via the auxiliary connector. , a means for making the nonvolatile memory on the failed control board accessible by the CPU of the new control board or other control board when the new control board or another control board is connected; An office electronic device characterized by being installed on an on-board control board.