JPH0435000A - Mounting of chip parts on circuit board - Google Patents

Mounting of chip parts on circuit board

Info

Publication number
JPH0435000A
JPH0435000A JP2143277A JP14327790A JPH0435000A JP H0435000 A JPH0435000 A JP H0435000A JP 2143277 A JP2143277 A JP 2143277A JP 14327790 A JP14327790 A JP 14327790A JP H0435000 A JPH0435000 A JP H0435000A
Authority
JP
Japan
Prior art keywords
circuit board
chip
support
mounting
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2143277A
Other languages
Japanese (ja)
Inventor
Kiyotaka Tanaka
清隆 田中
Yuji Hirasawa
平沢　雄二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Co
Original Assignee
Minnesota Mining and Manufacturing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Minnesota Mining and Manufacturing Co filed Critical Minnesota Mining and Manufacturing Co
Priority to JP2143277A priority Critical patent/JPH0435000A/en
Priority to DE19914117145 priority patent/DE4117145A1/en
Publication of JPH0435000A publication Critical patent/JPH0435000A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/02—Feeding of components
    • H05K13/027—Fluid transport of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0173—Template for holding a PCB having mounted components thereon
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Abstract

PURPOSE: To collectively bond all chip parts at the same time with a support prepared, assigning a chip part with an electrode pad up, forming a layer of anisotropic conductive bond, bonding all chip parts to a printed circuit collectively, and separating the support from the chip part. CONSTITUTION: A bonder head 100 falls to make a circuit board 30 pressurize chip parts 22 and 24, so that electrode pads 22a and 24a are depressed in a layer 36 of anisotropic conductive bond, resulting in the deformation of a printed circuit 34 and a flexible base material 32. In addition, the layer 36 of bond cures under heat. Thereby, the chip parts 22 and 24 are electrically and mechanically bonded to the printed circuit 34 of the circuit board 30, in short, bonding is completed. Thus, attaching of the chip parts 22 and 24 to the circuit board 30, or mounting is completed, and mounting is finished, when a bonding die 12 is separated from the chip parts 22 and 24 attached to the circuit board 30.

Description

【発明の詳細な説明】 ［発明の利用分野］ 本発明は電子機器用の回路基板へチップ抵抗、チップコ
ンデンサ、ＩＣペアチップ等のチップ部品を実装する方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for mounting chip components such as a chip resistor, a chip capacitor, and an IC pair chip onto a circuit board for electronic equipment.

［従来の技術］ 従来の、はんだ付けによるチップ部品の実装方法では、
まず、回路基板にクリームはんだをスクリーン印刷して
プリント回路を形成し、次に、その上にチップ固定用接
着剤をスクリーン印刷し、この接着剤の上にチップ抵抗
、チップコンデンサ、ＩＣ（リードつきフラットパック
）等のチップ部品を載せて位置合わせ後に仮固定し、し
かる後、チップ固定用接着剤を熱硬化させて回路基板に
チップ部品を固定する。その後で、チップ部品のリード
をはんだ付けにより基板上の回路に電気的に接続する。[Conventional technology] In the conventional method of mounting chip components by soldering,
First, cream solder is screen printed on the circuit board to form a printed circuit. Next, a chip fixing adhesive is screen printed on top of that. Chip resistors, chip capacitors, and ICs (with leads) are placed on top of this adhesive. A chip component such as a flat pack is mounted and temporarily fixed after positioning, and then the chip fixing adhesive is thermally cured to fix the chip component to the circuit board. Thereafter, the leads of the chip components are electrically connected to the circuits on the board by soldering.

上述の従来技術の方法においては、電気的接続ははんだ
付けに依存するため、回路基板の材料としてははんだ付
けが行われる高温度に耐え得る高値なもの（例えばポリ
イミド）が必要とされた。In the prior art methods described above, electrical connections relied on soldering, which required high-value circuit board materials (eg, polyimide) that could withstand the high temperatures at which soldering was performed.

上述の従来技術は、その後、電子機器の薄形軽量化およ
び低価格化を達成するために改良され、この改良された
チップ実装方法ではペアチップが採用され、また、クリ
ームはんだを用いた回路のスクリーン印刷の代わりに、
異方導電性接着剤のフィルムを基板にラミネート（積層
）することが行われる。このラミネート法によればはん
だ付けを行う必要がないので、基板の基材として高価な
耐熱性材料を用いる必要がなく、比較的安価で、薄く、
従ってフレキシブルな、例えばポリエステルフィルムを
用いることが可能である。また、スクリーン印刷と仮固
定用接着剤とが不要であるので、組み立てラインの設備
費、組み立て時間、所要エネルギー等の低減が達成され
る。The above-mentioned conventional technology has since been improved to make electronic devices thinner, lighter, and cheaper.This improved chip mounting method employs paired chips, and also uses cream solder to screen circuits. Instead of printing,
A film of anisotropically conductive adhesive is laminated onto a substrate. This lamination method does not require soldering, so there is no need to use expensive heat-resistant materials as the base material for the board, and it is relatively inexpensive, thin, and
It is therefore possible to use flexible, for example polyester films. Furthermore, since screen printing and temporary fixing adhesives are not required, assembly line equipment costs, assembly time, energy requirements, etc. can be reduced.

［発明が解決しよ゛うとする問題点］ しかしながら、上記の改良された技術のおいても、フレ
キシブルな回路基板上の異方導電性接着剤のフィルム層
に種々のチップ部品を載せてこれらを１つずつ所定の位
置に位置決めして仮固定する工程は欠かせない。この位
置決めは、実際の組み立てラインにおいては、高価で複
雑な光学装置を用いた位置決め装置により行われるので
、組み立てラインの建造に多額の費用がかかり、結果的
に、かかる組み立てラインで組み立てられた電子機器の
価格に影響を与える。という問題がある。[Problems to be Solved by the Invention] However, even with the above-mentioned improved technology, various chip components are mounted on a film layer of anisotropic conductive adhesive on a flexible circuit board. The process of locating and temporarily fixing each piece in a predetermined position is essential. In an actual assembly line, this positioning is performed by a positioning device that uses expensive and complicated optical equipment, so the construction of the assembly line costs a lot of money, and as a result, the electronics assembled on the assembly line Affect the price of equipment. There is a problem.

また、位置決めと仮固定はチップ部品１個ごとに行われ
るので、全部のチップ部品の位置決めと仮固定に多大の
時間がかかり、しかも、仮固定の後に本固定とも言うべ
きボンディング工程が必要さされるという問題もある。In addition, since positioning and temporary fixing are performed for each chip component, it takes a lot of time to position and temporarily fix all chip components, and furthermore, a bonding process, which can be called final fixing, is required after temporary fixing. There is also the problem.

従って、本発明は上述の改良された方法をさらに改良し
て、チップ部品の位置決めを光学装置を用いないで行い
、しかも、位置決めされた総てのチップ部品を回路基板
に対して一括して同時にボンディングするチップ実装方
法を提供することを目的とする。Therefore, the present invention further improves the above-described improved method to position the chip components without using an optical device, and to simultaneously position all the positioned chip components with respect to the circuit board at the same time. The purpose of this invention is to provide a chip mounting method using bonding.

［問題点を解決する手段］ 本発に従うチップ部品実装方法は、所要の電子機器用の
回路基板におけるチップ部品の位置に対応する位置に該
チップ部品の大きさと実質上同じ大きさのチップ位置決
め用の凹みを形成された表面を有する支持体を準備する
段階と、該支持体の前記凹みに所定のチップ部品をその
電極パッドを上にして配置する段階と、前記電子機器用
の回路基板の表面に異方導電性接着剤の層を形成する段
階と、前記支持体上の前記チップ部品に前記異方導電性
接着剤層が対向するように前記支持体と回路基板とを重
ね合わせかつ両者を所定の関係位置に位置決めして総べ
てのチップ部品をプリント回路に対して一括してボンデ
ィングする段階と、しかる後、前記支持体をチップ部品
から分離する段階とを有し、前記の各段階は逐次行われ
る。[Means for Solving the Problems] The chip component mounting method according to the present invention includes a chip positioning device having a size substantially the same as that of the chip component at a position corresponding to the position of the chip component on a circuit board for a desired electronic device. preparing a support having a surface formed with a recess; placing a predetermined chip component in the recess of the support with its electrode pad facing upward; and a surface of the circuit board for electronic equipment. forming a layer of an anisotropically conductive adhesive on the support; overlapping the support and the circuit board so that the anisotropically conductive adhesive layer faces the chip component on the support; the steps of positioning and bonding all the chip components to the printed circuit in a predetermined relationship, and then separating the support from the chip components; are performed sequentially.

［発明の作用と効果］ 本発明によれば、支持体の所定の凹みに所定のチップ部
品を配置することと、支持体と回路基板とを重ね合わせ
かつ両者を所定の関係位置に位置決めすることによって
、チップ部品の電極パッドがプリント回路の所定の部位
に正確に位置決めされる。この位置決めは光学的な位置
決め装置を必要とせず、機械的な位置決め手段で達成可
能である。従って、組み立てラインの建造費用が安くな
り、それだけ製品たる電子部品の価格を安く出来る。ま
た、従来の技術ではチップ部品を１個ずつ位置決めして
ボンディングしていたので、チップ部品の実装に１個に
つき約１５秒かかつていたが、本発明では上記のように
機械的に簡単に位置決めされたチップ部品を回路基板に
対して全部同時にボンディング出来るので、チップ部品
の実装に要する時間が大幅に短縮される。[Operations and Effects of the Invention] According to the present invention, a predetermined chip component is placed in a predetermined recess of a support, and the support and the circuit board are overlapped and positioned in a predetermined relative position. This allows the electrode pads of the chip component to be accurately positioned at predetermined locations on the printed circuit. This positioning does not require an optical positioning device and can be achieved by mechanical positioning means. Therefore, the construction cost of the assembly line is reduced, and the price of the electronic components that are the products can be reduced accordingly. In addition, in the conventional technology, chip components were positioned and bonded one by one, so it took about 15 seconds for each chip component to be mounted, but with the present invention, positioning can be easily performed mechanically as described above. Since all the chip components can be bonded to the circuit board at the same time, the time required for mounting the chip components can be greatly reduced.

［実施例］ 以下、添付図面を参照して本発明の詳細な説明する。[Example] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

第１図は電子機器の組み立てラインにおいて回路基板へ
チップ部品をボンディングにより固定するボンディング
ステーションの主要部を示す拡大断面図である。このボ
ンディングステーションには熱圧着ボンダーヘッド１０
０が設けられている。FIG. 1 is an enlarged cross-sectional view showing the main parts of a bonding station that fixes chip components to a circuit board by bonding in an electronic device assembly line. This bonding station has 10 thermocompression bonder heads.
0 is set.

このボンディングステーションを通って、図示しないタ
ーンテーブルまたはコンベアが間欠的に移動する。図示
したボンダーヘッド１００及び図示しないターンテーブ
ルまたはコンベアは当業者に周知であるので、ここでは
説明を省略する。A turntable or conveyor (not shown) moves intermittently through this bonding station. The illustrated bonder head 100 and the unillustrated turntable or conveyor are well known to those skilled in the art and will not be described here.

第１図に示す実施例においては、ボンディング用金型１
２からなる支持体が前記ターンテーブルまたはコンベア
上に載せられて運ばれる。ボンディング用金型１２の上
表面１４には複数のチップ位置決め用の凹み１６．１８
が形成されている。In the embodiment shown in FIG.
A support consisting of two parts is carried on the turntable or conveyor. The upper surface 14 of the bonding mold 12 has a plurality of recesses 16 and 18 for chip positioning.
is formed.

表面１４におけるこれらの凹み１６．１８の位置は所要
の、すなわち、製造しようとする電子機器の回路基板に
おけるチップ部品の位置に対応しており、また、凹み１
６．１８の形状と大きさは前記所要の電子機器における
チップ部品の形状と大きさに実質上等しい。The position of these recesses 16,18 in the surface 14 corresponds to the required, i.e. the position of the chip component in the circuit board of the electronic device to be manufactured;
The shape and size of 6.18 are substantially equal to the shape and size of the chip component in the required electronic device.

第１図に示すボンディングステーションよりも上流のス
テーションにおいて、前記所要の電子機器の所定のチッ
プ部品のペアチップ２２．２４がそれらの電極パッド２
２　ａ、　　２４　ａを上にして前記凹み１６．１８内
に配置される。第１図は、図示しないターンテーブルま
たはコンベアによって、金型１２がこれらのペアチップ
２２．２４とともにボンディングステーションまで運ば
れて来た状態を示している。At a station upstream from the bonding station shown in FIG.
2 a, 24 a are placed in said recess 16.18 with their a side up. FIG. 1 shows the mold 12 and the paired chips 22, 24 being conveyed to the bonding station by a turntable or conveyor (not shown).

第１図は、また、前記所要の電子機器用のプリント回路
基板３０が前記ボンディングステーションの前記ボンダ
ーヘッド１００の真下に運ばれて来た状態を示している
。回路基板３０は基材３２とその一表面に設けられたプ
リント回路３４とを有しており、このプリント回路３４
の上には異方導電性接着剤の層３６が設けられている。FIG. 1 also shows the state in which the printed circuit board 30 for the required electronic device has been transported directly below the bonder head 100 of the bonding station. The circuit board 30 has a base material 32 and a printed circuit 34 provided on one surface thereof.
A layer 36 of anisotropically conductive adhesive is provided over the .

この接着剤の層３６は第１図に示すボンディングステー
ションよりも上流の位置で、当業者に周知の異方導電性
接着剤のフィルムをプリント回路３４の上に積層するこ
とにより設けられたものであり、回路基板３０はその上
の接着剤の層３６が下向きになるようにしてボンディン
グステーションに運ばれる。回路基板３０の基材３２は
その両側縁に、例えば写真フィルムにおけるような駒送
り小孔を形成されている連続した帯状のフレキシブルシ
ートまたはフィルムからなることが好ましい。This layer of adhesive 36 is provided upstream of the bonding station shown in FIG. 1 by laminating a film of anisotropically conductive adhesive, well known to those skilled in the art, over the printed circuit 34. The circuit board 30 is then transported to the bonding station with the layer of adhesive 36 thereon facing downward. The base material 32 of the circuit board 30 is preferably made of a continuous band-shaped flexible sheet or film having small frame feed holes, such as those in photographic film, formed on both side edges thereof.

ボンディングステーションにおいては、チップ部品２２
．２４を載せたボンディング金型からなる支持体１２が
その上のチップ部品２２．２４がボンダーヘッド１００
の下方の所定の位置に位置するように位置決めされる。At the bonding station, the chip component 22
．． A support body 12 consisting of a bonding mold on which a chip component 22 and a chip component 24 are placed are attached to a bonder head 100.
is positioned at a predetermined position below.

この位置決めは、支持体１２を搬送するターンテーブル
又はコンベア上の所定の位置に支持体１２を位置決めし
た状態でターンテーブルまたはコンベアを運転してボン
ディングステーションにて周知の手段で停止させるのみ
でよい。このようにターンテーブルまたはコンベアを停
止させれば、ボンディング金型上のチップ部品もそれぞ
れ所定の位置で停止する。This positioning can be accomplished by simply positioning the support 12 at a predetermined position on the turntable or conveyor that transports the support 12, driving the turntable or conveyor, and stopping the turntable or conveyor at the bonding station using known means. When the turntable or conveyor is stopped in this way, the chip components on the bonding mold are also stopped at their respective predetermined positions.

一方、プリント回路基板３０は基材３２の両側縁におけ
る駒送り小孔に送り用のスプロケットホイールの爪を噛
み合わせて回路基板３０をボンディングステーションへ
送り、このボンディングステーションにおいて支持体１
２に対し所定の関係位置となった時に送りを停止するよ
うに位置決めする。この位置決めは写真フィルムの駒送
りの要領で一駒（１個のプリント回路基板３０の大きさ
）ずつ送ることにより達成される。すなわち、回路基板
３２の送りが停止した時にはこの回路基板３０上のプリ
ント回路３４の所定の部位が第１図に示すようにチップ
部品２２及び２４の電極バッド２２ａ及び２４ａに対し
て所定の位置関係になるようにターンテーブル又はコン
ベアと基材３２の送り装置とが予め設計されている。On the other hand, the printed circuit board 30 is sent to a bonding station by meshing the feed sprocket wheel pawls with small feed holes on both sides of the base material 32, and at this bonding station, the support
Positioning is performed so that feeding is stopped when a predetermined relative position is reached with respect to No. 2. This positioning is accomplished by feeding the frame one frame at a time (the size of one printed circuit board 30) in the same way as photographic film frames are fed. That is, when the feeding of the circuit board 32 is stopped, a predetermined portion of the printed circuit 34 on the circuit board 30 is in a predetermined positional relationship with respect to the electrode pads 22a and 24a of the chip components 22 and 24, as shown in FIG. The turntable or conveyor and the feeding device for the substrate 32 are designed in advance so that

回路基板３０のプリント回路３４が支持体１２上のチッ
プ部品２２及び２４に対して上述のように位置決めされ
た後、ボンダーヘッド１００が下降して回路基板３０を
チップ部品２２及び２４に対して周知の態様で押圧する
とともに約１５０℃にて約３０秒間加熱する。この押圧
によりチップ部品２２．２４の電極パッド２２ａ、２４
ａは第２図に示すように異方導電性接着剤の層３６に押
し込まれてプリント回路３４及びフレキシブル基材３２
を図示のように変形させる。また、接着剤の層３６は熱
により硬化する。このようにして、チップ部品２２及び
２４は回路基板３０のプリント回路３４に対して電気的
にも機械的にも結合される、すなわち、ボンディングが
完了する。よって、回路基板３０へのチップ部品２２．
２４の取り付け、すなわち実装が完了したので、回路基
板３０に取り付けられたチップ部品２２．２４からボン
ディング金型１２を分離して実装を終了する。After the printed circuits 34 of the circuit board 30 are positioned as described above with respect to the chip components 22 and 24 on the support 12, the bonder head 100 is lowered to familiarize the circuit board 30 with respect to the chip components 22 and 24. While pressing in this manner, it is heated at about 150° C. for about 30 seconds. This pressing causes the electrode pads 22a, 24 of the chip components 22.24 to
As shown in FIG.
Transform as shown. The adhesive layer 36 is also cured by heat. In this way, the chip components 22 and 24 are electrically and mechanically coupled to the printed circuit 34 of the circuit board 30, ie, the bonding is completed. Therefore, the chip components 22. to the circuit board 30.
24, that is, the mounting has been completed, the bonding mold 12 is separated from the chip components 22 and 24 attached to the circuit board 30, and the mounting is completed.

第１図に示す実施例においてはチップ位置決め用の凹み
１６及び１８がボンディング金型１２に形成されている
が、第３図に示す実施例においてはチップ位置決め用の
凹み１６Ａおよび１８Ａがチップキャリヤー１２Ａの一
表面に形成されている。チップキャリヤー１２Ａはプラ
スチックからなる連続した帯状体であり、これはロール
からコンベア１１０上へ引き出される。チップ部品２２
゜２４をチップキャリヤー１２Ａの凹み１６Ａ、１８Ａ
に配置する作業を組み立てライン上でボンディングステ
ーションの上流の位置で行っても良いし、この作業をチ
ップ部品のメーカーに依頼しても良い。後者の場合は、
所要の電子機器用の個々の回路基板に実装される所定の
チップ部品２２゜２４がチップキャリヤー１２Ａにおけ
る所定の凹み１６Ａ、１８Ａに配置された状態で、チッ
プキャリヤーがロールの形態でセットメーカーに供給さ
れる。いずれの場合でも、チップキャリヤーは連続した
帯状であるので、その両側縁に、前記回路基板３０の基
材３２の場合と同様に、駒送り用の小孔を設けておくこ
とにより、チップキャリヤー１２Ａをスプロケットホイ
ールで間欠的に送ることが出来る。この送りを帯状フィ
ルムからなる回路基板の基材３２の送りと同期させてお
き、かつ、基材３２の先端と帯状のチップキャリヤー１
２Ａの先端とがローディングステーションにおいて一致
するように調整しておくことにより、チップキャリヤー
１２Ａと回路基板の基材３２の送り及びプリント回路３
４に対するチップ部材２２゜２４のボンディングを自動
操作にて行うことが可能である。In the embodiment shown in FIG. 1, recesses 16 and 18 for chip positioning are formed in the bonding mold 12, but in the embodiment shown in FIG. It is formed on one surface of. Chip carrier 12A is a continuous strip of plastic that is drawn from a roll onto conveyor 110. Chip parts 22
゜24 into the recesses 16A and 18A of the chip carrier 12A
The work of arranging the chips may be performed at a position upstream of the bonding station on the assembly line, or this work may be outsourced to the chip component manufacturer. In the latter case,
The chip carrier is supplied to a set manufacturer in the form of a roll, with predetermined chip components 22 and 24 to be mounted on individual circuit boards for a desired electronic device placed in predetermined recesses 16A and 18A in the chip carrier 12A. be done. In either case, since the chip carrier is in the form of a continuous band, small holes for feeding the chip are provided on both sides of the chip carrier 12A, as in the case of the base material 32 of the circuit board 30. can be sent intermittently using a sprocket wheel. This feeding is synchronized with the feeding of the base material 32 of the circuit board made of a strip-shaped film, and the tip of the base material 32 and the strip-shaped chip carrier 1 are
By adjusting the tips of the chip carriers 12A and 2A to coincide with each other at the loading station, the feeding of the chip carrier 12A and the substrate 32 of the circuit board and the printed circuit 3
It is possible to bond the chip members 22 and 24 to each other automatically.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はボンディングステーションにおいて本発明の一
実施例により互いに位置決めされたプリント回路基板と
チップ部品とを示す拡大断面図、第２図はボンディング
により互いに結合されたプリント回路基板とチップ部品
とを示す拡大断面図、 第３図は本発明の他の実施例に従いコンベア上のチップ
キャリヤーに載せられたチップ部品を示す拡大断面図で
ある。 １２・・・ボンディング金型（支持体）、１２Ａ・・・
チップキャリヤー（支持体）、１６．１８，１６Ａ、１
８Ａ・・・チップ部品位置決め用の凹み、 ２２．２４・・・チップ部品、 ２２ａ、２４ａ・・・電極パッド、 ３０・・・プリント回路基板、 ３２・・・基材、 ３４・・・プリント回路、 ３６・・・異方導電性接着剤の層、 １００・・・ボンダーヘッド、 １１０・・・コンベア。FIG. 1 is an enlarged cross-sectional view showing a printed circuit board and a chip component positioned with respect to each other in accordance with an embodiment of the present invention at a bonding station, and FIG. 2 shows a printed circuit board and a chip component bonded together by bonding. Enlarged Cross-Sectional View FIG. 3 is an enlarged cross-sectional view showing chip components mounted on a chip carrier on a conveyor in accordance with another embodiment of the present invention. 12... Bonding mold (support body), 12A...
Chip carrier (support), 16.18, 16A, 1
8A... Recess for chip component positioning, 22.24... Chip component, 22a, 24a... Electrode pad, 30... Printed circuit board, 32... Base material, 34... Printed circuit , 36... layer of anisotropic conductive adhesive, 100... bonder head, 110... conveyor.

Claims (5)

【特許請求の範囲】[Claims] （１）所要の電子機器用の回路基板におけるチップ部品
の位置に対応する位置に該チップ部品の大きさと実質上
同じ大きさのチップ位置決め用の凹みを形成された表面
を有する支持体を準備する段階と、 該支持体の前記凹みに所定のチップ部品をその電極パッ
ドを上にして配置する段階と、 前記電子機器用の回路基板の表面に異方導電性接着剤の
層を形成する段階と、 前記支持体上の前記チップ部品に前記異方導電性接着剤
層が対向するように前記支持体と回路基板とを重ね合わ
せかつ両者を所定の関係位置に位置決めして総てのチッ
プ部品をプリント回路に対して一括してボンデイングす
る段階と、 しかる後、前記支持体をチップ部品から分離させる段階
と、 を有し、 前記の各段階を逐次行う、回路基板へのチップ部品の実
装方法。(1) Prepare a support having a surface formed with a chip positioning recess of substantially the same size as the chip component at a position corresponding to the position of the chip component on a circuit board for a desired electronic device. placing a predetermined chip component in the recess of the support with its electrode pad facing upward; and forming a layer of anisotropically conductive adhesive on the surface of the circuit board for electronic equipment. , overlapping the support and the circuit board so that the anisotropically conductive adhesive layer faces the chip components on the support, and positioning both in a predetermined relationship position to remove all the chip components. A method for mounting chip components on a circuit board, comprising: bonding the printed circuit all at once; and then separating the support from the chip components, and performing each of the above steps sequentially. （２）前記支持体がボンデイング用金型である請求項１
に記載の回路基板へのチップ部品の実装方法。(2) Claim 1, wherein the support is a bonding mold.
A method for mounting chip components on a circuit board as described in . （３）前記支持体がプラスチックからなるシート状のチ
ップキャリヤーである請求項１に記載の回路基板へのチ
ップ部品の実装方法。(3) The method for mounting chip components on a circuit board according to claim 1, wherein the support body is a sheet-like chip carrier made of plastic. （４）前記回路基板の基材がフレキシブルである請求項
１から３までのいずれか１つに記載の回路基板へのチッ
プ部品の実装方法。(4) The method for mounting chip components on a circuit board according to any one of claims 1 to 3, wherein the base material of the circuit board is flexible. （５）前記ボンデイングする段階が熱圧着ボンダーによ
り行われる請求項１から４までのいずれか１つに記載の
回路基板へのチップ部品の実装方法。(5) The method for mounting chip components on a circuit board according to any one of claims 1 to 4, wherein the bonding step is performed using a thermocompression bonder.
JP2143277A 1990-05-31 1990-05-31 Mounting of chip parts on circuit board Pending JPH0435000A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2143277A JPH0435000A (en) 1990-05-31 1990-05-31 Mounting of chip parts on circuit board
DE19914117145 DE4117145A1 (en) 1990-05-31 1991-05-25 Chip mounting method on substrate - by heating adhesive layer to receiver chips from carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2143277A JPH0435000A (en) 1990-05-31 1990-05-31 Mounting of chip parts on circuit board

Publications (1)

Publication Number Publication Date
JPH0435000A true JPH0435000A (en) 1992-02-05

Family

ID=15335000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2143277A Pending JPH0435000A (en) 1990-05-31 1990-05-31 Mounting of chip parts on circuit board

Country Status (2)

Country Link
JP (1) JPH0435000A (en)
DE (1) DE4117145A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330712A (en) * 1995-06-01 1996-12-13 Teikoku Tsushin Kogyo Co Ltd Method of fitting electronic chip part to substrate
JP2012119459A (en) * 2010-11-30 2012-06-21 Kyocera Kinseki Corp Element component mounting device
KR20160009691A (en) * 2013-05-20 2016-01-26 코닌클리케 필립스 엔.브이. Chip scale light emitting device package with dome
CN107889344A (en) * 2012-08-15 2018-04-06 深圳迈辽技术转移中心有限公司 Flexible circuit board device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010146524A1 (en) * 2009-06-19 2010-12-23 Koninklijke Philips Electronics N.V. Conformable electronic devices and methods for their manufacture
AT520857A1 (en) * 2018-02-08 2019-08-15 Friedrich Eibensteiner Dr Method for placing and soldering elements on component carriers

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330712A (en) * 1995-06-01 1996-12-13 Teikoku Tsushin Kogyo Co Ltd Method of fitting electronic chip part to substrate
JP2012119459A (en) * 2010-11-30 2012-06-21 Kyocera Kinseki Corp Element component mounting device
CN107889344A (en) * 2012-08-15 2018-04-06 深圳迈辽技术转移中心有限公司 Flexible circuit board device
KR20160009691A (en) * 2013-05-20 2016-01-26 코닌클리케 필립스 엔.브이. Chip scale light emitting device package with dome
JP2016521011A (en) * 2013-05-20 2016-07-14 コーニンクレッカ フィリップス エヌ ヴェＫｏｎｉｎｋｌｉｊｋｅ Ｐｈｉｌｉｐｓ Ｎ．Ｖ． Chip scale light emitting device package with dome
KR20200029519A (en) * 2013-05-20 2020-03-18 루미리즈 홀딩 비.브이. Chip scale light emitting device package with dome
US11145794B2 (en) 2013-05-20 2021-10-12 Lumileds Llc Chip scale light emitting device package with dome

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