JPH04335578A - Nonvolatile semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase a coupling capacitance between a control gate and a floating gate and to make a write speed high. CONSTITUTION:In a nonvolatile semiconductor device, by a trench-type element isolation structure, which can reduce the size of a unit cell, a floating gate 4 is formed on the surface of a semiconductor device 1, and a trench 6 is formed in a self-aligned manner. A control gate 5 is formed in a direction nearly perpendicular to the floating gate 4 on an insulator 7 which has been buried deeper than the surface of the floating gate 4 in the trench 6; a coupling capacitance between the control gate 5 and the floating gate 4 is increased by a portion where the control gate 5 faces the side face of the floating gate 4.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor device and a method for manufacturing the same, and more particularly to a nonvolatile semiconductor device typified by an EPROM having a trench type memory cell structure and a method for manufacturing the same.

0002

2. Description of the Related Art Erasable PROM (EPM), which has a floating gate and a control gate, is a type of non-volatile semiconductor device.
ROM is known. In this EPROM, in order to reduce the unit cell size, a trench type memory cell structure in which a floating gate is formed by self-alignment with a trench for element isolation has been reported ( NIKKEI MICROD
EVICES January 1990 issue P104).

0003

[Problem to be solved by the invention] By the way, EPROM
In order to increase the writing speed, it is necessary to increase the electric field applied between the floating gate and the substrate. When a voltage is applied to the control gate, the voltage between this floating gate and the substrate is the voltage between the control gate and the floating gate and between the floating gate and the floating gate.
Determined by the capacitive coupling ratio between the substrates. That is, as the coupling capacitance between the control gate and the floating gate is increased, the electric field between the floating gate and the substrate becomes larger, and high-speed writing becomes possible.

Among EPROMs, an EPROM having a structure in which element isolation is achieved by a LOCOS structure in which an element isolation region 3 made of a thick oxide film is formed outside a gate insulating film 2 on the surface of a semiconductor substrate 1 is shown in FIG. By extending the floating gate 4 to above the element isolation region 3,
The coupling capacitance between the control gate 5 and the floating gate 4 is increased to increase the writing speed. However, the E
In PROM, although it is possible to increase the coupling capacitance between the control gate 5 and the floating gate 4, this is disadvantageous in reducing the unit cell size.

On the other hand, as shown in FIG. 5, in a structure in which a floating gate 4 is formed in self-alignment with a trench 6 for element isolation, and an insulator 7 is buried in this trench 6 to achieve element isolation, the unit Although a reduction in cell size can be expected, since the area of the floating gate 4 facing the control gate 5 is reduced, there is a drawback that the coupling capacitance between the control gate 5 and the floating gate 4 is reduced.

Therefore, the present invention aims to increase the coupling capacitance between the control gate and the floating gate in a trench-type memory cell structure that allows for a reduction in unit cell size, and provides a non-volatile memory cell structure that enables faster write speeds. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same.

[0007]

[Means for Solving the Problems] A nonvolatile semiconductor device according to the present invention includes a first conductive film formed in a stripe shape on a semiconductor substrate with a first insulating film interposed therebetween, and a space between the first conductive film. a groove formed on the surface side of the semiconductor substrate; an insulator buried in the groove deeper than the upper surface of the first conductive film; and a second insulating film on the first conductive film and the insulator. a second conductive film formed in a stripe shape in a direction substantially perpendicular to the first conductive film through the conductive film, the first conductive film serving as a floating gate, and the second conductive film serving as a control gate; It becomes.

In the method for manufacturing a nonvolatile semiconductor device according to the present invention, a first conductive film is formed in a stripe shape on a semiconductor substrate via a first insulating film, and self-alignment is performed using the first conductive film as a mask. First, the first insulating film and the semiconductor substrate are etched to form a groove, an insulating material is buried in this trench, this insulating material is etched back deeper than the top surface of the first conductive film, and then the first insulating film and the semiconductor substrate are etched. A second conductive film is formed in a stripe shape on the conductive film and the insulator in a direction substantially perpendicular to the first conductive film with a second insulating film interposed therebetween.

[0009]

[Operation] In the non-volatile semiconductor device according to the present invention, an insulator is buried deeper than the upper surface of the floating gate in a groove (trench) formed by self-alignment with the floating gate (first conductive film) on the surface side of the semiconductor substrate. By forming a control gate (second conductive film) on the floating gate in a direction substantially perpendicular to the floating gate,
The coupling capacitance between the control gate and the floating gate can be increased by the amount that the control gate faces the side surface of the floating gate.

0010

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional structural diagram showing an embodiment of an EPROM having a trench type element isolation structure according to the present invention. In the figure, silicon dioxide (Si) is deposited on the semiconductor substrate 1.
A floating gate 4 is self-aligned with a trench 6 for forming an element isolation region by a striped conductive film made of a first layer of polysilicon via a gate insulating film 2 made of O2 or the like. target)
is formed.

For example, the semiconductor substrate 1 is placed in this trench 6.
A silicon dioxide SiO2-based insulator 7 is buried deeper than the surface of the substrate to provide element isolation. A floating gate 4 is formed on the floating gate 4 and the insulator 6 via a gate insulating film 8 made of silicon dioxide SiO2 or the like.
A control gate 5 made of a second layer of polysilicon is formed in a stripe shape as a word line in a direction substantially perpendicular to the gate line. Further, on the control gate 5, an Al wiring 10 is arranged as a bit line with an insulating layer 9 interposed therebetween.

Next, a method for manufacturing an EPROM having such a structure will be explained based on the process diagrams shown in FIGS. 2(A) to 2(D). First, as shown in FIG. 2A, a gate insulating film 2 made of silicon dioxide, SiO2, etc. is formed on a semiconductor substrate 1, and a first layer of polysilicon is grown on top of the gate insulating film 2, which is formed into stripes. The floating gate 4 is formed by etching (floating gate forming step).

Next, as shown in FIG. 2B, using the floating gate 4 as a mask, the gate insulating film 2 and the semiconductor substrate 1 are continuously etched to form a trench 6 in a self-aligned manner. A silicon dioxide SiO2-based insulator 7 is buried in the trench 6 (element isolation region forming step). Next, as shown in FIG. 2, the insulator 7 buried in the trench 6 is etched back by overetching to a position deeper than the upper surface of the semiconductor substrate 1, for example (etchback step). During this etchback, anisotropic etching is preferably used so that the gate insulating film 2 between the floating gate 4 and the substrate 1 can be left as is since it is not etched laterally.

After etching back the insulator 7, a gate insulating film 8 made of silicon dioxide SiO2 or the like is formed on the floating gate 4 and the insulator 7, as shown in FIG. The control gate 5 is formed by growing a layer of polysilicon and etching it into stripes parallel to the direction substantially perpendicular to the floating gate 4 (control gate forming step).

As mentioned above, the floating gate 4
In an EPROM having a control gate 5 and a control gate 5,
A trench 6 is formed by self-alignment using the floating gate 4 as a mask, an insulator 7 is buried in the trench 6, and the insulator 7 is retreated before forming the control gate 5. Since the floating gates 4 face each other not only on their top surfaces but also on their side surfaces, the coupling capacitance between the control gates 5 and the floating gates 4 can be increased by the opposing area of the side surfaces.

As an example, as shown in FIG. 3, when the width W and length L of the floating gate 4 are both 0.5 μm and the film thickness t is 0.2 μm, the area S1 of the upper surface of the floating gate 4 is: S1 = 0.5 x 0.5 = 0.25 [μm2], and the area S2 of the side surface of the floating gate 4 is S2
=0.2×0.5=0.10 [μm2].

Therefore, in FIG. 3, in the case of the conventional structure (A), the opposing area between the control gate 5 and the floating gate 4 is S1 itself, whereas in the case of the structure of the present embodiment (B ), S1 +2S
It becomes 2. As a result, according to the present invention, the opposing area between the control gate 5 and the floating gate 4 is 80% since 2S2 /S1 = 0.2/0.25 = 0.8 compared to the conventional example. % can be increased. As a result, the coupling capacitance between the control gate 5 and the floating gate 4 can be increased by 80%.

In the above embodiment, in the etch-back process shown in FIG. 2B, the insulator 7 buried in the trench 6 was etched back to a position deeper than the top surface of the semiconductor substrate 1, but this is preferable. This is just one example, and the invention is not limited to this. In short, it is sufficient to etch back deeper than the upper surface of the control gate 5 to form a region where the control gate 5 can face the side surface of the floating gate 4. .

[0019]

[Effects of the Invention] As explained above, according to the present invention,
In a non-volatile semiconductor device with a trench-type element isolation structure that can reduce the unit size, a trench is formed on the front side of the semiconductor substrate and is buried on an insulator buried deeper than the top surface of the floating gate. By forming the control gate in this direction, the coupling capacitance between the control gate and the floating gate can be increased by the area of the control gate facing the side surface of the floating gate, thereby increasing the writing speed.

[Brief explanation of the drawing]

FIG. 1: EPR of trench-type element isolation structure according to the present invention
FIG. 2 is a cross-sectional structural diagram showing an example of OM.

FIG. 2 is a process diagram showing each step of the manufacturing method according to the present invention, (A) is a floating gate forming step, (B)
(C) is an etch-back process,
(D) shows the control gate forming process.

FIG. 3 is a schematic perspective view showing the opposing areas of a floating gate and a control gate, in which (A) shows a conventional structure and (B) shows a structure according to the present invention.

FIG. 4 is a cross-sectional structural diagram of an EPROM with element isolation having a LOCOS structure.

FIG. 5 is a cross-sectional structural diagram showing a conventional example of an EPROM having a trench type element isolation structure.

[Explanation of symbols]

1 Semiconductor substrate 4 Floating gate 5 Control gate 6 Trench (groove) 7 Insulator

Claims (2)

[Claims] 1. A first conductive film formed in a stripe shape on a semiconductor substrate with a first insulating film interposed therebetween; and a groove formed on the surface side of the semiconductor substrate between the first conductive films. ,
an insulator buried in the groove deeper than the top surface of the first conductive film; and a second insulator buried on the first conductive film and the insulator.
a second conductive film formed in a stripe shape in a direction substantially orthogonal to the first conductive film through an insulating film, the first conductive film serving as a floating gate, and the second conductive film serving as a floating gate; A nonvolatile semiconductor device characterized by using a film as a control gate. 2. A first conductive film is formed in a stripe shape on a semiconductor substrate with a first insulating film interposed therebetween, and the first insulating film and the first conductive film are formed in a self-aligned manner using the first conductive film as a mask. A semiconductor substrate is etched to form a groove, an insulator is buried in the groove, the insulator buried in the groove is etched back deeper than the upper surface of the first conductive film, and then the first conductive film is etched back. A second layer is formed on the conductive film and the insulator.
A method for manufacturing a nonvolatile semiconductor device, comprising forming a second conductive film in a stripe shape in a direction substantially perpendicular to the first conductive film through an insulating film.