JPH04333246A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH04333246A
JPH04333246A JP10275891A JP10275891A JPH04333246A JP H04333246 A JPH04333246 A JP H04333246A JP 10275891 A JP10275891 A JP 10275891A JP 10275891 A JP10275891 A JP 10275891A JP H04333246 A JPH04333246 A JP H04333246A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
integrated circuit
circuit
current source
minimum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10275891A
Other languages
Japanese (ja)
Inventor
Retsu Yamakawa
Jiyosei Ou
Yukichi Shoji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FUAJII SYST KENKYUSHO
Original Assignee
FUAJII SYST KENKYUSHO
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by FUAJII SYST KENKYUSHO filed Critical FUAJII SYST KENKYUSHO
Priority to JP10275891A priority Critical patent/JPH04333246A/en
Publication of JPH04333246A publication Critical patent/JPH04333246A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make possible the parallel connection of a plurality of minimum and maximum operation integrated circuits in order to widen the limit of the number of input terminals and to suppress the consumption power of a current source in a semiconductor integrated circuit to do a fuzzy operation, such as the minimum value or the maximum value of an input signal or a combination of the minimum and maximum values.
CONSTITUTION: In a semiconductor integrated circuit 3 provided with a built-in current source 2, the circuit 3 is a semiconductor integrated circuit of a constitution wherein the current source and a circuit 1, which is supplied with a current from the current source, are each connected to independent external terminals 8 and 9 without being connected with each other in the interior of the circuit 3.
COPYRIGHT: (C)1992,JPO&Japio
JP10275891A 1991-05-08 1991-05-08 Semiconductor integrated circuit Pending JPH04333246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10275891A JPH04333246A (en) 1991-05-08 1991-05-08 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10275891A JPH04333246A (en) 1991-05-08 1991-05-08 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH04333246A true JPH04333246A (en) 1992-11-20

Family

ID=14336102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10275891A Pending JPH04333246A (en) 1991-05-08 1991-05-08 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH04333246A (en)

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