JPH04328521A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To use formed picture elements is a picture element group in an effective display area by holding the picture elements even in the uppermost and lowermost rows in an excellent display state as well as picture elements in other rows. CONSTITUTION:The picture elements are arrayed in matrix and additional capacity means 10 and 11 are formed for each of the picture elements. In this liquid crystal display device, the additional capacity means 10 and 14 for each of the picture elements in the uppermost row in picture element groups in respective rows have larger capacity values than additional capacity values of other picture elements and are made equal in resistance value to other picture elements, and the additional capacity means for each of the picture elements in the lowermost row are equalized in capacity value and resistance value to other picture elements.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a liquid crystal display device.
In particular, the present invention relates to a liquid crystal display device in which the pixel groups arranged in the top and bottom rows of the pixel groups arranged in a matrix are improved.

0002

2. Description of the Related Art In a liquid crystal display device in which pixels are arranged in a matrix as described above, since the pattern of each pixel can be the same, all the pixels are formed in the same pattern, and each pixel in charge of a group of pixels in the column direction is Connect the video drive signal to the drain line,
A vertical scanning signal is input to each gate line in charge of a group of pixels in the row direction.

Among the pixel groups arranged in a matrix, the display conditions of the pixel groups arranged in the top and bottom rows are better than those in other rows due to penetration of static electricity, etc. For this reason, the pixel groups in the top row and the bottom row are set in a display-disabled state using, for example, black matrix technology so that neither of them becomes a pixel group within the effective display area.

[0004] A liquid crystal display device having such a configuration is described, for example, in “Applied Physics Letter 45, No. 10, 1021, 1984 (Appl.
ied Physics Letter, T. J. S
cheffer, J. Nehring: “A ne
w, highly multiplexable l
known as "IQUID CRYSTAL DISPLAY").

[0005]

[Problem to be Solved by the Invention] However, in recent years, there has been a demand for an increase in the number of pixels, and for this reason, it is necessary to form a large number of pixel rows in advance, and then make it impossible to display the groups of pixels in the top and bottom rows. Things like making it a state began to be done.

However, it goes without saying that it is preferable that all the formed pixels be within the effective display area.
The present invention has been made from this viewpoint.

[0007] Therefore, the present invention has been made in view of the above circumstances, and its object is to ensure that even if the formed pixels are in the top and bottom rows, they do not interfere with pixels in other rows. It is an object of the present invention to provide a liquid crystal display device which has a good display state like a pixel group and can be used as a pixel group within an effective display area.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention basically provides a liquid crystal display in which pixels are arranged in a matrix and an additional capacitance means is formed for each pixel. In a display device, the additional capacitance means for each pixel in the top row of the pixel group in each row has a capacitance value larger than the additional capacitance value in other pixels, and a resistance value equal to the resistance value in other pixels. The additional capacitance means of each pixel in the bottom row has the same capacitance value and resistance value as the capacitance value and resistance value of the other pixels.

[0009]

[Operation] In the liquid crystal display device configured in this way, if the capacitance and resistance values of each gate line of the pixel group in the top row and the pixel group in the bottom row are made the same as those of the pixel groups in other rows, then , display unevenness is eliminated.

However, regarding the pixel group in the top row, the TFT in the pixel group in the second row is
Since there is a special situation in which there is a jump in the source voltage of the type MOS transistor, the capacitance value of the additional capacitance means is configured to be larger than that of the pixel groups in other rows to reduce the jump amount.

[0011] In this way, display unevenness is eliminated in each pixel group from the top row to the bottom row, and each pixel group in the top row and each pixel group in the bottom row can be used as the display area. Become.

0012

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention. In particular, the pixels arranged in the top row and the second row among the pixels arranged in a matrix form are shown in FIG. FIG.

The pattern is formed on the liquid crystal side surface of one of the two glass substrates arranged with the liquid crystal interposed therebetween.

In the figure, a common gate line 2 is formed below the pixel group arranged in the second row, running in the row direction. The pixel group in the second row is located between the gate line 2 and the common gate line 1 in the pixel groups arranged in the top row, and each pixel area in the pixel group in the second row are defined by drain lines 4, which will be described later.

A TFT is provided on the gate line 2 for each pixel.
A MOS transistor 5 of the same type is formed, and a part of the gate line 2 is directly connected to the gate electrode 2 of the MOS transistor 5.
It is configured as A.

Note that the MOS transistor 5 is composed of two transistors arranged in parallel, so that there is no problem even if one of them does not operate.

The MOS transistor 5 has a semiconductor layer 7 formed on the upper surface of the gate electrode (part of the gate line),
A source electrode 8 and a drain electrode 9 are formed at both ends of this semiconductor layer 7 (in the figure, the upper side and the lower side, respectively).

Here, the drain electrode 9 constitutes a part of the drain line 4.

There is a transparent pixel electrode 10 connected to the source electrode 8, and this transparent pixel electrode 10 is formed over almost the entire area of the pixel formation area.

Further, an additional capacitance forming electrode 11 is formed in the lower layer of the upper region of the transparent pixel electrode 10 in the figure with a dielectric film interposed therebetween. This additional capacitance forming electrode 11 is
This additional capacitance forming electrode 11 and the overlapping portion of the transparent pixel electrode 10 constitute an additional capacitance means, which has a U-shape with protrusions along both sides of the pixel forming area, and It is connected to the gate electrode 1 in the pixel group in the top row.

The above-mentioned additional capacitor means has a so-called midpoint potential (
This is provided to reduce the influence of gate potential changes on the pixel electrode potential (pixel electrode potential) and to store video information for a long time after the MOS transistor is turned off.

Furthermore, the pixel group on the top row has almost the same configuration as the pixel group on the second row described above, but there is a gate electrode 13 on the top of which a common voltage is applied.
In addition, an additional capacitance forming electrode 14 having a shape different from that of the additional capacitance forming electrode 11 is formed in each pixel region.

First, the additional capacitance forming electrode 14 is constructed so that the overlapping area with the transparent pixel electrode 10 is larger than that of the additional capacitance forming electrode 11.
The capacitance value of the additional capacitance means consisting of is increasing.

Specifically, in FIG. 1, the superimposition width l11 of the pixel group in the top row in the vertical direction in the drawing is larger (4 μm) compared to the superimposition width l12 in the vertical direction in the drawing of the pixel group in the second row. degree).

The overall resistance value of the gate line 13 connecting the additional capacitance forming electrode 14 is configured to be equal to the overall resistance value of the gate line 2 in the second row pixel group.

Specifically, in FIG. 1, the overlapping widths l21, l22, l2 of the pixel group in the top row in the vertical direction in the figure are
It is set by setting 3 to an appropriate value.

Next, as described above, the additional capacitance means of each pixel in the top row is set so that its capacitance value is larger than the additional capacitance value in other pixels, and its resistance value is the same as the resistance value in other pixels. The reason why display unevenness is eliminated by having the same configuration will be explained.

First, in FIG. 2, (a) is a diagram showing changes in the source voltage of the source electrode 8 of the MOS transistor 5 connected to the gate line 1 in the top row of pixels.

In the figure, the gate voltage 20 causes the MO
The S transistor 5 turns on, and the drain signal 22
appears as the source signal 23.

On the other hand, FIG. 2(b) is a diagram showing changes in the source voltage of the source electrode 8 of the MOS transistor 5 connected to the gate line 2 in the second row of pixels.

At this time, the MOS transistor 5 is turned on by the gate voltage 21, but the pulse 10 from the gate line 1 (the gate line in the top row of pixels) is transmitted from the additional capacitance forming electrode 14 to the source signal. The jump portion 24 is added to this source signal 23 via an additional capacitance means.
will be added.

The amount of this jump can be roughly expressed by the following equation, Equation 1.

[0033]

[Math 1]

Because of this jump, the value that minimizes the effective value of the source voltage (indicated by 25 in the figure) is shifted upward in the figure compared to the case where there is no jump. .

[0035] Here, this shift amount can be expressed by the following equation (2).

[0036]

[Math 2]

[0037] For example, specifically, Cadd=1
．． 67pF, Cgs=0.15pF, Cpx=0.3p
In the case of F, ΔT=64μS, T=15mS, and Vg=25V, the shift amount is 0.08V.

[0038] Since such a shift does not exist at all in the pixel group of the top row, this causes display unevenness.

For this reason, it is only necessary to correct the drop in the source voltage waveform caused by the fall of the gate voltage by the shift amount 26 and 27.

[0040] Here, this amount of drop can be approximately expressed by the following equation (3).

[0041]

[Math 3]

From this, by increasing the value of Cadd, the amount of the drop decreases. By making the difference between the dips 27 and 26 equal to Equation 2 above, the voltages 28 and 25 can be matched. That is,

[0043]

[Math 4]

It is sufficient if the following holds true.

Here, Cadd1 is the additional capacitance in the pixel group in the top row, and Cadd is the additional capacitance in the pixel groups in the other rows.

For example, using the above values, Ca
dd=1.67pF, Cadd1=1.77pF. That is, it is sufficient to increase the additional capacitance in the top row pixel group by about 0.1 pF.

Assuming that the intervening insulating film has ε=6.7 and a film thickness of 0.35 μm, the opposing electrodes are approximately 590 μm2.
This will increase the overlap.

It should be noted that the gate line 13 is configured so that the overall resistance value of the gate line 13 connecting the additional capacitance forming electrode 14 is equal to the overall resistance value of the gate line 2 in the second row pixel group. This is to make the delay time of the source signal propagated through the additional capacitance means the same as that of the other sources.

FIG. 3 shows a configuration showing a pattern of pixels arranged in the bottom row and one row above the bottom row (hereinafter referred to as the second bottom row) among the pixels arranged in a matrix. It is a diagram.

Note that this pattern is formed on the same glass substrate on which the pattern of FIG. 1 is formed.

The pixel group in the bottom row and the pixel group in the second bottom row have the same structure, but the structure of the gate electrode 30 in the pixel group in the bottom row is different from that of the other gate electrodes. . That is, the other gate electrodes are formed by connecting U-shaped additional capacitance forming electrodes having protrusions for each pixel forming region, but in the gate electrode 30, as described above, No additional capacitance forming electrode is formed, and only an electrode 32 formed in the shape of a gate line with a larger width is provided.

Therefore, it does not have a U-shape with a protrusion, and there is no transparent pixel electrode arranged in an overlapping manner.

[0053] The electrode 32 is thereby connected to the gate line 30.
The resistance values of all the gate lines are made to be the same as those of other gate lines. The resistance value of the electrode 32 can be set by the widths l31 and l32 in the vertical direction in the figure.

Further, as shown in FIG. 4, the capacitance value of the gate line 30 is ensured by capacitance means newly provided at both ends of the gate line 30, and is made equal to the capacitance value of the other gate lines.

It should be noted that a common voltage is applied to the capacitor means from the bonding pad 42 via the capacitor 41.

FIG. 5 shows a plan view of an embodiment in which the capacitor means is formed on a glass substrate. In the figure, the gate line 30 is drawn out to a pad 32 via a lead 31. On the other hand, there is a pad 33 for applying a common voltage, and this pad 33 is led out through a lead 34 to a pad 35 arranged to overlap with the pad 32.

A laminated body of an insulating layer 36 and a semiconductor layer 37 is interposed between the pad 32 and the pad 35.

Note that FIG. 6 shows a cross-sectional view taken along the line II in FIG. 5.

In the figure, reference numeral 38 indicates the TFT type MOS
These are the source/drain layers of the transistor, and 39 is a passivation film.

The capacitor means having such a structure can be formed in the same process as the TFT type MOS transistor.

FIG. 7 is a graph illustrating the effects of providing the capacitance means. As is clear from the figure, the capacitance of the gate line in the bottom row, which is not provided with the capacitance means, is smaller than the capacitance 71 of the gate line in the row above it, as indicated by 70 in the figure. However, it can be seen that by providing the capacitive means, the value approaches 71 as shown at 72 in the figure.

According to the embodiment described above, if the capacitance and resistance values of each gate line of the pixel group in the top row and the pixel group in the bottom row are made the same as those of the pixel groups in other rows, as a general rule, Display unevenness is eliminated.

However, regarding the pixel group in the top row, the TFT in the pixel group in the second row is
Since there is a special situation in which there is a jump in the source voltage of the type MOS transistor, the capacitance value of the additional capacitance means is configured to be larger than that of the pixel groups in other rows to reduce the jump amount.

By doing this, display unevenness is eliminated in each pixel group from the top row to the bottom row, and each pixel group in the top row and each pixel group in the bottom row can be used as the display area. Become.

[0065]

[Effect of the invention] As is clear from the above explanation,
According to the present invention, even if the formed pixels are in the top row and the bottom row, the display state is as good as that of the pixel groups in other rows, and the pixels can be used as a pixel group within the effective display area. .

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a liquid crystal display device according to the present invention, and particularly shows a pattern of pixels arranged in the top row and second row among pixels arranged in a matrix. FIG.

FIGS. 2A and 2B are explanatory diagrams showing the reason for increasing the additional capacitance value in the top row pixel group.

FIG. 3 is a configuration diagram showing an embodiment of a liquid crystal display device according to the present invention, and in particular, a pattern of pixels arranged in the bottom row and the first row above the bottom row of pixels arranged in a matrix. FIG.

FIG. 4 is an explanatory diagram showing that capacitor means is provided in the bottom row.

FIG. 5 is a plan view showing an example of a pattern in which the capacitor means is formed on a glass substrate.

FIG. 6 is a cross-sectional view taken along line II in FIG. 5;

FIG. 7 is a graph showing that the capacitance of the gate line in the bottom row can be formed to be approximately equal to that of the other gate lines.

[Explanation of symbols]

1, 2, 30 Gate line 10 Transparent pixel electrode 11, 14
Additional capacitance forming electrode 32 Electrode 41 Capacitance

Claims (1)

[Claims] Claim 1: In a liquid crystal display device in which pixels are arranged in a matrix and additional capacitance means is formed for each pixel, the additional capacitance means of each pixel in the top row of the pixel group in each row is defined by its capacitance. The value is larger than the additional capacitance value in other pixels, and the resistance value is the same as the resistance value in other pixels, and the additional capacitance means of each pixel in the bottom row is configured to A liquid crystal display device characterized in that the capacitance and resistance values of other pixels are configured to be the same.