JPH04323867A - Semiconductor nonvolatile memory and its writing method - Google Patents

Abstract

PURPOSE:To prevent malfunctions by forming of a memory transistor, a read bit line, a resistor connected between the bit line and a word line and a write bit line. CONSTITUTION:A power source voltage in which a potential difference between a drain 11 and a source 12 connected through a resistor 21 and a write bit line 16 to a terminal 20 becomes a drain withstand voltage or higher of a memory transistor 10, is supplied to the terminal 20, and a breakdown current flows between the drain 11 and the source 12 of the transistor 10. As a result, the drain 11, a gate 13 and the source 12 are electrically short-circuited thereamong thereby to write information. When a potential of a word line 17 is set to the power source voltage, a leakage current flows from the transistor 10 of a writing state to the source 12 through the gate 13, the potential is dropped via a resistor 18, a potential lower than 1/2 of the power source voltage is output from a read bit line 15 to read information. Thus, erroneous writing and erroneous reading can be prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only semiconductor nonvolatile memory that can be written only once, and a writing method therefor.

0002

[Background Art] In semiconductor integrated circuits, yields are improved by using memory elements that can be written only once to correct manufacturing variations in transistor threshold voltages and to store changes in operating conditions. , performance has been stabilized.

[0003] As memory elements that can be written only once, there are various types of PROM (Programmable Memory) such as laser fuse blowing type, electric fuse blowing type, and junction destruction type.
The main example is eRead Only Memory).

0004

However, the laser fuse blowing type PROM requires a dedicated device for laser generation in order to write information. Furthermore, it is necessary to open the passivation film on the fuse to form a laser entrance window, which increases the cost. Moreover, writing information after mounting has the disadvantage that the mounting form is limited.

Electrical fuse blowing type PROM physically destroys polysilicon etc., so it does not generate silicon waste or
There are problems such as deterioration of the passivation film.

[0006] Junction destruction type PROM requires a large current to write information. For this reason, the voltage applied during writing is large, and in order to prevent write current from leaking, the semiconductor element needs to have a withstand voltage higher than the write voltage. This has the disadvantage that the manufacturing process of semiconductor nonvolatile memory becomes complicated.

[0007] Electrical fuse blowing type PROMs and junction destruction type PROMs are characterized by applying a high voltage to the memory element and thermally destroying the part on which most of the voltage is applied in the path through which a large current flows through the memory element. In order to write information, the size of the resistance that can be inserted between the memory element and the write voltage terminal is limited. Therefore, even if a protection element is connected to the write voltage terminal in parallel with the memory element in order to prevent erroneous writing due to electrostatic noise, the effect is small, so there is a drawback that it cannot be used as a PROM for adjusting characteristics after mounting. .

Therefore, an object of the present invention is to provide a method that does not cause generation of silicon waste or deterioration of the passivation film, does not require high breakdown voltage of peripheral elements, has a simple manufacturing process, and allows information to be written only once even after mounting. non-volatile memory,
The present invention provides a writing method.

[0009]

Means for Solving the Problems In order to achieve the above object, a semiconductor nonvolatile memory of the present invention employs the structure and writing method described below.

A memory transistor, a read bit line connected to the gate of the memory transistor, a resistor connected between the read bit line and the word line, and a write resistor connected to either the source or drain of the memory transistor. The bit lines constitute a memory cell.

The memory transistor structure constituting the memory cell is a MOS structure, MIS structure, MNOS structure, MO
It consists of at least one NOS structure.

[0012] The resistance constituting the memory cell is a diffused resistance,
It consists of at least one polysilicon resistor.

Writing is performed by applying a high negative or positive voltage as a write voltage to either the source or drain of the memory transistor.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a part of the circuit of a memory cell which is an embodiment of the semiconductor nonvolatile memory of the present invention.

As shown in FIG. 1, an n-channel MOS transistor (hereinafter referred to as a memory transistor) 10, which is a memory element, has a drain 11, a source 12,
It is composed of a gate 13 and a substrate 14. The gate 13 is connected to the read bit line 15, the drain 11 is connected to the write bit line 16, and the source 12 and substrate 14 are grounded. Read bit line 15 is connected to word line 17 via first resistor 18 . Furthermore, when writing information to the memory transistor 10, a terminal 20 is provided to supply a high external write voltage (hereinafter referred to as Vpp), and this terminal 20 is connected to the write bit line 16 via a second resistor 21. Terminal 20
is grounded via diode 22.

The operation of the semiconductor nonvolatile memory configured as described above will be explained below. Information is written by setting the potential of the gate 13 to a power supply voltage (hereinafter referred to as Vdd). Furthermore, the potential difference Vds between the drain 11 and the source 12 connected to the terminal 20 via the second resistor 21 and the write bit line 16 is the same as that of the memory transistor 10.
Vpp that exceeds the drain breakdown voltage of terminal 2 is applied from an external power supply.
0, causing a breakdown current to flow between the drain 11 and source 12 of the memory transistor 10. Due to dielectric breakdown induced by this breakdown current, drain 11 and gate 1
Information is written by electrically shorting at least one of between the transistor 3 and the source 12, between the drain 11 and the gate 13, or between the source 12 and the gate 13.

Next, the information read operation will be explained. The explanation of the read operation is as follows: "1" indicates a state where the potential of the read bit line 15 is higher than 1/2 of Vdd, and "1" indicates a state where the potential is lower than Vdd.
0" for explanation. Reading out stored information is
When the potential of the word line 17 is set to Vdd, a leakage current flows from the memory transistor 10 in the write state to the source 12 via the gate 13, and the potential drops due to the first resistor 18, and "0" is read from the bit line 15. is output from. On the other hand, since no potential drop occurs from the memory transistor in the non-written state, "1" is read out as information.

FIG. 2 is a partial cross-sectional view showing a memory transistor in an embodiment of the present invention. A cross-sectional view of the memory transistor 10 in FIG. 1 before writing is shown in FIG. 2(a), and a cross-sectional view after writing is shown in FIG. 2(b). Figure 2(a)
A method for manufacturing a memory transistor using the following will be briefly described. A field oxide film 31 is formed on a p-type silicon substrate 30 by selective oxidation. After that, gate oxide film 3
After growing 2, polysilicon is deposited, and a gate 33 is formed by photo-etching. Next, an n-type impurity having a conductivity type opposite to that of the silicon substrate 30 is implanted and annealing is performed to form a drain 34 and a source 35, which are high concentration n-type diffusion layers. After that, an interlayer insulating film 36 is deposited, and then this interlayer insulating film 3 is etched using a photo-etching technique.
After forming an opening in 6, an aluminum wiring 37 is formed. Figure 2 (
In b), the parts designated by the same reference numerals as those in FIG.

When the information explained using FIG. 1 is written into the memory transistor 10, an aluminum layer 40 is formed as shown in FIG. 2(b). As a result, at least one of the drain 34, the gate 33, and the source 35, the drain 34 and the gate 33, or the source 35 and the gate 33 are connected via the aluminum layer 40, and electrically connected. Short circuit. The mechanism by which the aluminum layer 40 is formed will be explained as follows.

When writing information, the memory transistor is supplied with a voltage higher than its drain breakdown voltage, so the junction between the drain 34 and the p-type silicon substrate 30 breaks down, causing an excessive current to flow. Furthermore, since most of the voltage is applied to the thin junction interface, heat loss at the junction is large, and the temperature of a part of the non-uniform junction rises rapidly due to thermal runaway, leading to junction breakdown. Due to this bond failure,
Since most of the voltage is applied to the channel portion below the gate 33, heat loss in the channel portion increases and the temperature rises.

Due to the temperature rise between the drain 34 and the source 35 of this series of memory transistors, first the aluminum wiring 37 on the drain 34 and then the gate of the phosphorous-doped silicon oxide film used as the interlayer insulating film 36 The contact surface between the oxide film 32 and the gate 33 is melted. Then, due to the high electric field applied between the drain 34 and the gate 33 and between the drain 34 and the source 35, the melted aluminum wiring 37 is deposited along the electric field in the melted part of the interlayer insulating film 36, forming an aluminum layer 40. do.

Next, FIG. 3 shows an example of the relationship between the write voltage Vpp and the write time in the memory cell of the circuit shown in FIG. As the memory transistor 10, the impurity concentration of the p-type silicon substrate is 1.9×10 16 atoms.
/cm3, drain and source impurity concentration 1.2
×1020atoms/cm3, gate oxide film thickness 30
The resistance value of the second resistor 21 is 5 nm, the gate length is 2 μm, and the gate width is 10 μm.
0Ω is used. In FIG. 3, a curve 50 indicates the writing time (hereinafter referred to as dielectric breakdown time) until the aluminum layer 40 shown in FIG. It shows the writing time until the bond between the substrates 30 breaks down (hereinafter referred to as bond breakdown time).

As shown in FIG. 3, the curves 50 and 51 are almost the same until Vpp is 18V, and the difference in writing time is not clear. This is due to the slow absolute write time. However, when Vpp is higher than 18V, the write time becomes about 10-6 seconds, and curve 5
The difference between 0 and curve 51 becomes clear. Further, the slope of the dielectric breakdown time is gentler than the slope of the junction breakdown time with respect to Vpp, and the higher Vpp is, the larger the difference between the junction breakdown time and the dielectric breakdown time becomes. In other words, in order to write information, a Vpp pulse of 1 μs or more is required, and instantaneous pulses such as electrostatic noise, which are high voltage but have a limited amount of charge, can only cause junction breakdown. happens,
This will not lead to dielectric breakdown. As is clear from Figure 1,
Even if the drain 11 is grounded through the substrate 14 due to junction breakdown, there is no path for leakage current to flow, and the memory transistor is maintained in a non-written state. Moreover, by setting the breakdown voltage of the diode 22 shown in FIG. 1 to a voltage lower than the intrinsic breakdown voltage of the gate oxide film, it is possible to prevent the occurrence of intrinsic breakdown of the gate oxide film. Therefore, erroneous writing due to electrostatic noise does not occur.

[0024] As a memory transistor, a p-channel MOS transistor, MIS transistor, MNOS
It is clear that transistors or MONOS transistors can also be used as a memory in the same way. Furthermore, the resistors constituting the memory cells are composed of diffused resistors or polysilicon resistors. Furthermore, by increasing the channel length of the memory transistor, it is possible to selectively create an electrical short-circuit between the drain and the gate.

[0025]

As is clear from the above description, according to the present invention, there is no generation of silicon debris or deterioration of the passivation film. Therefore, characteristic deterioration of the semiconductor element does not occur. Furthermore, there is no need to increase the voltage resistance of peripheral semiconductor elements. In addition, erroneous writing due to electrostatic noise does not occur, so
Writing after implementation is possible. Furthermore, the structure is exactly the same as a normal MOS transistor, making it possible to obtain a writable nonvolatile memory, and if applied to semiconductor integrated circuits made of MOS transistors, there will be no increase in manufacturing costs, which has a very large effect. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a semiconductor nonvolatile memory in an embodiment of the present invention.

FIG. 2 shows cross-sectional views of a memory transistor in an embodiment of the present invention, with FIG. 2(a) showing a cross-sectional view before writing information, and FIG. 2(b) showing a cross-sectional view after writing information.

FIG. 3 is a graph showing an example of writing information in the semiconductor nonvolatile memory of the present invention, and showing a relationship between write voltage and write time.

[Explanation of symbols]

10 Memory transistor 11 Drain 12 Sauce 13 Gate 14 Board 15 Read bit line 16 Write bit line 17 Word line 18 First resistance

Claims (4)

[Claims] 1. A memory transistor, a read bit line connected to a gate of the memory transistor, a resistor connected between the read bit line and a word line, and one of a source and a drain of the memory transistor. A semiconductor nonvolatile memory characterized in that a memory cell is configured by a connected write bit line. 2. The semiconductor nonvolatile memory according to claim 1, wherein the structure of the memory transistor constituting the memory cell is at least one of a MOS structure, an MIS structure, an MNOS structure, and a MONOS structure. 3. The semiconductor nonvolatile memory according to claim 1, wherein the resistor constituting the memory cell comprises at least one of a diffused resistor and a polysilicon resistor. 4. A semiconductor nonvolatile memory write method, characterized in that writing is performed by applying a high negative or positive voltage as a write voltage to either the source or drain of a memory transistor.