JPH04320527A - Central arithmetic processing unit - Google Patents

Abstract

PURPOSE:To conduct a rate test of hardware in a CPU by conducting the rate test of the hardware, which is specified by reading a microinstruction out, according to timing control data read out of respective addresses of the memory together with the microinstruction. CONSTITUTION:The timing control data are provided in the respective addresses of the memory 1C which is built in the CPU 1 and stores microinstructions. Hardware 1D which currently operates is specified by reading the microinstruction out and the rate test of the hardware 1D is conducted by controlling the clock generation period of a clock generator 2 according to the timing control data read out together with the microinstruction. Thus, operation timing can be controlled in microinstruction units and the rate test is conducted in the microinstruction units. Consequently, the rate test of the hardware 1D in the CPU 1 can be conducted and the hardware 1D with small timing tolerance can be specified (self-diagnosed).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a central processing unit that can be used in computers or other equipment.

0002

2. Description of the Related Art A central processing unit is generally called a CPU or the like and is known as a device that operates at the center of a computer or the like. Figure 3 shows a conventional central processing unit (CPU).
This figure shows the general structure of the system. In the figure, 1 indicates the entire CPU. The CPU 1 is composed of a controller 1A, a microsequencer 1B, a memory 1C, and a hardware group 1D.

Microinstructions and microsequence control instructions are stored in the memory 1C, and microinstructions and microsequence control instructions at arbitrary addresses are read out by address signals given from the microsequencer 1B. The microsequence control command is input to the microsequencer 1B. Under the control of the controller 1A, the microsequencer 1B calculates the address from which the next microinstruction should be read based on the inputted microsequence control command read from the memory 1C, and provides the calculated address to the memory 1C. Read the next microinstruction and microsequence control instruction. The microinstructions read from the memory are given to the hardware group 1D and the controller 1A, and the controller 1A and the hardware group 1D are controlled. The hardware group 1D is composed of registers, counters, adders, etc., and a program is executed by the hardware group 1D operating according to microinstructions.

2 indicates a clock generator. The CPU 1 operates at a predetermined timing cycle using the clock output from the clock generator 2.

[0005]

[Problems to be Solved by the Invention] CPUs are generally integrated into ICs. However, the special purpose CPUs are controller 1A, micro sequencer 1B, and memory 1.
C. The hardware group 1D may be composed of individual ICs, and the whole may constitute a CPU. In such cases, in addition to testing whether each part operates normally according to the microinstructions during the initial adjustment, it is also possible to test whether each part operates at a faster timing than the normal operation timing, which is called a rate test. It must also be tested to see if it works.

[0006] Furthermore, when a failure occurs during actual operation, in order to recover from the failure, for example, the IC constituting the hardware group 1D is
If the hardware is replaced, it is necessary to test whether this hardware operates normally after the replacement, and also to perform a rate test. In such cases, conventional methods have been to generate a high-speed clock by switching the clock generation rate of the clock generator 2, or to connect an external variable-rate clock generator and generate a high-speed clock from this variable-rate clock generator. , to test whether it operates normally with this high-speed clock. If a malfunction occurs in this rate test, it is not possible to identify in which part of the hardware the malfunction has occurred, so if a malfunction occurs in the rate test, it will be necessary to replace the entire hardware group 1D. It is uneconomical to deal with this.

[0007] In addition, in the case of a prototype test for converting the CPU 1 into an IC, if a defect occurs in the prototype CPU during a rate test, if the part of the hardware that has become inoperable can be identified, it is possible to improve the circuit of that part. This allows for efficient development. An object of the present invention is to propose a CPU having a self-diagnosis function that can identify the part of the hardware in which the defect occurs when a defect occurs in a rate test.

[0008]

[Means for solving the problem] In this invention, the memory 1C
A bit is provided at each address in which timing control data defining a timing period is written, and the clock generation period of the clock generator is controlled by the timing control data written to this bit during a rate test.

Therefore, according to the present invention, when performing a rate test, microinstructions and timing control data can be read out as a pair. Therefore, the operation timing can be controlled for each microinstruction, and a rate test can be performed for each microinstruction block. As a result, it is possible to specify the hardware operated by the microinstruction block and perform a rate test.

0010

[Embodiment] FIG. 1 shows an embodiment of the present invention. In the figure, 1 is the CPU, 1A is the controller, 1B is the sequencer, 1C
1D indicates a memory that stores microinstructions, and 1D indicates a hardware group that operates based on the microinstructions. In this invention, the memory 1C is provided with timing control data in addition to microinstructions and sequence control instructions. These micro-instructions, sequence control instructions, and timing control data are as shown in FIG. It can be allocated to microsequence control instructions, and the lower two bits can be allocated to timing control data.

The sequence control command and timing control data are input to the sequencer 1B to control the sequencer 1B, and the timing control data is input to the clock generator 2.
, and controls the clock generation rate of the clock generator 2. If we allocate 2 bits to timing control data, the 2 bits of data will be "00" and "01".
, "10", and "11" can be performed. For example, "00" is the normal rate, "01" is the first high speed rate, "10" is the second high speed rate, and "11" is the third high speed rate. In addition to the normal rate, three types of high speed rates can be set. can do.

[0012] By combining these three types of high-speed rates, microinstructions, and microsequence control instructions, each piece of hardware can be specified and a high-speed rate test can be performed. That is, a certain piece of hardware in the hardware group 1D is specified by a microinstruction and a sequence control instruction, and the specified hardware is operated in accordance with timing control data. At this time, if the hardware operates normally at each high speed rate, it can be determined that the hardware can operate at all high speed rates.

[0013] Therefore, when hardware is detected to be inoperable through a high-speed rate test, it is possible to take measures such as replacing only that part or changing the circuit structure of that hardware part. Note that the reference numeral 3 shown in FIG. 1 indicates a mode switch. By setting the mode switch 3 to the rate test mode, a rate test can be performed. When the normal mode is set, the clock generator 2 is not controlled by timing control data.

Furthermore, in the above description, a case has been described in which timing control data is written to memory 1C that stores microinstructions, but timing control data can be written to other memories as long as they can be read out in synchronization with memory 1C. You can also write .

[0015]

[Effects of the Invention] As explained above, according to the present invention, it is possible to individually rate test the hardware in the CPU, and it is possible to identify defective hardware by the rate test. It is possible to take measures such as replacing only the parts or changing the circuit structure, which has the advantage that the adjustment time can be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining one embodiment of the present invention.

FIG. 2 is a diagram for explaining essential parts of the invention.

FIG. 3 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

1 CPU 1A Controller 1B Micro sequencer 1C Memory 1D Hardware group 2 Clock generator 3 Mode switch

Claims (1)

[Claims] 1. A microsequencer, a memory accessed by an address signal outputted from the microsequencer to read microinstructions, and an operation controlled by the microinstructions read from the memory, the microsequencer's memory being controlled by the microinstructions read from the memory; In a central processing unit configured by a controller that controls operations and a clock generator that provides a timing clock that defines the operation timing of this controller. A writing area for timing control data is provided at each address of the memory, and the timing control data written in this writing area controls changing the clock generation period of the clock generator. A central processing unit configured to self-diagnose the timing tolerance of each piece of hardware within the processing unit.