JPH04320325A - Semiconductor manufacturing device - Google Patents

Semiconductor manufacturing device

Info

Publication number
JPH04320325A
JPH04320325A JP8813391A JP8813391A JPH04320325A JP H04320325 A JPH04320325 A JP H04320325A JP 8813391 A JP8813391 A JP 8813391A JP 8813391 A JP8813391 A JP 8813391A JP H04320325 A JPH04320325 A JP H04320325A
Authority
JP
Japan
Prior art keywords
film
wafer
conductor
potential
controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8813391A
Other languages
Japanese (ja)
Inventor
Koichi Tsuzuki
浩一 都築
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8813391A priority Critical patent/JPH04320325A/en
Publication of JPH04320325A publication Critical patent/JPH04320325A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable contamination due to dust and dirt to be reduced and a process to be stabilized by controlling a potential on a surface of a formed film by a device for forming a conductive thin film of a semiconductor manufacturing device. CONSTITUTION:A conductor for controlling surface potential 12 is installed close to a wafer 11 which is installed within a film-formation device 1 and the formed conductive film 11-3 connects the wafer 11 and the conductor for controlling surface potential 12, thus enabling a surface potential of the formed film 11-3 to be controlled through the conductor for controlling surface potential 12. Since magnetization of wafer surface due to a process can be prevented, adhesion of dust and dirt can be reduced and the potential on a surface of a wafer can be controlled arbitrarily, thus enabling plasma state to be controlled finely and the process to be stabilized.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体製造プロセスのう
ち、CVDやスパッタ等の成膜プロセスで、プロセス装
置内部での、形成膜表面電位を制御することで、基板周
囲の静電気を制御して、プロセスの安定性を向上させる
とともに、微粒子が静電気によって基板上に付着するこ
とを防ぐ半導体製造装置に関する。
[Industrial Application Field] The present invention controls static electricity around a substrate by controlling the surface potential of the formed film inside the process equipment in a film forming process such as CVD or sputtering in the semiconductor manufacturing process. , relates to a semiconductor manufacturing apparatus that improves process stability and prevents fine particles from adhering to a substrate due to static electricity.

【0002】0002

【従来の技術】従来の成膜プロセス装置では、形成する
膜の表面電位を制御することは行われていない。従来で
も、ウエハの保持装置を通じてウエハを任意の電位に保
とうとする工夫は実施されることがあるが、保持装置が
ウエハに接している部分と、形成膜間には必ずしも導通
があるわけではない。すなわち、ウエハの上には、不導
体の膜が形成されていることも多く、そのような不導体
膜形成後は、いくらウエハの下地面に保持装置を接触さ
せても、間に存在する不導体膜のために、これから形成
する膜表面の電位は制御できない。
2. Description of the Related Art Conventional film forming process apparatuses do not control the surface potential of the film being formed. In the past, attempts have been made to maintain the wafer at a desired potential through a wafer holding device, but there is not necessarily electrical conduction between the part where the holding device is in contact with the wafer and the formed film. . In other words, a nonconductor film is often formed on the wafer, and after such a nonconductor film is formed, no matter how much the holding device is brought into contact with the underlying surface of the wafer, the nonconductor existing in between will be removed. Since the film is a conductor, the potential on the surface of the film to be formed cannot be controlled.

【0003】ところが、形成膜表面の電位が制御できな
いと、プロセスが原因で形成膜表面が帯電してしまうこ
とがある。例えば、多くの膜形成は、低圧雰囲気でプラ
ズマを利用して行われるが、プラズマによって表面が帯
電し、しかも、形成膜と下地の間には不導体膜が存在す
るので、形成膜の表面がそれによる電位を持つことがあ
る。このような形成膜の帯電によって、次のような不都
合が生じる。
However, if the potential on the surface of the formed film cannot be controlled, the surface of the formed film may become charged due to the process. For example, most film formation is performed using plasma in a low-pressure atmosphere, but the plasma charges the surface, and since there is a nonconducting film between the formed film and the base, the surface of the formed film is It may have a potential due to this. Such charging of the formed film causes the following disadvantages.

【0004】まず、塵埃汚染の増大である。装置内部の
壁面には、反応生成物が付着している。そのような反応
生成物がさまざまな力で壁面から離脱するとフレークと
呼ばれる塵埃となる。そのような塵埃は、通常、帯電し
ているので、ウエハ表面の形成膜が静電気を帯びている
と、そのために生じる電界によって塵埃が引き寄せられ
てウエハに付着してしまう。
First, there is an increase in dust pollution. Reaction products adhere to the walls inside the device. When such reaction products are separated from the wall surface by various forces, they become dust called flakes. Such dust is usually electrically charged, so if a film formed on the wafer surface is charged with static electricity, the dust is attracted by the resulting electric field and adheres to the wafer.

【0005】次に、プロセスの不安定性の増大である。 プラズマプロセスでは、基板表面の電位によってプラズ
マの状態が微妙に変化する。従って、表面電位が制御で
きないと、結果としてプロセスそのものの制御が不十分
となる。
[0005] Next, there is an increase in process instability. In a plasma process, the plasma state changes slightly depending on the potential of the substrate surface. Therefore, if the surface potential cannot be controlled, the process itself will be insufficiently controlled as a result.

【0006】[0006]

【発明が解決しようとする課題】本発明の目的は、プロ
セス中の形成膜表面帯電を防止し、形成膜表面電位を制
御できるようにするものであり、特に、不導体膜形成後
に形成する導電性膜、例えば、アルミニウム膜のスパッ
タによる形成や、ポリシリコン膜のCVDによる形成時
にそれら形成膜の表面電位を制御する手段を提供するこ
とにある。
SUMMARY OF THE INVENTION An object of the present invention is to prevent the surface of a formed film from being charged during the process and to control the surface potential of the formed film. An object of the present invention is to provide a means for controlling the surface potential of a polysilicon film, for example, when forming an aluminum film by sputtering or a polysilicon film by CVD.

【0007】[0007]

【課題を解決するための手段】上記目的は、形成膜を導
体と電気的に接触させて、上記導体の電位を制御するこ
とで達成される。具体的には、以下の方法がある。
[Means for Solving the Problems] The above object is achieved by bringing the formed film into electrical contact with a conductor and controlling the potential of the conductor. Specifically, there are the following methods.

【0008】すなわち、第一の方法は、ウエハに接触あ
るいはごく近くに上記導体を設置し、形成膜が、ウエハ
の表面と導体表面をつなぐように形成されるようにする
方法である。こうすれば、膜は導電性であるから、導体
と膜は導通し、膜表面電位が導体を通じて行える。
That is, the first method is to place the conductor in contact with or very close to the wafer so that the formed film is formed so as to connect the surface of the wafer and the surface of the conductor. In this case, since the membrane is electrically conductive, the conductor and the membrane are electrically connected, and the membrane surface potential can be applied through the conductor.

【0009】第二の方法は、膜形成後に上記導体を膜表
面に接触させる方法である。この場合、膜の形成中は、
表面電位を制御することができないが、膜形成後の塵埃
付着低減に有効である。
The second method is to bring the conductor into contact with the surface of the film after the film is formed. In this case, during the formation of the film,
Although the surface potential cannot be controlled, it is effective in reducing dust adhesion after film formation.

【0010】第三の方法は、ウエハの裏面など、ウエハ
表面で不導体膜が形成されてない個所に上記導体を接触
させるとともに、形成膜が形成される場所の一部で、そ
れ以前に形成された不導体膜を除去しておき、形成膜(
導電性)がその部分では、ウエハの下地上に直接形成さ
れるようにすることで、ウエハ本体を通じて、ウエハ裏
面等に接触させた導体と、形成膜の間を電気的に接触さ
せる方法である。
The third method is to contact a portion of the wafer surface where a nonconductor film is not formed, such as the back surface of the wafer, with the conductor, and to contact a part of the area where a nonconductor film is formed, such as the back surface of the wafer, and to contact a portion of the wafer surface where a nonconductor film is not formed. The formed nonconductor film is removed, and the formed film (
This is a method in which a conductor (conductive) is formed directly on the base of the wafer in that area, thereby creating electrical contact between the conductor that is in contact with the back surface of the wafer, etc., and the formed film through the wafer body. .

【0011】[0011]

【作用】本発明の一実施例を用いて、各構成要素の作用
を説明する。
[Operation] The operation of each component will be explained using one embodiment of the present invention.

【0012】図1は、本発明の一実施例の構成を示す図
である。この実施例は、第一の方法、ウエハに接触ある
いはごく近くに導体を設置し、形成膜が、ウエハの表面
と導体表面をつなぐように形成されるようにする方法の
実施例である。本実施例の成膜装置1は、RFプラズマ
を用いる装置であり、パワー電極2に、RF電源4より
パワーが供給されるとともに、直流電源5によってバイ
アス電圧がかかる。パワー電極2は、不導体3によって
装置1の壁面とは、電気的に絶縁されている。ウエハ1
1は、やはり不導体9によって装置1の壁面と電気的に
絶縁しているサセプタ8の上に設置される。
FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. This example is an example of the first method, in which a conductor is placed in contact with or very close to the wafer, and a formed film is formed so as to connect the surface of the wafer and the surface of the conductor. The film forming apparatus 1 of this embodiment is an apparatus that uses RF plasma, and power is supplied to the power electrode 2 from an RF power source 4 and a bias voltage is applied by a DC power source 5. The power electrode 2 is electrically insulated from the wall surface of the device 1 by a nonconductor 3. Wafer 1
1 is placed on a susceptor 8 which is also electrically insulated from the wall of the device 1 by a non-conductor 9.

【0013】ウエハ11の側面には、ウエハ表面電位制
御用の導体12が接している。導体12は、直流電源1
2によってその電位が制御される。膜形成に必要なガス
はガス供給口6より流入し、排気口7から排気される。
A conductor 12 for controlling the wafer surface potential is in contact with the side surface of the wafer 11. The conductor 12 is connected to the DC power supply 1
2 controls its potential. Gas necessary for film formation flows in through the gas supply port 6 and is exhausted through the exhaust port 7.

【0014】このような構造であるため、図1(b)に
示すように、この装置で形成される導電性膜11−3は
、ウエハと導体12をつないで形成されるため、膜11
−3の電位は、導体12を通じて、プロセス全期間を通
して制御できる。
Because of this structure, the conductive film 11-3 formed by this apparatus is formed by connecting the wafer and the conductor 12, as shown in FIG. 1(b).
The -3 potential can be controlled throughout the process through conductor 12.

【0015】[0015]

【実施例】第一の実施例は、既に紹介したので、他の実
施例を説明する。
[Embodiments] Since the first embodiment has already been introduced, other embodiments will be explained.

【0016】次の実施例は、図2に示すものである。こ
の実施例は、第二の方法、すなわち、膜形成後に導体を
膜表面に接触させる方法の実施例である。この場合、膜
の形成中は、表面電位を制御することができないが、成
膜後に膜表面の電位が制御でき、成膜後の塵埃付着低減
に有効である。この実施例である装置1は、第一の実施
例と同様、RFプラズマで成膜する。始めの実施例と異
なるのは、導体12がリニアに動き、成膜中は、ウエハ
11と離れていて、成膜後にウエハと接する点である。 導体12は実際には、導体先端13が鞘で、鞘とは電気
的に絶縁して保持されており、先端13は導線14によ
って、直流電源10につながっている。導体12は、軸
受17−1と17−2で支えられており、その後端には
磁石15が設置されている。装置1の外側には、磁石1
5に対向するようにスライド磁石16がついていて、ス
ライド磁石16を動かすと、それにつれて導体12がリ
ニアに動く。このような構造なので、成膜後に、導体1
2をウエハ11の方にスライドさせて先端13をウエハ
11の、形成膜11−3に接触させて、ウエハの表面電
位を制御させる。
The next embodiment is shown in FIG. This example is an example of the second method, that is, the method of bringing the conductor into contact with the membrane surface after the membrane is formed. In this case, the surface potential cannot be controlled during film formation, but the film surface potential can be controlled after film formation, which is effective in reducing dust adhesion after film formation. The apparatus 1 of this embodiment forms a film using RF plasma as in the first embodiment. The difference from the first embodiment is that the conductor 12 moves linearly, is separated from the wafer 11 during film formation, and comes into contact with the wafer after film formation. The conductor 12 actually has a conductor tip 13 that is a sheath and is held electrically insulated from the sheath, and the tip 13 is connected to the DC power source 10 by a conductive wire 14. The conductor 12 is supported by bearings 17-1 and 17-2, and a magnet 15 is installed at the rear end. A magnet 1 is placed on the outside of the device 1.
A slide magnet 16 is attached to face 5, and when the slide magnet 16 is moved, the conductor 12 moves linearly. Because of this structure, after film formation, the conductor 1
2 toward the wafer 11 to bring the tip 13 into contact with the formed film 11-3 of the wafer 11, thereby controlling the surface potential of the wafer.

【0017】第三の実施例を図3に示す。これは、第三
の方法、すなわち、ウエハの裏面など、ウエハ表面で不
導体膜が形成されてない個所に導体を接触させるととも
に、形成膜が形成される場所の一部で、それ以前に形成
された不導体膜を除去しておき、形成膜(導電性)がそ
の部分では、ウエハの下地上に直接形成されるようにす
ることで、ウエハ本体を通じて、ウエハ裏面等に接触さ
せた導体と、形成膜の間を電気的に接触させる方法に対
応する。
A third embodiment is shown in FIG. This is the third method, in which a conductor is brought into contact with a part of the wafer surface where a nonconducting film is not formed, such as the backside of the wafer, and a part of the place where a nonconducting film is formed is used. By removing the nonconductive film that has been removed and forming a formed film (conductive) directly on the base of the wafer in that area, it is possible to connect the conductor that is in contact with the back surface of the wafer through the wafer body. , corresponds to a method of making electrical contact between formed films.

【0018】この実施例では、ウエハの裏面に静電チャ
ックによって導体12が接触している。静電チャックは
誘電体19に、電極20を通じて電源21から電気が供
給され、そこで生じる静電気力によってウエハと接触し
ている。静電チャックは導体12とやはり導電性である
ウエハに囲まれているので、そこに生じている静電気は
外には出ない。ウエハ11は、あらかじめその側面の一
部18で不導体膜11−2を除去して、ウエハの下地1
1−1を露出させる。もともと、不導体膜11−2はそ
の厚さが、たかだか1ミクロンかそれ以下の薄膜である
から、その除去はそこを軽くこすればよい。さて、その
ようにしてから膜を形成すると、図4に示すように、形
成される導電性膜11−3は、側面18で、ウエハの下
地11−1に接して形成されるので、膜11−3と導体
12がウエハそのものを通して電気的につながる。従っ
て、導体12を通じて、膜11−3表面電位が制御でき
る。
In this embodiment, a conductor 12 is brought into contact with the back surface of the wafer by an electrostatic chuck. In the electrostatic chuck, electricity is supplied to the dielectric 19 from a power source 21 through an electrode 20, and the electrostatic force generated therein brings the dielectric chuck into contact with the wafer. Since the electrostatic chuck is surrounded by the conductor 12 and the wafer, which is also conductive, static electricity generated therein does not escape. The wafer 11 is prepared by removing the nonconducting film 11-2 from a portion 18 of the side surface of the wafer 11 in advance, and then forming the base 1 of the wafer.
Expose 1-1. Originally, the nonconductor film 11-2 is a thin film with a thickness of at most 1 micron or less, so it can be removed by lightly rubbing it. Now, when a film is formed after doing so, as shown in FIG. -3 and conductor 12 are electrically connected through the wafer itself. Therefore, the surface potential of the membrane 11-3 can be controlled through the conductor 12.

【0019】[0019]

【発明の効果】膜形成において、形成膜表面の電位が任
意に制御できる。その効果、表面電位をアース電位,装
置内部も全て、プラズマプロセス時以外はアース電位に
制御した時と、ウエハだけが50Vに帯電した時の、フ
レーク塵埃の付着確率の差を図5に示す。図5は、フレ
ーク塵埃が電子一個を帯びていると仮定した時の解析結
果である。解析モデルは、枚葉式のプラズマCVD装置
で、パワー電極がシャワ電極、すなわち小さい孔が多数
設けてあり、それらの孔からガスが供給されるタイプに
なっている。解析は、ウエハ電位が0V,50Vの時で
、ウエハが重力に対して膜形成面が上向きに置かれてい
る場合と、ウエハが重力に対してそっている垂直プロセ
スでウエハ電位0Vの場合の三ケースについて行った。 ウエハ電位がたかだか50Vで、粒子の電荷が一個だけ
の時でも、特にサブミクロン粒子については、静電気が
ない時に比べて、付着確率が十倍になることがわかる。 また、大きい粒子は非常に多くの電荷を持ち得るので、
実際には、大きい粒子についても静電気による付着確率
の増加は顕著となる。
[Effects of the Invention] During film formation, the potential on the surface of the formed film can be controlled arbitrarily. Figure 5 shows the difference in flake dust adhesion probability when the surface potential is grounded and the entire inside of the device is grounded except during the plasma process, and when only the wafer is charged to 50V. FIG. 5 shows the analysis results assuming that the flake dust is tinged with one electron. The analysis model is a single-wafer type plasma CVD apparatus in which the power electrode is a shower electrode, that is, a type in which a large number of small holes are provided, and gas is supplied through these holes. The analysis is performed when the wafer potential is 0V and 50V, and the wafer is placed with the film formation surface facing upward against gravity, and when the wafer potential is 0V in a vertical process where the wafer is aligned against gravity. I followed three cases. It can be seen that even when the wafer potential is at most 50 V and there is only one charge on a particle, the adhesion probability is ten times greater than when there is no static electricity, especially for submicron particles. Also, large particles can have a large number of charges, so
In fact, even for large particles, the probability of adhesion due to static electricity increases significantly.

【0020】また、その他の効果としては、プラズマプ
ロセス時に表面電位が制御できるため、プロセス制御が
キメ細かに行え、プロセスが非常に安定になる。
[0020] In addition, as another effect, since the surface potential can be controlled during the plasma process, the process can be precisely controlled and the process becomes extremely stable.

【0021】[0021]

【発明の効果】本発明によればプロセス中の形成膜表面
帯電を防ぎ、形成膜表面電位を、制御することができる
According to the present invention, it is possible to prevent the surface of the formed film from being charged during the process and to control the surface potential of the formed film.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例を示す説明図。FIG. 1 is an explanatory diagram showing one embodiment of the present invention.

【図2】本発明の第二の実施例を示す説明図。FIG. 2 is an explanatory diagram showing a second embodiment of the present invention.

【図3】本発明の第三の実施例のプロセス前のウエハの
状態を示す説明図。
FIG. 3 is an explanatory diagram showing the state of a wafer before processing in a third embodiment of the present invention.

【図4】図3で示した実施例に関し、プロセス開始後、
成膜が始まってからのウエハの状態を示す説明図。
FIG. 4 Regarding the embodiment shown in FIG. 3, after starting the process,
FIG. 3 is an explanatory diagram showing the state of the wafer after film formation has started.

【図5】本発明の効果を示すもので、ウエハの帯電が制
御出来ないときに塵埃の付着確率が大きくなることを示
すグラフ。
FIG. 5 is a graph illustrating the effects of the present invention, showing that the probability of dust adhesion increases when wafer charging cannot be controlled.

【符号の説明】[Explanation of symbols]

1…成膜装置、2…パワー電極、10…電位制御用電源
、11…ウエハ、11−1…ウエハ下地、11−2…不
導体膜、11−3…導体膜、12…電位制御用導体。
DESCRIPTION OF SYMBOLS 1... Film forming apparatus, 2... Power electrode, 10... Power supply for potential control, 11... Wafer, 11-1... Wafer base, 11-2... Nonconductor film, 11-3... Conductor film, 12... Conductor for potential control .

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】CVD,スパッタ等で電導性のある膜の成
膜を気相中で行う装置において、被処理基板の一部に導
体を接触させておき、前記基板上と前記導体の表面上に
膜が連続して形成されるようにして、前記成膜と前記導
体間に導通が確保できるようにし、前記導体を通じて前
記成膜の電位を任意に制御できるようにしたことを特徴
とする半導体製造装置。
1. In an apparatus for forming a conductive film in a gas phase by CVD, sputtering, etc., a conductor is brought into contact with a part of a substrate to be processed, and a conductor is formed on the substrate and on the surface of the conductor. A semiconductor characterized in that a film is formed continuously to ensure continuity between the film and the conductor, and the potential of the film can be arbitrarily controlled through the conductor. Manufacturing equipment.
JP8813391A 1991-04-19 1991-04-19 Semiconductor manufacturing device Pending JPH04320325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8813391A JPH04320325A (en) 1991-04-19 1991-04-19 Semiconductor manufacturing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8813391A JPH04320325A (en) 1991-04-19 1991-04-19 Semiconductor manufacturing device

Publications (1)

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JPH04320325A true JPH04320325A (en) 1992-11-11

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670270B1 (en) 1998-03-24 2003-12-30 Nec Electronics Corporation Semiconductor device manufacturing apparatus and semiconductor device manufacturing method
JP2005339895A (en) * 2004-05-25 2005-12-08 Sekisui Chem Co Ltd Plasma treatment method and plasma treatment device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670270B1 (en) 1998-03-24 2003-12-30 Nec Electronics Corporation Semiconductor device manufacturing apparatus and semiconductor device manufacturing method
US7220318B2 (en) 1998-03-24 2007-05-22 Nec Electronics Corporation Semiconductor device manufacturing apparatus and semiconductor device manufacturing method
US7563696B2 (en) 1998-03-24 2009-07-21 Nec Electronics Corporation Semiconductor device manufacturing apparatus and semiconductor device manufacturing method
JP2005339895A (en) * 2004-05-25 2005-12-08 Sekisui Chem Co Ltd Plasma treatment method and plasma treatment device
JP4643929B2 (en) * 2004-05-25 2011-03-02 積水化学工業株式会社 Plasma processing method and plasma processing apparatus

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