JPH0431826A - Liquid crystal display element - Google Patents
Liquid crystal display elementInfo
- Publication number
- JPH0431826A JPH0431826A JP2138723A JP13872390A JPH0431826A JP H0431826 A JPH0431826 A JP H0431826A JP 2138723 A JP2138723 A JP 2138723A JP 13872390 A JP13872390 A JP 13872390A JP H0431826 A JPH0431826 A JP H0431826A
- Authority
- JP
- Japan
- Prior art keywords
- tft
- gap
- leveling layer
- transparent electrode
- tpt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000010408 film Substances 0.000 claims abstract description 20
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 abstract description 8
- 239000002245 particle Substances 0.000 abstract description 6
- 239000007772 electrode material Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 30
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011859 microparticle Substances 0.000 description 1
- 238000007645 offset printing Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
本発明は、薄膜トランジスタ（以下、ＴＰＴと略記する
。）により駆動される液晶表示素子に関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a liquid crystal display element driven by a thin film transistor (hereinafter abbreviated as TPT).
「従来の技術」
第４図は従来のＴＰＴ付液晶表示素子の例を示すもので
、この液晶表示素子は、２枚の透明ガラス基板１．２と
、それらの間に封入された液晶３と、一方の基板ｌの内
面に形成されたＴＰＴ４とを主な材料として構成されて
いる。"Prior Art" Figure 4 shows an example of a conventional liquid crystal display element with TPT.This liquid crystal display element consists of two transparent glass substrates 1.2 and a liquid crystal 3 sealed between them. , TPT 4 formed on the inner surface of one substrate l as the main material.
このＴＰＴ４は、一方の基板ｌ上にゲート電極５、ゲー
ト酸化層６、ゲート絶縁層７、半導体層８を順次積層し
、この半導体層８上に所定のチャンネル幅を空けて二つ
のｎ＋層９．９を形成し、さらに、これら ｎ＋層９，
９上にそれぞれソース電極ｌＯおよびドレイン電極１１
を設けて構成されている。またゲート絶縁層７上には透
明電極１２が設けられている。さらにこのＴＰＴ４上に
は配向膜１３が設けられている。This TPT 4 has a gate electrode 5, a gate oxide layer 6, a gate insulating layer 7, and a semiconductor layer 8 sequentially laminated on one substrate l, and two n+ layers 9 are placed on the semiconductor layer 8 with a predetermined channel width. .9, and furthermore, these n+ layers 9,
A source electrode lO and a drain electrode 11 are respectively formed on
It is configured by providing. Further, a transparent electrode 12 is provided on the gate insulating layer 7. Furthermore, an alignment film 13 is provided on this TPT4.
また他方の基板２の内面側には、透明電極１４と配向膜
１５が積層されている。Further, on the inner surface side of the other substrate 2, a transparent electrode 14 and an alignment film 15 are laminated.
また双方の基板１．２の外面には、偏光板２１．２２が
設けられている。Polarizing plates 21.22 are also provided on the outer surfaces of both substrates 1.2.
この液晶表示素子を作製するには、ＴＰＴ４を形成し、
その上に配向膜１３を形成し、この配向膜１３をラビン
グ処理した一方の基板ｌと、透明電極１４及び配向膜１
５を形成し、配向膜１５をラビング処理した他方の基板
２とを所定のギャップを確保しつつ接着させる。この際
１２枚の基板１．２間に所定のギャップを確保するため
、スペーサと称する微小粒子を間にはさんでいる。具体
的には、このスペーサを一方の基板ｌ上にふりかけ、こ
の上に他方の基板２をのせて重ねる。このように所定の
ギャップを確保した状態で２枚の基板１．２を重ね、こ
れらを接合した後、基板間に液晶３を封入する。To produce this liquid crystal display element, TPT4 is formed,
One substrate l on which an alignment film 13 is formed and the alignment film 13 is rubbed, a transparent electrode 14 and an alignment film 1
5 is formed, and the other substrate 2 on which the alignment film 15 has been rubbed is bonded to the other substrate 2 while maintaining a predetermined gap. At this time, in order to ensure a predetermined gap between the 12 substrates 1.2, microparticles called spacers are sandwiched between them. Specifically, this spacer is sprinkled on one substrate 1, and the other substrate 2 is placed on top of it. After the two substrates 1.2 are stacked with a predetermined gap secured in this manner and bonded together, the liquid crystal 3 is sealed between the substrates.
「発明が解決しようとする課題」
しかしながら、この液晶表示素子にあっては、ＴＰＴ４
が一方の基板１内面に突出した状態で形成されているた
めに、スペーサ粒子をふりかけて２枚の基板１．２を重
ね合わせる際、ＴＦＴＪ上にスペーサ粒子が乗るとＴＰ
Ｔ４が破損するおそれがあり、またギャップの均一性が
確保できなくなるという問題があった。"Problem to be solved by the invention" However, in this liquid crystal display element, TPT4
is formed protruding from the inner surface of one of the substrates 1. Therefore, when sprinkling spacer particles and overlapping the two substrates 1.2, if the spacer particles are placed on the TFTJ, the TP
There was a problem that T4 might be damaged and the uniformity of the gap could not be ensured.
また、ＴＰＴ４が一方の基板１内面に突出した状態で形
成されているために、配向膜１３をラビング処理する際
、突出したＴＰＴ４が邪魔となって、ラビングムラが生
じ易くなる問題があった。Further, since the TPT 4 is formed in a protruding state on the inner surface of one of the substrates 1, when rubbing the alignment film 13, the protruding TPT 4 becomes a hindrance, resulting in a problem that uneven rubbing tends to occur.
さらに、ＴＰＴ部のギャップ（第４図中、符号ｄ、で示
す）と表示部のギャップ（同図中、符号ｄ２で示す）と
では、約１〜２μｍのギャップ差（ｌｄ＋−ｄ！ｌ
）が生し、このためコントラストが悪化してしまう問題
もあった。Furthermore, there is a gap difference of about 1 to 2 μm (ld+-d!l) between the gap in the TPT section (indicated by d in FIG. 4) and the gap in the display section (indicated by d2 in the same figure).
), which caused the problem of deterioration of contrast.
本発明は、上記事情に鑑みてなされたしので、液晶表示
素子における基板間のギャップの均一化を目的としてい
る。The present invention has been made in view of the above circumstances and aims to equalize the gap between substrates in a liquid crystal display element.
「課題を解決するための手段」
かかる課題は、ＴＰＴ形成側の基板上に、ＴＰＴを覆っ
て平坦化するレベリング層を形成し、かつレベリング層
上に透明電極と配向膜とを形成することによって解消さ
れる。"Means for solving the problem" This problem can be solved by forming a leveling layer that covers and flattens the TPT on the substrate on the TPT forming side, and forming a transparent electrode and an alignment film on the leveling layer. It will be resolved.
「作用」
ＴＰＴ形成側の基板上に、ＴＰＴを覆って平坦化するレ
ベリング層を形成して構成したので、ＴＰＴ部のギャッ
プと表示部のギャップとの差を無くすことができ、スペ
ーサ粒子を介して２枚の基板を接合した際にＴＰＴが破
損するおそれがなく、基板間のギャップを均一化するこ
とができる。"Function" Since a leveling layer is formed on the substrate on the TPT formation side to cover and flatten the TPT, it is possible to eliminate the difference between the gap in the TPT section and the gap in the display section, and to There is no fear that the TPT will be damaged when two substrates are bonded together, and the gap between the substrates can be made uniform.
またＴＰＴ上に形成される配向膜のラビング処理が容易
となり、ラビングムラを防止できる。またＴＰＴ部と表
示部とのギャップ差をなくすことができるので、表示面
のコントラストか均一になる。Further, the rubbing treatment of the alignment film formed on the TPT becomes easy, and uneven rubbing can be prevented. Furthermore, since the gap difference between the TPT section and the display section can be eliminated, the contrast of the display surface becomes uniform.
以下、本発明の詳細な説明する。The present invention will be explained in detail below.
第１図はこの発明による液晶表示素子の一例を示す図で
ある。なお、同図において第４図と共通する構成要素に
は同一符号が付されている。FIG. 1 is a diagram showing an example of a liquid crystal display element according to the present invention. In this figure, the same reference numerals are given to the same components as those in FIG. 4.
この液晶表示素子では、一方の基板１のＴＦＴ４形成側
の面に、ＴＰＴ４を覆って平坦化するレベリング層１６
が形成され、このレベリング層１６の平坦な面上に、Ｉ
ＴＯなどからなる透明電極１７と配向膜１８が形成され
ている。またＴＰＴ４のソース電極１０上には、コンタ
クトホール１９が設けられ、その中を通って透明電極材
料がソース電極１０に達し、ソース電極ＩＯが透明電極
１７に導通している。In this liquid crystal display element, a leveling layer 16 is provided on the TFT 4 formation side of one substrate 1 to cover and planarize the TPT 4.
is formed on the flat surface of this leveling layer 16.
A transparent electrode 17 made of TO or the like and an alignment film 18 are formed. Further, a contact hole 19 is provided on the source electrode 10 of the TPT 4, through which the transparent electrode material reaches the source electrode 10, and the source electrode IO is electrically connected to the transparent electrode 17.
このレベリング層Ｉ６の厚さは、ＴＰＴ４よりも厚くな
るように形成され、例えばＴＰＴ４が１μ園厚であれば
、レベリング層１６は少なくとも１μｍ以上、好ましく
は１．５〜２μｍ程度の享さに形成される。The thickness of the leveling layer I6 is formed to be thicker than the TPT4. For example, if the TPT4 is 1 μm thick, the leveling layer 16 is formed to have a thickness of at least 1 μm or more, preferably about 1.5 to 2 μm. be done.
このレベリング層１６の形成方法としては、ＴＰＴ４を
形成した基板１に、オルガノンランまたはオルガノシリ
カゾル（例えば、東京応化製オルガノシリカゾルや、日
本コルコート社製 Ｓ ＩＯを系フルコートなど）をス
ピンナーで塗布し、次に温度２００〜３００℃で加熱硬
化して略Ｓ＋Ｏｔのレベリング層１６を形成する方法が
好適に用いられる。The method for forming the leveling layer 16 is to apply organonlan or organosilica sol (for example, organosilica sol manufactured by Tokyo Ohka Co., Ltd. or S IO full coat manufactured by Nihon Colcoat Co., Ltd.) to the substrate 1 on which the TPT 4 is formed using a spinner. Next, a method of heating and curing at a temperature of 200 to 300° C. to form a leveling layer 16 of approximately S+Ot is preferably used.
またスピンナーによる塗布の代わりに、オフセント印刷
を用いてレベリング層１６を形成することもできる。Further, instead of coating with a spinner, the leveling layer 16 can also be formed using offset printing.
また、ＴＦＴＪ上に、例えば窒化ケイ素やシリカ（Ｓｉ
Ｏｚ）をＣＶＤで積層して保護層を形成した後、上記方
法にてレベリング層１６を形成しても良い。In addition, for example, silicon nitride or silica (Si
The leveling layer 16 may be formed by the above method after forming a protective layer by stacking layers (Oz) by CVD.
またコンタクトホール１９は、レベリング層１６を形成
後、レベリング層１６を部分的にエツチングしてソース
電極ｌＯに達するコンタクトホール１９を形成しく第２
図）、次にレベリング層１６上にＩＴＯなどからなる透
明電極１７を成膜する際に、コンタクトホール１９内に
透明電極材料を入れ、ソース電極１０と透明電極１７が
導通する（第３図）ように構成されている。Further, after forming the leveling layer 16, the contact hole 19 is formed by partially etching the leveling layer 16 to form a second contact hole 19 reaching the source electrode IO.
(Fig. 3). Next, when forming a transparent electrode 17 made of ITO or the like on the leveling layer 16, a transparent electrode material is placed in the contact hole 19, and the source electrode 10 and the transparent electrode 17 are electrically connected (Fig. 3). It is configured as follows.
この液晶表示素子は、ＴＰＴ形成側の基板上に、ＴＰＴ
を覆って平坦化するレベリング層Ｉ６を形成して構成し
たので、ＴＦＴ部のギャップ（ｄＩ）と表示部のギャッ
プ（ｄ２）との差（ｌｄ、−ｃｔ、ｌ）がほとんど無く
なり（０，１μｍ以下）、スペーサ粒子を介して２枚の
基板１．２を接合した際にＴＰＴ４が破損するおそれが
なく、基板間のギャップを均一化することができる。This liquid crystal display element has TPT on the substrate on the side where TPT is formed.
Since the leveling layer I6 is formed to cover and planarize, the difference (ld, -ct, l) between the gap (dI) of the TFT section and the gap (d2) of the display section is almost eliminated (0.1 μm). (below), there is no fear that the TPT 4 will be damaged when the two substrates 1.2 are joined via spacer particles, and the gap between the substrates can be made uniform.
また平坦なレベリング層１６上に配向膜１８を形成する
ので、この配向膜のラビング処理が容易となり、ラビン
グムラを無くすことができる。またＴＦＴ部と表示部と
のギャップ差をなくすことができるので、表示面のコン
トラストを向上させることができる。Furthermore, since the alignment film 18 is formed on the flat leveling layer 16, the rubbing treatment of this alignment film is facilitated, and uneven rubbing can be eliminated. Furthermore, since the gap difference between the TFT section and the display section can be eliminated, the contrast of the display surface can be improved.
（実施例）
逆スタガー構造にＴＰＴ（厚さ約１μｍ）を形成した基
板にオルガノンリカゾル（東京応化社製）をスピンナー
で塗布し、２００〜３００℃で加熱硬化し、略Ｓ１０．
のレベリング層を約２μｍ形成した。次に、レベリング
層上にフォトレジストを塗布し、第２図に示したように
ソース電極と導通をとるべく局部的にレベリング層をエ
ツチングしてコンタクトホールを形成した。このエツチ
ングには通常のＨＰ系エッチャントを用いた。次に、こ
の基板にＩＴＯをスパッタして透明電極とし、所望の形
状にパターン化し、さらにその上に配向膜を形成し、ラ
ビング処理して一方の基板とした。(Example) Organon Ricasol (manufactured by Tokyo Ohka Co., Ltd.) was applied with a spinner to a substrate on which TPT (thickness: about 1 μm) was formed in an inverted staggered structure, and heated and cured at 200 to 300° C. to give approximately S10.
A leveling layer of about 2 μm was formed. Next, a photoresist was applied on the leveling layer, and as shown in FIG. 2, the leveling layer was locally etched to form a contact hole in order to establish conduction with the source electrode. A normal HP etchant was used for this etching. Next, this substrate was sputtered with ITO to form a transparent electrode, patterned into a desired shape, an alignment film was formed thereon, and a rubbing treatment was performed to obtain one substrate.
次に、この一方の基板上に、スペーサ粒子をふりかけ、
更に透明電極及び配向膜を形成した他方の基板をのせて
重ね、基板間を接着するとともに、液晶（ＴＮ）を封入
した。Next, sprinkle spacer particles on this one substrate,
Further, the other substrate on which a transparent electrode and an alignment film were formed was placed and stacked, and the substrates were bonded together, and liquid crystal (TN) was encapsulated.
得られた液晶表示素子は、ＴＰＴの破損がなく、従来法
によって作製したものと比べ、セル厚及びラビングムラ
による表示ムラが圧倒的に少なくなった。The obtained liquid crystal display element had no damage to the TPT and had significantly less display unevenness due to cell thickness and rubbing unevenness than those produced by conventional methods.
「発明の効果」
以上説明したように、本発明の液晶表示素子は、ＴＰＴ
形成側の基板上に、ＴＰＴを覆って平坦化するレベリン
グ層を形成したので、ＴＦＴ部のギャップと表示部のキ
ャップとの差をほとんど無くすことができ、スペーサ粒
子を介して２枚の基板を接合シた際にＴＰＴが破損する
おそれがなく、基板間のギャップを均一にすることがで
きる。"Effects of the Invention" As explained above, the liquid crystal display element of the present invention has TPT.
Since a leveling layer that covers and flattens the TPT is formed on the substrate on the formation side, the difference between the gap of the TFT section and the cap of the display section can be almost eliminated, and the two substrates can be connected via spacer particles. There is no fear that the TPT will be damaged during bonding, and the gap between the substrates can be made uniform.
また平坦化されたレベリング層上に配向膜を形成するの
で配向膜のラビング処理が容易となりラビングムラを無
くすことができる。またＴＦＴ部と表示部とのギャップ
差をなくすことができるので、表示面のコントラストを
均一にすることができる。Furthermore, since the alignment film is formed on the flattened leveling layer, the rubbing treatment of the alignment film becomes easy and uneven rubbing can be eliminated. Furthermore, since the gap difference between the TFT section and the display section can be eliminated, the contrast of the display surface can be made uniform.
第１図は、本発明による液晶表示素子の断面図、第２図
および第３図は、第１図に示す液晶表示素子のコンタク
トホールの形成方法を説明するための要部断面図である
。
第４図は従来の液晶表示素子の断面図である。
１．２・・・基板
４ ・・・ＴＰＴ
１６・・・レベリング層
１７・・・透明電極
１８・・・配向膜FIG. 1 is a sectional view of a liquid crystal display element according to the present invention, and FIGS. 2 and 3 are sectional views of essential parts for explaining a method for forming contact holes in the liquid crystal display element shown in FIG. 1. FIG. 4 is a cross-sectional view of a conventional liquid crystal display element. 1.2...Substrate 4...TPT 16...Leveling layer 17...Transparent electrode 18...Alignment film
Claims (1)
スタ形成側の基板上に、該薄膜トランジスタを覆って平
坦化するレベリング層を形成し、かつ該レベリング層上
に透明電極と配向膜とを形成したことを特徴とする液晶
表示素子。A liquid crystal display with a thin film transistor, characterized in that a leveling layer that covers and flattens the thin film transistor is formed on a substrate on the side where the thin film transistor is formed, and a transparent electrode and an alignment film are formed on the leveling layer. element.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2138723A JPH0431826A (en) | 1990-05-29 | 1990-05-29 | Liquid crystal display element |
| DE19914117484 DE4117484A1 (en) | 1990-05-29 | 1991-05-28 | LCD device driven by thin film transistor - covered by levelling and aligning layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2138723A JPH0431826A (en) | 1990-05-29 | 1990-05-29 | Liquid crystal display element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0431826A true JPH0431826A (en) | 1992-02-04 |
Family
ID=15228645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2138723A Pending JPH0431826A (en) | 1990-05-29 | 1990-05-29 | Liquid crystal display element |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0431826A (en) |
| DE (1) | DE4117484A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6011274A (en) * | 1997-10-20 | 2000-01-04 | Ois Optical Imaging Systems, Inc. | X-ray imager or LCD with bus lines overlapped by pixel electrodes and dual insulating layers therebetween |
| US6359672B2 (en) * | 1997-10-20 | 2002-03-19 | Guardian Industries Corp. | Method of making an LCD or X-ray imaging device with first and second insulating layers |
| US7095478B2 (en) | 1996-04-12 | 2006-08-22 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for fabricating thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1313563C (en) * | 1988-10-26 | 1993-02-09 | Makoto Sasaki | Thin film transistor panel |
| US5042918A (en) * | 1988-11-15 | 1991-08-27 | Kabushiki Kaisha Toshiba | Liquid crystal display device |
-
1990
- 1990-05-29 JP JP2138723A patent/JPH0431826A/en active Pending
-
1991
- 1991-05-28 DE DE19914117484 patent/DE4117484A1/en not_active Ceased
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7095478B2 (en) | 1996-04-12 | 2006-08-22 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for fabricating thereof |
| US7196749B2 (en) | 1996-04-12 | 2007-03-27 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for fabricating thereof |
| US7636136B2 (en) | 1996-04-12 | 2009-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for fabricating thereof |
| US6011274A (en) * | 1997-10-20 | 2000-01-04 | Ois Optical Imaging Systems, Inc. | X-ray imager or LCD with bus lines overlapped by pixel electrodes and dual insulating layers therebetween |
| US6359672B2 (en) * | 1997-10-20 | 2002-03-19 | Guardian Industries Corp. | Method of making an LCD or X-ray imaging device with first and second insulating layers |
Also Published As
| Publication number | Publication date |
|---|---|
| DE4117484A1 (en) | 1991-12-05 |
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