JPH04307763A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the steady-state current flow in a substrate potential detection circuit in a semiconductor integrated circuit making the substrate potential detection circuit. CONSTITUTION:The control signals 101 in a control signal transmitting circuit 1 are inputted to the respective gates of a PMOS transistor 3, another PMOS transistor 7 and an NMOS transistor 9 while the control signal 102 are inputted to the respective gates of an NMOS transistor 6 and a PMOS transistor 10. In the PMOS transistor 3, the conduction/cut-off modes are periodically repeated by the control signals 101 so that the substrate potential may be detected to be outputted in the conduction period but not to be detected in the cut-off period. In the conduction period of the PMOS transistor 3, the substrate potential detected output is inputted in an inverter 8 to be inverted and outputted from a terminal 28. Furthermore, in the cut-off period, the output from the substrate potential detection part is latched up.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, the present invention relates to a semiconductor integrated circuit forming a substrate potential detection circuit.

0002

2. Description of the Related Art In a conventional semiconductor integrated circuit of this type, as shown in FIG.
) and the substrate potential Vb, as a substrate potential detection section, a PM
The OS transistor 12 and the NMOS transistors 13 and 14 are connected in series, the gate of the PMOS transistor 12 is set to the ground potential, and the NMOS transistors 13 and 14 are connected in a forward direction from the power supply in accordance with the substrate potential Vb. diode connected to. The detection output at node A of this substrate potential detection section is input to the inverter 15, inverted, and output from the terminal 29. In this base potential detection section, a current is constantly flowing from the power supply to the base potential Vb, and fluctuations in the base potential Vb are detected based on the potential at node A corresponding to the fluctuating base potential.

[0003] The detection output at node A is
5 and is input to a predetermined substrate potential generation circuit (not shown), but if the substrate potential Vb rises above a desired potential, this substrate potential generation circuit is controlled to operate, and When the substrate potential Vb drops below a predetermined potential, the substrate potential generation circuit is controlled to stop operating.

0004

The above-mentioned conventional semiconductor integrated circuit has a drawback in that, due to operating conditions, a steady current must always be applied to the substrate potential from the power source in the substrate potential detection section.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention generates and outputs a periodic control signal and an inverted control signal obtained by inverting the control signal in a semiconductor integrated circuit forming a substrate potential detection circuit. control signal generating means for detecting and outputting a desired substrate potential during a substrate potential detection period under the control of the control signal;
a substrate potential detection means that stops detecting the substrate potential outside the substrate potential detection period; and a substrate that is controlled by the control signal and the inversion control signal and output from the substrate potential detection means during the substrate potential detection period. A latch means inputs and outputs a potential, and latches the output voltage from the substrate potential detecting means outside the substrate potential detecting period.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a control signal generating section formed by a control signal generating circuit 1 and an inverter 2, a substrate potential detecting section formed by a PMOS transistor 3, NMOS transistors 4 and 5,
NMOS transistor 6 and PMOS transistor 7
a first complementary transfer gate comprising an NMOS transistor 9 and a second complementary transfer gate comprising an NMOS transistor 9 and a PMOS transistor 10;
, and a latch section formed by inverters 8 and 11.

In FIG. 1, a control signal 101 outputted from a control signal generation circuit 1 is outputted from a terminal 21, inputted to the gate of a PMOS transistor 3 via a terminal 23 of a substrate potential detection section, and is also input to a gate of a PMOS transistor 3. The signal is input to the gate of the PMOS transistor 7 via the terminal 25 of the first complementary transfer gate, and to the gate of the NMOS transistor 9 via the terminal 26 of the second complementary transfer gate. Further, the control signal 102 output from the control signal generation circuit 1 and inverted by the inverter 2 is
N via terminal 24 of the first complementary transfer gate
The signal is input to the MOS transistor 6, and is also input to the gate of the PMOS transistor via the terminal 27 of the second complementary transfer gate.

The structure of the substrate potential detection section consisting of the PMOS transistor 3 and the NMOS transistors 4 and 5 is the same as that of the conventional example, except that the control signal 101 is input to the gate of the PMOS transistor 3. It is different from the example. The PMOS transistor 3 is controlled by a control signal 101 that is input to the gate via the terminal 23, and is periodically turned on/off, and has a function of detecting the substrate potential during the period of conduction. However, the function of detecting the substrate potential is lost during the cut-off period.

Control signal 1 input to the gate from terminal 23
During the period in which the PMOS transistor 3 is in a conductive state, the first complementary transfer gate and the second complementary transfer gate receive the control signal 10 via the control signal 10.
1 and 102, respectively, and the potential at node A, which is the detection output of the substrate potential detection section, is transferred to the inverter 8 via the NMOS transistor 6 in the first complementary transfer gate. The signal is inputted to the terminal 28, inverted, and outputted from the terminal 28 and sent to a predetermined substrate potential generation circuit (not shown) to control the operation/stop of the substrate potential generation circuit. This point is similar to the case of the conventional example described above.

Next, during the period in which the PMOS transistor 3 is in the cut-off state, the first complementary transfer gate and the second complementary transfer gate are controlled via the control signal 101 inputted to the gate from the terminal 23. Via signals 101 and 102, they are in a cutoff state and a conduction state, respectively, and in this case, the potential at node A, which is the detection output of the substrate potential detection section, is latched and the terminal 2
8 will not be output. That is, during the period when the substrate potential detection function is lost, the substrate potential Vb is
Current is prevented from flowing through.

0012

Effects of the Invention As explained above, the present invention provides a control signal generation circuit to a PMO which forms a substrate potential detection section.
By controlling conduction/cutoff of the S transistor, the current flowing from the power supply to the substrate potential detection section can be stopped outside the substrate potential detection period, and the steady current in the substrate potential detection section can be reduced. be.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1 Control signal generation circuit

Claims (1)

[Claims] 1. A semiconductor integrated circuit forming a substrate potential detection circuit, comprising: a control signal generating means for generating and outputting a periodic control signal and an inverted control signal obtained by inverting the control signal; a substrate potential detection means for detecting and outputting a desired substrate potential during the substrate potential detection period and stopping detection of the substrate potential outside the substrate potential detection period; a latch that is controlled to input and output the substrate potential output from the substrate potential detection means during the substrate potential detection period, and to latch the output voltage from the substrate potential detection means outside the substrate potential detection period; A semiconductor integrated circuit comprising means.