JPH04291410A - Interface circuit - Google Patents
Interface circuitInfo
- Publication number
- JPH04291410A JPH04291410A JP3056290A JP5629091A JPH04291410A JP H04291410 A JPH04291410 A JP H04291410A JP 3056290 A JP3056290 A JP 3056290A JP 5629091 A JP5629091 A JP 5629091A JP H04291410 A JPH04291410 A JP H04291410A
- Authority
- JP
- Japan
- Prior art keywords
- information processing
- turned
- power
- processing device
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 48
- 238000012544 monitoring process Methods 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 230000002265 prevention Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 1
Landscapes
- Power Sources (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、各々独立した内蔵電源
をもった情報処理装置間を信号線により結合し、情報処
理装置を拡張するシステムに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for expanding information processing apparatuses by connecting information processing apparatuses each having an independent built-in power supply through a signal line.
【０００２】0002
【従来の技術】従来の情報処理装置間を結合するインタ
ーフェースの素子としてオープンコレクタ，オープンド
レイン，トーテムポール等を使用していた。2. Description of the Related Art Conventionally, open collectors, open drains, totem poles, etc. have been used as interface elements for coupling between information processing devices.
【０００３】なお、この種の装置として関連するものに
は、例えば、特開平２−９６２１０号公報が挙げられる
。[0003] Related devices of this type include, for example, Japanese Patent Application Laid-Open No. 2-96210.
【０００４】0004
【発明が解決しようとする課題】上記従来技術は、情報
処理装置間を結合するためのインターフェース回路部の
送信素子としてオープンコレクタ，又はオープンドレイ
ンを使用し、プルアップ抵抗を付加していた。しかし、
素子や、伝送媒体等に含まれるストレージキャパシタの
影響（時定数−プルアップ抵抗値×ストレージキャパシ
タ値）で伝送時間の遅延の問題があり、高速動作に不向
きであった。また、伝送遅延の影響を少なくするために
、プルアップ抵抗値を下げると、消費電流の増大、及び
送信側素子のファンアウトオーバ等の問題があった。The above-mentioned prior art uses an open collector or an open drain as a transmitting element of an interface circuit section for coupling between information processing devices, and adds a pull-up resistor. but,
There is a problem of transmission time delay due to the influence of the storage capacitor included in the element and the transmission medium (time constant - pull-up resistance value x storage capacitor value), making it unsuitable for high-speed operation. Further, when the pull-up resistance value is lowered in order to reduce the influence of transmission delay, there are problems such as an increase in current consumption and fan-out of the transmitting side element.
【０００５】また、インターフェース回路部にトーテム
ポール素子を使用し、インターフェース回路部を高速動
作させる場合、送信側情報処理装置の電源オン、受信側
の情報処理装置の電源がオフ時、電源のない受信側素子
入力に電圧が印加され、受信側素子が破損する問題があ
った。[0005] Furthermore, when a totem pole element is used in the interface circuit section and the interface circuit section is operated at high speed, when the transmitting side information processing device is powered on and the receiving side information processing device is powered off, it is difficult to receive data without power. There was a problem in that a voltage was applied to the input of the side element, damaging the receiving side element.
【０００６】本発明の目的は、情報処理装置システムの
高速動作を可能にし、かつ、受信素子の破損を防ぐこと
にある。An object of the present invention is to enable high-speed operation of an information processing device system and to prevent damage to receiving elements.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明は情報処理装置のインターフェース回路部の
送信素子としてトーテムポールを使用し、各々の情報処
理装置に他情報処理装置の電源オン，オフを監視する機
能を付加し、受信側電源がオフ時、受信素子に電圧が印
加されないように信号をインターロックした。[Means for Solving the Problems] In order to achieve the above object, the present invention uses a totem pole as a transmitting element of an interface circuit section of an information processing device, and each information processing device is configured to turn on the power of other information processing devices. , We added a function to monitor when the receiver is off, and interlocked the signal so that no voltage is applied to the receiver element when the receiver power is off.
【０００８】[0008]
【作用】請求項１の受信素子破損防止回路は、送信側の
情報処理装置が受信側の情報処理装置の電源オフを検出
し、送信側出力をハイインピーダンスとするように動作
する。それによって電源オフの受信側素子に電圧は印加
されず、受信側素子を破損することはない。The receiving element damage prevention circuit according to the first aspect of the present invention operates such that the information processing device on the transmitting side detects that the power of the information processing device on the receiving side is turned off, and makes the output on the transmitting side high impedance. As a result, no voltage is applied to the receiving element when the power is turned off, and the receiving element will not be damaged.
【０００９】請求項２の電源のインターロックに関して
は、全数の情報処理装置の電源がオンすることをもって
、各々の情報処理装置内の回路の電源が入るように動作
する。それによって電源オフの受信側素子に電圧は印加
されず、受信側素子を破損することはない。Regarding the power supply interlock according to claim 2, the power supply is operated so that when all the information processing apparatuses are powered on, the circuits in each information processing apparatus are powered on. As a result, no voltage is applied to the receiving element when the power is turned off, and the receiving element will not be damaged.
【００１０】0010
【実施例】以下、本発明の一実施例を説明する。[Embodiment] An embodiment of the present invention will be described below.
【００１１】＜実施例１＞図１は、本実施例における情
報処理装置の回路図である。本実施例における各情報処
理装置１，１０は、トランジスタ２，１１とトーテムポ
ール形のスリーステート送信素子３，１３と、受信素子
４，１２と、論理回路６，１５より構成される。<Embodiment 1> FIG. 1 is a circuit diagram of an information processing apparatus in this embodiment. Each information processing device 1, 10 in this embodiment is composed of transistors 2, 11, totem pole type three-state transmitting elements 3, 13, receiving elements 4, 12, and logic circuits 6, 15.
【００１２】以下、本実施例の動作について説明する。The operation of this embodiment will be explained below.
【００１３】情報処理装置１の電源オン，情報処理装置
２の電源オン時、トランジスタ２がオンし、スリーステ
ート送信素子３がイネーブルとなり、信号線２２が有効
となる。また、情報処理装置１の電源オン，情報処理装
置２の電源オフ時、トランジスタ２がオフし、スリース
テート送信素子３がディスイネーブルとなり、信号線２
２がハイインピーダンス状態となって受信素子１２に電
圧が印加されない。また、情報処理装置１の電源オフ，
情報処理装置２の電源オフン時、トランジスタ１１がオ
フし、スリーステート送信素子１３がディスイネーブル
となり、信号線２３がハイインピーダンス状態となって
受信素子４に電圧が印加されない。When the information processing device 1 and the information processing device 2 are powered on, the transistor 2 is turned on, the three-state transmitting element 3 is enabled, and the signal line 22 is enabled. Further, when the information processing device 1 is powered on and the information processing device 2 is powered off, the transistor 2 is turned off, the three-state transmission element 3 is disabled, and the signal line 2 is turned off.
2 is in a high impedance state and no voltage is applied to the receiving element 12. In addition, the power of the information processing device 1 is turned off,
When the information processing device 2 is powered off, the transistor 11 is turned off, the three-state transmitting element 13 is disabled, the signal line 23 is in a high impedance state, and no voltage is applied to the receiving element 4.
【００１４】本実施例によれば、電源オフ状態の受信素
子に電圧が印加されず、受信素子を破損しない。According to this embodiment, no voltage is applied to the receiving element in the power-off state, so that the receiving element is not damaged.
【００１５】＜実施例２＞図２は、本実施例における情
報処理装置の回路図である。本実施例における各情報処
理装置３０，４０は、リレー３１，３２，４１，４２と
論理回路３４，４４から構成される。<Embodiment 2> FIG. 2 is a circuit diagram of an information processing apparatus in this embodiment. Each information processing device 30, 40 in this embodiment is composed of relays 31, 32, 41, 42 and logic circuits 34, 44.
【００１６】以下、本実施例の動作について説明する。The operation of this embodiment will be explained below.
【００１７】情報処理装置１の電源オン，情報処理装置
１０の電源オン時、リレー３１，３２，４１，４２がオ
ンし、論理回路に電源線３３，４３を経由して電源が供
給される。また、情報処理装置３０の電源オン，情報処
理装置４０の電源オフ時、リレー３２がオフとなるため
、論理回路３４に電源が供給されない。それにより、電
源オフの論理回路４４内の受信素子に電圧が印加されな
い。また、情報処理装置３０の電源オフ，情報処理装置
４０の電源オン時、リレー３３がオフとなるため、論理
回路４４に電源が供給されない。それにより、電源オフ
の論理回路３４の受信素子に電圧が印加されない。When the information processing device 1 and the information processing device 10 are powered on, the relays 31, 32, 41, and 42 are turned on, and power is supplied to the logic circuit via the power lines 33, 43. Further, when the information processing device 30 is powered on and the information processing device 40 is powered off, the relay 32 is turned off, so power is not supplied to the logic circuit 34. As a result, no voltage is applied to the receiving elements in the logic circuit 44 that is powered off. Furthermore, when the information processing device 30 is powered off and the information processing device 40 is powered on, the relay 33 is turned off, so power is not supplied to the logic circuit 44. As a result, no voltage is applied to the receiving element of the logic circuit 34 that is powered off.
【００１８】本実施例によれば、電源オフ状態の受信素
子に電圧が印加されず、受信素子を破損することがない
。According to this embodiment, no voltage is applied to the receiving element in the power-off state, so that the receiving element is not damaged.
【００１９】[0019]
【発明の効果】本発明によれば、電源オフの受信素子に
電圧が印加されないので、各情報処理装置の電源投入順
序を規定する必要がない。また、各情報処理装置の電源
を別個に設けられるため、単一電源を各情報処理装置へ
供給するシステムと比較して、電源の引回しが不必要と
なり、誤動作が発生しにくい。According to the present invention, since no voltage is applied to receiving elements when the power is off, there is no need to specify the order in which the power is turned on for each information processing device. Furthermore, since the power supply for each information processing device is provided separately, compared to a system that supplies a single power supply to each information processing device, there is no need to route the power supply, and malfunctions are less likely to occur.
【００２０】また、他情報処理装置を使用せず、一つの
情報処理装置単体で動作できるシステムで有益であり、
さらに、全情報処理装置の電源がオンして動作するシス
テムで、消費電力を最小とすることができる。[0020] Also, it is useful as a system that can operate with one information processing device alone without using other information processing devices.
Furthermore, in a system that operates with all information processing devices turned on, power consumption can be minimized.
【図１】本発明の一実施例の情報処理装置の回路図。FIG. 1 is a circuit diagram of an information processing device according to an embodiment of the present invention.
【図２】本発明の他の実施例の情報処理装置の回路図。FIG. 2 is a circuit diagram of an information processing device according to another embodiment of the present invention.
１，１０…情報処理装置、２，１１…トランジスタ、３
，１３…トーテムポール形スリーステート送信素子、４
，１２…受信素子、６，１５…論理回路、３０，４０…
情報処理装置、３１，３２，４１，４２…リレー、３４
，４４…論理回路。1, 10... Information processing device, 2, 11... Transistor, 3
, 13... totem pole type three-state transmitting element, 4
, 12...Receiving element, 6, 15...Logic circuit, 30, 40...
Information processing device, 31, 32, 41, 42...relay, 34
, 44...Logic circuit.
Claims (2)
処理装置の相互間を、信号線により結合するシステムに
おいて、各々の前記情報処理装置に電源監視機能を設け
、前記信号線の受信側の前記情報処理装置の電源オフ時
、前記情報処理装置の電源オフの状態を送信側の前記情
報処理装置に伝達して前記信号線の送信素子出力に電圧
出力防止のインターロック制御をかけることにより、電
源オフ状態の受信素子に電圧が印加されて前記受信素子
が破損されることを防ぐ機能を付加したことを特徴とす
るインターフェース回路。Claim 1: A system in which a plurality of information processing devices each having an independent built-in power supply are connected to each other by a signal line, wherein each of the information processing devices is provided with a power supply monitoring function, and a receiving side of the signal line is provided with a power monitoring function. When the power of the information processing device is turned off, the power-off state of the information processing device is transmitted to the information processing device on the transmitting side, and interlock control is applied to the output of the transmitting element of the signal line to prevent voltage output. . An interface circuit characterized in that an interface circuit is added with a function of preventing damage to the receiving element due to voltage being applied to the receiving element in a power-off state.
前記情報処理装置の電源オフ時、前記情報処理装置の電
源オフの状態を送信側に伝達して送信側の電源を受信側
の電源がオンの時のみオンするようにインターロックす
る情報処理装置。2. In claim 1, when the power of the information processing device on the receiving side of the signal line is turned off, the power-off state of the information processing device is transmitted to the transmitting side so that the power on the transmitting side is turned off on the receiving side. An information processing device that is interlocked so that it turns on only when the power is on.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3056290A JPH04291410A (en) | 1991-03-20 | 1991-03-20 | Interface circuit |
| BR929200971A BR9200971A (en) | 1991-03-20 | 1992-03-19 | ELECTRIC COOKING APPLIANCE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3056290A JPH04291410A (en) | 1991-03-20 | 1991-03-20 | Interface circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04291410A true JPH04291410A (en) | 1992-10-15 |
Family
ID=13022970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3056290A Pending JPH04291410A (en) | 1991-03-20 | 1991-03-20 | Interface circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04291410A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11264989B1 (en) | 2020-08-07 | 2022-03-01 | Kabushiki Kaisha Toshiba | Semiconductor device |
-
1991
- 1991-03-20 JP JP3056290A patent/JPH04291410A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11264989B1 (en) | 2020-08-07 | 2022-03-01 | Kabushiki Kaisha Toshiba | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69426470T2 (en) | Local network system | |
| US5202593A (en) | Bi-directional bus repeater | |
| US4488066A (en) | Databus coupling arrangement using transistors of complementary conductivity type | |
| JPH0535668A (en) | Signal processor | |
| JPH09512371A (en) | Circuit having data communication bus | |
| TW509965B (en) | Mixed swing voltage repeaters for high resistance or high capacitance signal | |
| KR100247604B1 (en) | Digital voltage shifters and systems using the same | |
| US5450356A (en) | Programmable pull-up buffer | |
| JPH04291410A (en) | Interface circuit | |
| US4449064A (en) | Three state output circuit | |
| JP2837122B2 (en) | Data output buffer circuit of semiconductor memory device | |
| CA1304805C (en) | Data transmission system | |
| CN113778363B (en) | Display terminal, cascading system thereof and control method | |
| US5051619A (en) | Predrive circuit having level sensing control | |
| US5880606A (en) | Programmable driver circuit for multi-source buses | |
| JPH0785562B2 (en) | Failure detection method between communication devices | |
| US5225722A (en) | Signal transmission circuit and signal transmission method | |
| US6731154B2 (en) | Global voltage buffer for voltage islands | |
| US6816417B2 (en) | Input/output buffer circuit | |
| JP3203409B2 (en) | Switch circuit for bidirectional bus line | |
| JP4190593B2 (en) | Data processing system with compensation circuit to compensate for capacitive coupling on the bus | |
| JP3737567B2 (en) | Computer system | |
| JPH0225202B2 (en) | ||
| US7436215B2 (en) | Transmitter | |
| JPH03206711A (en) | Input buffer circuit |