JPH04273148A - Gate array type semiconductor integrated circuit and drive method thereof - Google Patents

Abstract

PURPOSE:To inhibit the generation of noise induced by level fluctuations in a power source line. CONSTITUTION:An unused bonding pad 4u is connected to a power supply line (GND line 6) by way of transistors 2A1 to 2An in an outer cell. Bias voltage VB1, which turns on or off a transistor connected between an unused bonding pad and the power supply line, responding to level fluctuations in a power supply line is applied.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applied to gate array type semiconductor integrated circuits, and in particular, in LSI tester inspection, VDD within a chip is reduced by simultaneous operation of its output buffers.
The present invention relates to a gate array type semiconductor integrated circuit that reduces noise generation in power supply lines such as GND.

0002

2. Description of the Related Art In general, a gate array type semiconductor integrated circuit has an external cell 2, an internal cell 3, and a plurality of bonding pads 4 disposed on a chip 1, and a VDD line 5 and a GND line 6, as shown in FIG. The configuration is such that each power supply line is placed around the periphery. Here, a bonding pad 4V is connected to the VDD line 5, and a bonding pad 4g is connected to the GND line 6. Also, bonding pad 4
s is connected to the external cell 2 for signal use, and the bonding pad 4u is unused.

0003

[Problems to be Solved by the Invention] The conventional gate array type semiconductor integrated circuit described above is tested using an LSI tester after wiring is formed and after assembly is completed, but due to the structure of this LSI tester, a considerable load capacity is required. In gate array type semiconductor integrated circuits, noise is likely to occur on the power supply line due to this load. As a countermeasure to this problem, it is effective to limit the number of output buffers that operate simultaneously or to adopt a structure in which the output buffer is placed near the power supply line, but this poses a major constraint when designing gate array type semiconductor integrated circuits. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate array type semiconductor integrated circuit which suppresses noise generation in a power supply line by solving the above-mentioned problems.

[0005]

Means for Solving the Problems The gate array type semiconductor integrated circuit of the present invention includes a plurality of bonding pads and external cells arranged around a chip, and a power supply line. The bonding pad is characterized in that it includes an unused bonding pad connected to the power supply line via a transistor in the external cell.

Further, the method for driving a gate array type semiconductor integrated circuit of the present invention provides a method for driving a gate array type semiconductor integrated circuit according to claim 1, wherein in the gate array type semiconductor device according to claim 1, the power line is connected between the unused bonding pad and the power line. A bias voltage is applied to make the connected transistors conductive in response to level fluctuations.

[0007]

[Operation] A bias voltage is applied between the unused bonding pad connected to the power line via a transistor in the external cell and the power line, and if the level of the power line changes, the connection will be interrupted. The connected transistor becomes conductive to prevent level fluctuations in the power supply line.

[0008] Therefore, it is possible to suppress the generation of noise due to power line level fluctuations.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the main parts of a first embodiment of the present invention. The first embodiment is an example applied to the gate array type semiconductor integrated circuit chip shown in FIG. 3, and uses an unused bonding pad 4u among a plurality of bonding pads. That is, as a noise reduction measure in the GND line 6, which is a feature of the present invention, as shown in FIG.
, 2A2, . . . , 2An are connected to the GND line 6. Here, N channel MOS transistors 2A1, 2A
2,..., 2An connect the source and drain to the unused bonding pad 4u and the GND line 6, respectively.
The gate is connected to the GND line 6. Furthermore, -0.6 V is applied to unused bonding pad 4u.
Apply a bias voltage VB1 of approximately

With this circuit configuration, when the GND level rises by about 0.1V or more due to the simultaneous operation of the output buffer from the "H" level to the "L" level, the N-channel MOS transistors 2A1, 2A2, . . . , 2An
conducts and operates to lower the GND level, suppressing noise generation.

FIG. 2 is a circuit diagram showing the main part of a second embodiment of the present invention, and shows an example in which measures are taken to reduce noise in the VDD line 5. That is, the VDD, which is a feature of the present invention,
Connect wire 5 and unused bonding pad 4u to external cell 2.
P-channel MOS transistors 2B1 and 2B2 in
,..., are connected via 2Bn. Here, P channel MOS transistors 2B1, 2B2,..., 2B
n connects the source and drain to unused bonding pad 4u and VDD line 5, respectively;
The gate is connected to an unused bonding pad 4u. Also unused bonding pad 4u and VDD
A bias voltage VB2 of about +0.6 V is applied between the lines 5. In this circuit configuration, when the VDD level drops by about 0.1V or more due to simultaneous operation of the output buffer from "L" level to "H" level, P channel MOS transistors 2B1, 2B2, ..., 2Bn become conductive and VDD
It operates in the direction of raising the level and suppresses noise generation.

[0013]

[Effects of the Invention] As explained above, the present invention provides VDD
When the level of the GND power supply line fluctuates, the transistor connected between the unused bonding pad becomes conductive, suppressing the level fluctuation, and suppressing the generation of noise in the power supply line. As a result, there is no need to limit the number of output buffers that operate simultaneously or the arrangement of output buffers, and the degree of freedom in designing a gate array type semiconductor integrated circuit can be improved, which is highly effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the main parts of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing the main parts of a second embodiment of the present invention.

FIG. 3 is a plan layout diagram of a chip to which the present invention is applied.

[Explanation of symbols]

1 Chip 2 External cells 2A1, 2A2,..., 2An N-channel MOS transistors 2B1, 2B2,..., 2Bn P-channel MOS transistors 3 Internal cells 4g, 4s, 4u, 4v Bonding pad 5 VDD line 6 GND line VB1, VB2 Bias voltage

Claims (2)

[Claims] 1. In a gate array type semiconductor integrated circuit including a plurality of bonding pads and external cells arranged around a chip, and a power supply line, the bonding pad connects the power supply through a transistor in the external cell. A gate array type semiconductor integrated circuit characterized in that it includes an unused bonding pad connected to a line. 2. The gate array type semiconductor integrated circuit according to claim 1, wherein a transistor connected between the unused bonding pad and the power supply line is made conductive according to a level fluctuation of the power supply line. A method for driving a gate array type semiconductor integrated circuit, the method comprising applying a bias voltage.