JPH04267225A - Manufacture of thin film transistor array device - Google Patents

Abstract

PURPOSE:To provide an efficient method of manufacturing a thin film transistor array device which has a low possibility of occurrence of a defect, by improving the pattern of source wiring in a method of manufacturing a thin film transistor array which can be formed of two photo-masks by exposing a photo-resist through a gate wiring as a mask from the rear surface side of a transparent substrate so as to form a photoresist pattern which is aligned with the gate wiring. CONSTITUTION:Simultaneous with the formation of source wiring 7 and pixel electrodes 8, the source wiring 7 is formed thereto with branch parts 7a. Accordingly, even though a breakage occurs at the crossing between the branch part 7a and a gate wiring 2, no defects occur.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor array device used in a so-called active matrix liquid crystal display device.

0002

2. Description of the Related Art Conventionally, thin film transistor array devices used in active matrix liquid crystal display devices and the like have been manufactured by using only two photomasks.

FIG. 6 is a cross-sectional view schematically showing a method of manufacturing such a thin film transistor array device. Figure 7
is a plan view corresponding to FIG. 6(F), and is a plan view corresponding to FIG.
FIG. 6(F) shows a cross section along IV. Hereinafter, the manufacturing method (
(manufacturing process).

(A) A gate wiring 2 is formed using a light-shielding metal such as chromium on a transparent substrate 1 made of glass or the like. Note that the gate wiring herein is a general term that includes gate electrodes of each transistor as well as gate wiring in a narrow sense that connects the gates of each transistor.

(B) A gate insulating layer 3 made of silicon nitride, an intrinsic amorphous silicon layer 4 containing almost no impurities that serve as donors or acceptors, and an appropriate amount of impurities that serve as donors or acceptors such as phosphorus. The impurity-doped amorphous silicon layer 5 (n+ amorphous silicon layer) is formed by plasma CVD.
sequentially deposited using a method. These gate insulating layer 3, intrinsic amorphous silicon layer 4, and impurity-doped amorphous silicon layer 5 are all transparent.

(C) A positive photoresist 6 is applied on the impurity-doped amorphous silicon layer 5. continuation,
An appropriate amount of ultraviolet light is irradiated onto the photoresist 6 from the back side of the transparent substrate 1 to expose the photoresist 6 to light. Since the gate wiring 2 does not transmit ultraviolet rays, the photoresist 6 above the gate wiring 2 is not exposed.

(D) Developing the photoresist 6 to form a game
Photoresist pattern 6 having substantially the same planar shape as the contact wiring 2
form. Using this photoresist pattern 6 as a mask, the intrinsic amorphous silicon layer 4 and the impurity-doped amorphous silicon layer 5 are etched to form the intrinsic amorphous silicon layer pattern 4 and the impurity-doped amorphous silicon layer 5. A crystalline silicon layer pattern 5 is formed.

(E) ITO (indium tin)
A transparent conductive layer using oxide) is deposited over the entire surface, and this is selectively removed to form the source wiring 7 and the pixel electrode 8 at the same time. Note that the term "source wiring" as used herein is a general term that includes not only the source wiring in a narrow sense that connects the sources of each transistor, but also the source electrode of each transistor.

[0009] The pixel electrode herein refers to the pixel electrode in a narrow sense connected to the drain of each transistor;
This is a general term that also includes the drain electrode of each transistor.

(F) The impurity-doped amorphous silicon layer pattern 5 is etched using the source wiring 7 and the pixel electrode 8 as a mask. At this time, it is necessary to completely remove the impurity-doped amorphous silicon layer pattern 5 in the etched area, so a slight over-etching is performed. As a result, the intrinsic amorphous silicon layer pattern 4 is also slightly etched.

As described above, FIGS. 6(F) and 7
A thin film transistor array device as shown in FIG. In addition, in FIG. 7, R, G, B shown in the pixel electrode 8
indicates the display color corresponding to each pixel electrode, R indicates red, G indicates green, and B indicates blue.

0012

[Problems to be Solved by the Invention] By the way, as can be seen from FIG. 7, in a thin film transistor array, a plurality of sources
Since the source wiring 7 and the plurality of gate wirings 2 are wired vertically and horizontally, the source wiring 7 and the gate wirings 2 inevitably intersect with each other. Therefore, the source wiring 7 is likely to be disconnected at the intersection. For example, in an active matrix type liquid crystal display device, if a wire breakage occurs at even one point, a signal will not be transmitted after the breakage point, and this will appear as a line defect when viewed as a whole.

In the conventional thin film transistor array, when focusing on one source wiring 7 and one gate wiring 2, as can be seen from FIG.
It intersects with the main wiring 2. Therefore, there is a problem in that the probability of disconnection of the source wiring 7 increases accordingly, and line defects are more likely to occur.

An object of the present invention is to provide a method for manufacturing a thin film transistor array device in which the probability of line defects occurring is low by improving the pattern of the source wiring.

[0015]

[Means for Solving the Problems] The present invention forms branches that overlap the gate wiring in the transparent conductive layer removal process, and connects the gate wiring and the pixel electrode. The o-
The overlap part is used as the drain, and the overlap part between the gate wiring and the branch part is used as the source.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 5 are plan views schematically showing first to fifth embodiments, respectively, and show a part of a thin film transistor array used in an active matrix liquid crystal display device. The basic manufacturing methods (manufacturing steps) in the first to fifth embodiments are all the same as the conventional example shown in FIG. Therefore, for the manufacturing method (manufacturing process), the one shown in FIG. 6 will be used and the explanation will be omitted. Further, in FIGS. 1 to 5, the same reference numerals as those in FIGS. 6 and 7 represent the same components, and a description thereof will be omitted.

In FIGS. 1 to 5, 2a is the gate wiring 2
This is a branch formed as a part of the gate wiring 2, and is formed simultaneously with the gate wiring 2 in the process shown in FIG. 6(A). 1 to 5, 7a is a branch formed as part of the source wiring 7, and 8a is a branch formed as part of the pixel electrode 8. These branch portions 7a and 8a are shown in FIG. 6(E).
In the process, the source wiring 7 and the pixel electrode 8 are formed simultaneously.

In the first to fifth embodiments shown in FIGS. 1 to 5, the first overlapping portion between the gate wiring 2 and the pixel electrode 8 is used as a drain, and the gate wiring 2 and the - branch 7 of base wiring 7
The second overlap part with a is used as the source, and the gate wiring 2 located between the first overlap part and the second overlap part is used as the gate. This is what I did. So like this
Since a drain is provided on the branch portion 7a of the gate wire 7, even if a disconnection occurs at the intersection of the branch portion 7a and the gate wire 2, a line defect will not occur as in the conventional case, and the drain corresponding to the branch portion 7a will not occur. Point defects occur only at the pixel electrode 8. In addition, source wiring in a narrow sense (source wiring 7 other than branch 7a)
) The shape (width, length, etc.) of the branch portion 7a can be arbitrarily selected without being limited to the line width, etc. of the branch portion 7a, increasing the degree of freedom in device formation.

In both the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 2, the gate electrode 2 is provided with a branch portion 2a.

The third embodiment shown in FIG.
The pixel electrode 8 is provided with a branch portion 2a, and the pixel electrode 8 is provided with a branch portion 8a. By providing the branch portion 8a on the pixel electrode 8, uniform transistor characteristics can be obtained even if the alignment of the photomask is slightly misaligned.

The fourth embodiment shown in FIG.
In this case, the pixel electrode 8 is provided with a branch portion 8a without specifically providing a branch portion on the pixel electrode 8.

In the fifth embodiment shown in FIG. 5, two pixel electrodes 8 adjacent to each other constitute one display color (R, G, B).

[0023]

[Effects of the Invention] According to the present invention, a branch portion is formed on the source wire at the same time as the source wire and the pixel electrode are formed, and the overlap portion between the branch portion and the gate wire is used as the source. , it is possible to obtain a thin film transistor array device with a low probability of line defects occurring.

[Brief explanation of the drawing]

FIG. 1 is a first embodiment of the present invention, and is a plan view schematically showing a part of a thin film transistor array.

FIG. 2 is a second embodiment of the present invention, and is a plan view schematically showing a part of a thin film transistor array.

FIG. 3 is a plan view schematically showing a part of a thin film transistor array, which is a third embodiment of the present invention.

FIG. 4 is a fourth embodiment of the present invention, and is a plan view schematically showing a part of a thin film transistor array.

FIG. 5 is a plan view schematically showing a part of a thin film transistor array, which is a fifth embodiment of the present invention.

FIG. 6 schematically shows a method of manufacturing a thin film transistor array device according to the present invention and a conventional method.

FIG. 7 is a plan view of a conventional example and corresponds to FIG. 6(F).

[Explanation of symbols]

1...Transparent substrate 2...Gate wiring 3...Gate insulating layer 4...Intrinsic silicon layer 5... Impurity silicon layer 6...Photoresist 7...Source wiring 7a...branch 8...Pixel electrode

Claims (1)

[Claims] 1. A step of forming a plurality of gate wirings on the surface of a transparent substrate, and a step of forming a gate insulating layer on the transparent substrate on which the gate wirings are formed. , the above game
a step of forming an intrinsic silicon layer on the insulating layer; a step of forming an impurity silicon layer containing an impurity as a donor or an acceptor on the intrinsic silicon layer; and forming a photoresist on the impurity silicon layer. a step of exposing the photoresist from the back side of the light-transmitting substrate; developing the exposed photoresist;
A step of forming a photoresist pattern having substantially the same planar shape as the gate wiring, and etching the impurity silicon layer and the intrinsic silicon layer using the photoresist pattern as a mask to form the gate wiring. a step of forming an impurity silicon layer pattern and an intrinsic silicon layer pattern having substantially the same planar shape, and a step of forming a transparent conductive layer on the gate insulating layer and the impurity silicon layer pattern. , a transparent conductive layer that selectively removes the transparent conductive layer to form a plurality of source wirings that intersect with the gate wiring and a plurality of pixel electrodes that overlap the gate wiring; In the method for manufacturing a thin film transistor array device comprising a removing step and a step of etching the impurity silicon layer pattern using the source wiring and the pixel electrode as a mask, the gate wiring is removed in the transparent conductive layer removing step. A branch portion overlapping the gate wire and the pixel electrode is formed on the source wire, and a first branch portion is formed between the gate wire and the pixel electrode.
The overlap part is used as a drain, the second overlap part between the gate wiring and the branch part is used as a source, and the first overlap part and the second overlap part are used as a source. A method for manufacturing a thin film transistor array device using a gate between the burlap portion and the burlap portion.