JPH04260353A - Semiconductor and manufacture thereof - Google Patents
Semiconductor and manufacture thereofInfo
- Publication number
- JPH04260353A JPH04260353A JP3021756A JP2175691A JPH04260353A JP H04260353 A JPH04260353 A JP H04260353A JP 3021756 A JP3021756 A JP 3021756A JP 2175691 A JP2175691 A JP 2175691A JP H04260353 A JPH04260353 A JP H04260353A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal nitride
- nitride film
- metal
- metal oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims 3
- 239000002184 metal Substances 0.000 claims abstract description 41
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 150000004767 nitrides Chemical class 0.000 claims abstract description 41
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 24
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 23
- 239000012212 insulator Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910000676 Si alloy Inorganic materials 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 13
- 239000010936 titanium Substances 0.000 description 11
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910018125 Al-Si Inorganic materials 0.000 description 3
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 3
- 229910018520 Al—Si Inorganic materials 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は，半導体装置のメモリー
回路などで使用している冗長回路に接続するためのヒュ
ーズの切断方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for cutting a fuse for connection to a redundant circuit used in a memory circuit of a semiconductor device.
【０００２】0002
【従来の技術】近年のメモリー回路では，不良ビットが
あると予備として持っている冗長回路に接続するが，こ
のとき，１０１０Ａ／ｃｍ２ 程度の電流密度で溶断す
るので，ヒューズを構成している多結晶シリコン（ポリ
Ｓｉ）が素子上に飛び散ったり，またヒューズ幅の依存
性が大きいので切断不良といった問題をしばしば引き起
こす。[Prior Art] In recent memory circuits, if there is a defective bit, it is connected to a spare redundant circuit, but at this time, it is blown out at a current density of about 1010 A/cm2, so there are many parts that make up the fuse. This often causes problems such as crystalline silicon (poly-Si) scattering on the device and poor cutting because it is highly dependent on the fuse width.
【０００３】0003
【発明が解決しようとする課題】従って，従来のポリＳ
ｉ膜構造のヒューズの切断ではポリＳｉが飛び散ったり
，ポリＳｉ膜のヒューズ幅のばらつきによる切断不良が
発生していたため，歩留りの低下につながっていた。[Problem to be solved by the invention] Therefore, the conventional polyS
When cutting fuses with an i-film structure, poly-Si scatters and cutting failures occur due to variations in the fuse width of the poly-Si film, leading to lower yields.
【０００４】これらの問題を解決するために，溶断時の
ヒューズ材料の飛び散りや，ヒューズ幅のばらつきの少
ない材料・方法によるヒューズを得ることを目的として
本発明は提供されるものである。[0004] In order to solve these problems, the present invention is provided with the object of obtaining a fuse using a material and method that causes less scattering of the fuse material when blown and less variation in fuse width.
【０００５】[0005]
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１は半導体基板，２は絶縁物，
３は金属窒化膜，３１は第１の金属窒化膜，３２は第１
の金属窒化膜，４１は第１の金属酸化膜， ４２は第２
の金属酸化膜，５は導電層，６はパターン幅である。[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulator,
3 is a metal nitride film, 31 is a first metal nitride film, and 32 is a first metal nitride film.
, 41 is the first metal oxide film, 42 is the second metal nitride film, and 42 is the second metal oxide film.
, 5 is a conductive layer, and 6 is a pattern width.
【０００６】上記の問題点を解決するためには， 図１
（ａ），（ｂ）に示すように，従来のポリＳｉ膜による
ヒューズに代えて，アルミニウム（Ａｌ）−シリコン（
Ｓｉ）合金膜等の導電層５を使用し，かつ，下地膜の種
類の相違を利用して， 溶断部分にＳｉノジュールを発
生させて切断することにより，あるいは，図１（ｃ），
（ｄ）に示すように，エレクトロマイグレーションを利
用して溶断部分を切断する。[0006] In order to solve the above problems, Fig. 1
As shown in (a) and (b), instead of the conventional poly-Si film fuse, aluminum (Al)-silicon (
By using a conductive layer 5 such as a Si) alloy film and by utilizing the difference in the type of base film to generate Si nodules at the fused part, or by cutting by generating Si nodules in the fused part,
As shown in (d), the fused portion is cut using electromigration.
【０００７】これは， 第１の例では，Ｓｉを１％以上
含んだＡｌ膜において，ＲＦスパッタ等により表面の自
然酸化膜を除去した正常な金属窒化膜上では， 二酸化
シリコン（ＳｉＯ２）膜等の絶縁膜に比べてＳｉが凝集
するいわゆるＳｉノジュールが出来にくいことを利用す
る。In the first example, in an Al film containing 1% or more of Si, a silicon dioxide (SiO2) film, etc. This method takes advantage of the fact that so-called Si nodules, in which Si aggregates, are less likely to form compared to other insulating films.
【０００８】また， 第２の例では，同様に， Ｓｉを
１％以上含んだＡｌ膜において，金属窒化膜の表面上に
金属酸化膜が僅かでも存在する場合には， エレクトロ
マイグレーションが生じ難いことを利用する。[0008] In the second example, similarly, in an Al film containing 1% or more of Si, if even a small amount of metal oxide film exists on the surface of the metal nitride film, electromigration is difficult to occur. Use.
【０００９】即ち，本発明の目的は，半導体装置のヒュ
ーズ領域を図１（ａ）に平面図で，図１（ｂ）に断面図
で示すように，絶縁物２表面に，互いに電気的に隔絶さ
れた第１の金属窒化膜３１および第２の金属窒化膜３２
を被着形成する工程と，次いで， 導電層５を， 該第
１の金属窒化膜３１表面から該絶縁物２表面を経由して
該第２の金属窒化膜３２で挟まれた該絶縁物２表面にお
いて， 通電によって溶断可能なパターン幅６に形成す
ることにより，或いは，半導体装置のヒューズ領域を図
１（ｃ）に平面図で，図１（ｄ）に断面図で示すように
，絶縁物２表面に，金属窒化膜３を被覆する工程と，該
金属窒化膜３表面に， 互いに電気的に隔絶された第１
の金属酸化物３１および第２の金属酸化膜３２を被着形
成する工程と，次いで， 導電層５を， 該第１の金属
酸化膜４１表面から該金属窒化膜３表面を経由して該第
２の金属酸化膜４２で挟まれた該金属窒化膜３表面にお
いて， 通電によって溶断可能なパターン幅６に形成す
ることにより，また，前記導電層５は，Ｓｉが１％以上
含まれているＡｌーＳｉ合金膜であることにより達成さ
れる。That is, an object of the present invention is to electrically connect the fuse region of a semiconductor device to the surface of an insulator 2, as shown in a plan view in FIG. 1(a) and in a cross-sectional view in FIG. 1(b). First metal nitride film 31 and second metal nitride film 32 isolated
Next, a conductive layer 5 is formed from the surface of the first metal nitride film 31 to the insulator 2 sandwiched between the second metal nitride film 32 via the surface of the insulator 2. By forming a pattern width 6 on the surface that can be blown by applying current, or by forming an insulating material in the fuse region of a semiconductor device, as shown in a plan view in FIG. 1(c) and in a cross-sectional view in FIG. 1(d), a step of coating a metal nitride film 3 on the second surface, and a step of coating a first metal nitride film 3 on the surface of the metal nitride film 3;
a step of depositing a metal oxide 31 and a second metal oxide film 32, and then a conductive layer 5 is formed from the surface of the first metal oxide film 41 through the surface of the metal nitride film 3, On the surface of the metal nitride film 3 sandwiched between the metal oxide films 42 of No. 2, the conductive layer 5 is formed to have a pattern width 6 that can be fused by energization. -Achieved by using a Si alloy film.
【００１０】0010
【作用】本発明では，ヒューズの一部に Ａｌ−Ｓｉ合
金膜等の導電層を有することにより，下地絶縁膜と金属
窒化膜の相違による Ａｌ−Ｓｉ合金膜のＳｉノジュー
ル或いはエレクトロマイグレーションの相違を利用して
，ヒューズを溶断することができる。[Operation] In the present invention, by having a conductive layer such as an Al-Si alloy film in a part of the fuse, the difference in Si nodules or electromigration of the Al-Si alloy film due to the difference between the underlying insulating film and the metal nitride film can be suppressed. This can be used to blow the fuse.
【００１１】[0011]
【実施例】図２，図３は本発明の第１，第２の実施例の
工程順模式断面図である。図において， ７はＳｉ基板
， ８はＳｉＯ２膜， ９は窒化チタン（ＴｉＮ） 膜
， ９１は第１のＴｉＮ膜， ９２は第２の ＴｉＮ膜
， １０１は第１のはチタン（Ｔｉ）酸化膜， １
０２は第２のはＴｉ酸化膜， １１は Ａｌ−Ｓｉ膜，
１２はパターン幅， １３は溶断部分である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2 and 3 are schematic sectional views in the order of steps of the first and second embodiments of the present invention. In the figure, 7 is a Si substrate, 8 is a SiO2 film, 9 is a titanium nitride (TiN) film, 91 is a first TiN film, 92 is a second TiN film, and 101 is a first titanium (Ti) oxide film. , 1
02 is the second Ti oxide film, 11 is the Al-Si film,
12 is the pattern width, and 13 is the fused portion.
【００１２】図２により，本発明の第１の実施例につい
て説明する。左側に断面図，右側に平面図でヒューズ領
域を示す。図２（ａ）に示すように，半導体基板として
使用したＳｉ基板７上に，絶縁物として，熱酸化法によ
り ６，０００Åの厚さのＳｉＯ２膜８を被覆する。A first embodiment of the present invention will be explained with reference to FIG. The fuse area is shown in a cross-sectional view on the left and a plan view on the right. As shown in FIG. 2(a), a SiO2 film 8 with a thickness of 6,000 Å is coated as an insulator on the Si substrate 7 used as the semiconductor substrate by thermal oxidation.
【００１３】そして， ＳｉＯ２膜８の上にスパッタ法
により ＴｉＮ膜９を １，０００Åの厚さに被覆し図
示しないレジスト膜を ８，０００Åの厚さに塗布し，
マスクを用いてパタニングし，隙間１２を挟んで相対
する第１の ＴｉＮ膜９１と第２の ＴｉＮ膜９２を形
成する。[0013] Then, a TiN film 9 was coated on the SiO2 film 8 to a thickness of 1,000 Å by sputtering, and a resist film (not shown) was applied to a thickness of 8,000 Å.
Patterning is performed using a mask to form a first TiN film 91 and a second TiN film 92 facing each other with a gap 12 in between.
【００１４】次に， 図２（ｂ）に示すように，ＴｉＮ
膜９をＲＦスパッタエッチングにより， ５０Å程表
面をエッチングした後， スパッタ法により１％のＳｉ
を含んだ Ａｌ−Ｓｉ膜１１を１μｍの厚さに被覆しパ
タニングしてヒューズを形成する。Next, as shown in FIG. 2(b), TiN
After etching the surface of film 9 to about 50 Å by RF sputter etching, 1% Si was etched by sputtering.
An Al--Si film 11 containing 1 μm is coated and patterned to form a fuse.
【００１５】そして，冗長回路の使用に際して，図２（
ｃ）に溶断部分１３として示すように，所定のヒューズ
に電流を流して，第１のＴｉＮ 膜９１と第２の Ｔｉ
Ｎ膜９２の間のパターン幅１２上の Ａｌ−Ｓｉ膜１１
を溶断する。[0015] When using a redundant circuit, FIG.
As shown as the blown portion 13 in c), by passing a current through a predetermined fuse, the first TiN film 91 and the second Ti
Al-Si film 11 on pattern width 12 between N films 92
fuse.
【００１６】図３により，本発明の第２の実施例につい
て説明する。左側に断面図，右側に平面図でヒューズ領
域を示す。図３（ａ）に示すように，Ｓｉ基板７上に，
熱酸化法により ６，０００Åの厚さに， ＳｉＯ２膜
８を被覆する。A second embodiment of the present invention will be explained with reference to FIG. The fuse area is shown in a cross-sectional view on the left and a plan view on the right. As shown in FIG. 3(a), on the Si substrate 7,
A SiO2 film 8 is coated to a thickness of 6,000 Å by thermal oxidation.
【００１７】そして， ＳｉＯ２膜８の上にスパッタ法
により ＴｉＮ膜９を １，０００Åの厚さに被覆する
。続いて， 酸素（０２）雰囲気中，４５０℃で３０分
の熱処理を行い， ＴｉＮ膜９の表面に極く薄く１０Å
程度のＴｉ酸化膜 （ＴｉＮｘＯｙ ，恐らく， 極く
表面はＴｉＯ２膜） １０を形成する。[0017] Then, a TiN film 9 is coated on the SiO2 film 8 to a thickness of 1,000 Å by sputtering. Subsequently, heat treatment was performed at 450°C for 30 minutes in an oxygen (02) atmosphere to form a very thin layer of 10 Å on the surface of the TiN film 9.
A Ti oxide film (TiNxOy, probably a TiO2 film on the very surface) 10 is formed.
【００１８】次に， 図示しないレジスト膜を １，０
００Åの厚さに塗布し， マスクを用いてパタニングし
，弗化炭素系のガスを用いてこのＴｉ酸化膜のドライエ
ッチングを行い， パターン幅１２で隔絶する第１のＴ
ｉ酸化膜１０１ と第２のＴｉ酸化膜１０２ を形成す
る。Next, apply a resist film (not shown) to 1,0
The Ti oxide film was coated to a thickness of 0.00 Å, patterned using a mask, and dry etched using a carbon fluoride gas to form first T oxide films separated by a pattern width of 12.
An i oxide film 101 and a second Ti oxide film 102 are formed.
【００１９】次に， 図３（ｂ）に示すように，Ｓｉ基
板７上に，スパッタ法により１％のＳｉを含んだ Ａｌ
−Ｓｉ膜１１を１μｍの厚さに被覆しパタニングしてヒ
ューズを形成する。そして，冗長回路の使用に際して，
図３（ｃ）に溶断部分１３として示すように，所定のヒ
ューズに電流を流して，第１のＴｉ酸化膜１０１ と第
２のＴｉ酸化膜１０２ の間のパターン幅１２上で Ａ
ｌ−Ｓｉ膜１１を溶断する。Next, as shown in FIG. 3(b), Al containing 1% Si is deposited on the Si substrate 7 by sputtering.
- A fuse is formed by coating and patterning a Si film 11 with a thickness of 1 μm. And when using redundant circuits,
As shown as the blown portion 13 in FIG. 3(c), a current is applied to a predetermined fuse to cause A to flow over the pattern width 12 between the first Ti oxide film 101 and the second Ti oxide film 102.
The l-Si film 11 is fused.
【００２０】[0020]
【発明の効果】以上説明したように， 本発明のように
，半導体装置内のヒューズをＡｌーＳｉ合金膜で形成し
，Ｓｉノジュール，エレクトロマイグレーションを利用
して簡単にかつ安定して切断することが可能となる。[Effects of the Invention] As explained above, according to the present invention, a fuse in a semiconductor device is formed of an Al-Si alloy film and can be easily and stably blown using Si nodules and electromigration. becomes possible.
【図１】 本発明の原理説明図[Figure 1] Diagram explaining the principle of the present invention
【図２】 本発明の第１の実施例の工程順模式断面図
[Fig. 2] Schematic sectional view of the process order of the first embodiment of the present invention
【図３】 本発明の第２の実施例の工程順模式断面図
[Figure 3] Schematic sectional view of the process order of the second embodiment of the present invention
１ 半導体基板 ２ 絶縁物 ３ 金属窒化膜 ３１ 第１の金属窒化膜 ３２ 第２の金属窒化膜 ４１ 第１の金属酸化膜 ４２ 第２の金属酸化膜 ５ 導電層 ６ パターン幅 ７ Ｓｉ基板 ８ ＳｉＯ２膜 ９ ＴｉＮ膜 ９１ 第１の ＴｉＮ膜 ９２ 第２の ＴｉＮ膜 １０１ 第１のＴｉ酸化膜 １０２ 第２のＴｉ酸化膜 １１ Ａｌ−Ｓｉ 膜 １２ パターン幅 １３ 溶断部分 1 Semiconductor substrate 2 Insulator 3 Metal nitride film 31 First metal nitride film 32 Second metal nitride film 41 First metal oxide film 42 Second metal oxide film 5 Conductive layer 6 Pattern width 7 Si substrate 8 SiO2 film 9 TiN film 91 First TiN film 92 Second TiN film 101 First Ti oxide film 102 Second Ti oxide film 11 Al-Si film 12 Pattern width 13 Fused part
Claims (5)
に隔絶された第１の金属窒化膜（３１）および第２の金
属窒化膜（３２）を被着形成する工程と，次いで， 導
電層（５） を， 該第１の金属窒化膜（３１）表面か
ら該絶縁物（２） 表面を経由して該第２の金属窒化膜
（３２）で挟まれた該絶縁物（２） 表面において，
通電によって溶断可能なパターン幅（６） に形成する
工程とを有する半導体装置の製造方法。[Claim 1] A step of depositing a first metal nitride film (31) and a second metal nitride film (32) electrically isolated from each other on the surface of the insulator (2), and then forming a conductive film. layer (5) from the surface of the first metal nitride film (31) to the surface of the insulator (2) sandwiched between the second metal nitride film (32) via the surface of the insulator (2). In,
A method for manufacturing a semiconductor device, comprising the step of forming a pattern width (6) that can be blown out by energization.
３） を被覆する工程と，該金属窒化膜（３） 表面に
， 互いに電気的に隔絶された第１の金属酸化物（３１
）および第２の金属酸化膜（３２）を被着形成する工程
と，次いで， 導電層（５） を， 該第１の金属酸化
膜（４１）表面から該金属窒化膜（３） 表面を経由し
て該第２の金属酸化膜（４２）で挟まれた該金属窒化膜
（３） 表面において，通電によって溶断可能なパター
ン幅（６） に形成する工程とを有する半導体装置の製
造方法。[Claim 2] A metal nitride film (
3) and coating the surface of the metal nitride film (3) with a first metal oxide (31) electrically isolated from each other.
) and a second metal oxide film (32), and then a conductive layer (5) is formed from the surface of the first metal oxide film (41) through the surface of the metal nitride film (3). and forming a pattern width (6) on the surface of the metal nitride film (3) sandwiched between the second metal oxide films (42), which can be fused by electricity.
％以上含まれているアルミニウムーシリコン合金膜であ
ることを特徴とする請求項１，或いは請求項２記載の半
導体装置の製造方法。[Claim 3] The conductive layer (5) is made of silicon.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the film is an aluminum-silicon alloy film containing % or more of aluminum.
に隔絶されるように被着形成された第１の金属窒化膜（
３１）および第２の金属窒化膜（３２）と，該第１の金
属窒化膜（３１）表面と該第２の金属窒化膜（３２）と
の間を電気的に接続するように，かつ該第１の金属窒化
膜（３１）と該第２の金属窒化膜（３２）との間におい
て，通電によって溶断可能なパターン幅（６） に形成
された導電層（５） を有する半導体装置。4. Insulator (2) A first metal nitride film (2) deposited on the surface so as to be electrically isolated from each other.
31) and a second metal nitride film (32), so as to electrically connect between the surface of the first metal nitride film (31) and the second metal nitride film (32), and the second metal nitride film (32). A semiconductor device having a conductive layer (5) formed between a first metal nitride film (31) and the second metal nitride film (32) to have a pattern width (6) that can be fused by electricity.
気的に隔絶されるように被着形成された第１の金属酸化
膜（４１）および第２の金属酸化膜（４２）と，該第１
の金属酸化膜（４１）表面と該第２の金属酸化膜（４２
）との間を電気的に接続するように，かつ該第１の金属
酸化膜（４１）と該第２の金属酸化膜（４２）との間に
おいて，通電によって溶断可能なパターン幅（６） に
形成された導電層（５） を有する半導体装置。5. Metal nitride film (3) A first metal oxide film (41) and a second metal oxide film (42) that are deposited on the surface so as to be electrically isolated from each other; 1st
The surface of the metal oxide film (41) and the second metal oxide film (42)
), and between the first metal oxide film (41) and the second metal oxide film (42), a pattern width (6) that can be fused by energization. A semiconductor device having a conductive layer (5) formed in a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3021756A JPH04260353A (en) | 1991-02-15 | 1991-02-15 | Semiconductor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3021756A JPH04260353A (en) | 1991-02-15 | 1991-02-15 | Semiconductor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04260353A true JPH04260353A (en) | 1992-09-16 |
Family
ID=12063907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3021756A Withdrawn JPH04260353A (en) | 1991-02-15 | 1991-02-15 | Semiconductor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04260353A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094386A (en) * | 1998-08-13 | 2000-07-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device of redundant circuit system |
-
1991
- 1991-02-15 JP JP3021756A patent/JPH04260353A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6094386A (en) * | 1998-08-13 | 2000-07-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device of redundant circuit system |
| US6506634B1 (en) | 1998-08-13 | 2003-01-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for producing same |
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|---|---|---|---|
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