JPH0425559B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a musical tone waveform generating device that generates a plurality of different types of musical tone waveforms through time-sharing processing. BACKGROUND ART Conventionally, an electronic musical instrument has been considered that can generate a plurality of different musical tones at the same time by time-division multiplexing one musical sound waveform generation circuit and assigning different types of waveforms to each of a plurality of sounding channels. For example, Japanese Patent Application Laid-open No. 16616/1983. However, in the above method, a plurality of different tone waveforms generated in each sound generation channel are given as analog voltage values, and are finally added up in analog form and output. As described above, a system that digitally accumulates and outputs the peak values from each sound generation channel has not yet been considered, and even if it were possible, there is still room for various improvements. The present invention has been made in view of the above points, and it is an object of the present invention to realize a musical waveform generator using a digital accumulation method that is more applicable. In order to achieve the above object, the present invention provides a waveform storage means capable of storing plural types of arbitrary tone waveform data, and stores the peak value of the tone waveform read out in each sound generation channel for each type of waveform. The key point is to digitally accumulate and output the accumulated values for each type of waveform in a time-division manner. Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing the functional blocks of a large-scale integrated circuit (LSI) chip 1 used in this embodiment. In the electronic musical instrument of this embodiment, a musical tone signal is generated by one LSI chip. It is something. Inside this LSI chip 1 is a musical tone generation section 2, which will be described later.
and a control section 3 (detailed explanation of this control section 3 will be omitted). Then, from this control section 3,
In addition to outputting signals for scanning external switches or key switches on the keyboard via bus line _B1 , it also outputs signals or data for specifying addresses to external memory (RAM or ROM). External operation signals from an external switch or key switch, data from an external memory, etc. are input to the control section ₃ via the bus line B2. As a result, the control unit 3 outputs the bus lines B ₁ ,
In accordance with the information output from _B2 , an instruction is sent to the musical tone generating section 2 as to what kind of musical tone should be generated. Therefore, the control section 3 and the musical tone generation section 2 have a data bus (4-bit bus) _D1 in the direction,
A control bus C ₁ (this is a unidirectional bus from the control section 3 to the tone generation section 2) for sending control signals other than data is connected to the control bus C 1 . Then, musical tone output is sent from the musical tone generating section 2 to an external D/A converter via the bus line _B3 . Next, details of the tone generating section 2 will be explained with reference to FIGS. 2A to 2C. In addition, Figure 3 is similar to Figure 2A~
The drawing shows the connection state of C. The musical tone generating section 2 shown in FIGS. 2A to 2C can be roughly divided into the following 10 blocks. First, the general functions of each block will be described. Block 10 is a scale clock generator that generates a scale clock SC CLK which is the basis for generating the assigned pitch. In addition. This scale clock generator 10 performs time-division operation on four channels. Block 20 is a waveform step counter section,
It counts up using the scale clock SC CLK from the scale clock generator 10 and outputs its contents to the waveform RAM section 30. Note that this waveform step counter section 20 also performs time-division operation of four channels. Block 30 is the above-mentioned waveform RAM section which divides the tone waveform into 16 steps and stores the waveform difference value for each step. This waveform RAM section stores two types of waveforms (MAIN/SUB) as described later, and selectively outputs the difference value of one of the waveforms for each channel. Block 40 is a channel control section that controls the musical tone generated from each of the four channels by setting it to one of two types of characteristic musical tones.
This channel control section 40 outputs a control signal.
Output MAIN/SUB, clock φM, φS for each channel. Block 50 is an ADSR register section in which two types of envelope data (MAIN/SUB) are stored in advance. Therefore, one of the envelope data is selected for each channel by the control signal MAIN/SUB output from the channel control section 40. Block 60 is the envelope clock generator.
Based on the envelope data given from the ADSR register section 50, it is sent to the envelope clock section 70 at a predetermined speed. Incidentally, this envelope clock generating section 60 also performs four-channel time-division operation. The block 70 is the above-mentioned envelope counter section, which performs a counting operation using the envelope clock ENV CLK supplied from the envelope clock generating section 60. In addition to supplying the contents to the status register section 80 that stores the envelope de-status, an envelope carry signal ENVCO for changing the status is sent to the envelope status section 80. Of course, this envelope counter section 70
It also performs 4-channel time-division operation. The block 80 is the above-mentioned status register section, which stores the envelope status, and based on this information, selects and controls the data to be output from the ADSR register section 50, as well as controls the start or stop of musical tones. This status register section 80 also performs time-division operation of four channels. Block 90 is the multiplication section described above, and the waveform
The waveform difference value data supplied from the RAM section 30 is multiplied by the envelope data given from the envelope counter section 70, and the resultant data is sent to the accumulating section 100. The block 100 is an accumulator, which obtains amplitude value data at each sample point of the waveform by accumulating the difference value data of the envelope-controlled waveform, and outputs the output from an external D/D.
The A converter is supplied via bus line _B3 . In addition, in order to be able to externally control the volume ratio of the two types of musical tones (MAIN/SUB), or to further control switching of the external filter (analog circuit) for each of the two types of musical tones, this cumulative The calculation unit 100 divides each period (4 channel time) of the time division process into two and alternately outputs amplitude value data of each type of waveform. Therefore, according to the circuit configuration of the present embodiment, according to the control of the channel control section 40, one of the four channels will play a musical tone with the MAIN characteristic, and the other channels will play the musical tone with the SUB characteristic. It is possible to generate
For example, if the MAIN side is represented by data "1" and the SUB side is represented by data "0", as shown in Table 1, which of the four channels can be used as a musical tone with the characteristics of MAIN? It is possible to variably control whether a channel is generated as a musical tone with SUB characteristics.

【table】

[Table] By setting MAIN or SUB, for example, one can be used as a melody sound and the other as an accompaniment sound, or one can be set as an automatic performance sound and the other as a manual performer. If the performance is controlled in step 3, the two types of musical tones can be output in any way within four channels, making it extremely versatile. Next, the detailed configuration of each part will be explained in order. <1> Scale clock generator 10 The scale clock generator 10 includes a scale code register 10-1 and an octave code register 10-2.
The registers 10-1 and 10-2 each consist of a shift register that is shifted by a clock (see FIG. 6a). The scale code register 10-1 performs a 4-bit parallel shift operation in four stages, and the octave code register 10-2 performs a 3-bit parallel shift operation in four stages. The relationship between the scale code and octave code stored in the scale code register 10-1 and octave code register 10-2 and the scale or octave is as shown in Tables 2 and 3.

【table】

【table】

[Table] In Table 2, the special code "1111"
has the function of stopping the output of the scale clock SC CLK, and this special code "1111" is input when no musical tone is to be generated from that channel. A 4-bit scale code is supplied from the control section 3 to the scale code register 10-1 via the data bus _D1 . The 4-bit code is transferred to transfer gates G10-1 and G10-G.
2, G10-3, and G10-4 to the input terminal of the scale code register 10-1. These transfer gates G10-1 to G10-4 (all other transfer gates as well) are opened when the gate voltage is at the High (logical value "1") level. Therefore, from the control unit 3 to the control bus
The control signal SCW supplied via _C1 is LOW level (normally HIGH level, other control signals are exactly the same)
When this happens, the output of the NAND gate NAND10-1 becomes High level, and the transfer gates G10-1 to G10-4 are opened. On the other hand, at that time, this scale code register 10-
The scale code that is generally rescaled from the output terminal of 1 and supplied to the input terminal is transferred from the transfer gate G10-5, G10-6, G10-7, G
10-8 is closed, new contents are written to the scale code register 10-1. Note that each channel is synchronized with _the timing signals t ₁ to _{t 4} shown in FIG. Then, the contents of the scale code register 10-1 are changed. In addition, in the above NAND gate NAND10-1,
A control signal SCR is supplied from the control unit 3 via the control bus _C1 , and this control signal SCR is Low.
When reaching the level, Transfer Gate G10-
1 to G10-4 are opened, and the scale code output from the scale code register 10-1 is transferred to the data bus.
It will be supplied to the control unit 3 via _D1 .
Therefore, in the control section 3, the scale code register 10
This means that the contents of -1 can also be determined. In addition, the octave code register 10-2 is also supplied with an octave code from the control section 3 and written therein, similarly to the scale code register 10-1, and its contents are read out and transferred to the data bus.
It can also be supplied to the control unit 3 via _D1 . That is, transfer gate G10-9, G10
-10, G10-11 is "1" of data bus D ₁ ,
It is connected to the weighting line of "2" and "4", and when the control signal OCW is output or the control signal
When outputting OCR, NAND gate NAND10-2
The output becomes High level, and input/output control to the octave code register 10-2 becomes possible.
Also, transfer gate G10-12, G10
-13, G10-14, control signal OCW is Lew
When the level (usually High level) is reached, the gate is closed, the resacillate loop is cut, and a new octave chord is generated by the above transfer gate G1.
It will be input from 0-9 to G10-10. The contents of the scale code register 10-1 and octave code register 10-2 are supplied to the scale clock generation circuit 10-3. The details of this scale clock generation circuit 10-3 are not shown, but for example,
No. 53-31369 (Japanese Unexamined Patent Publication No. 54-123937, title of invention: "Sound waveform setting method for electronic musical instruments") also discloses a detailed configuration of a circuit similar to this scale clock generating circuit 10-3. There is. That is, this scale clock generation circuit 10-3 internally includes a 4-channel shift register, a matrix circuit (ROM) in which an addend is selected according to a scale code and an octave code,
It has an adder etc. The scale clock generation circuit 10-3 generates a scale clock SC CLK corresponding to the scale code and octave code for each channel. The scale clock SC CLK is then supplied to the waveform step counter section 20, the multiplication section 90, and the accumulation section 100 via the AND gate AND10-1. Furthermore, the output of the NAND gate NAND10-3 whose logical value becomes "0" when the special code "1111" is outputted is applied to one input terminal of the AND gate AND10-1. . Therefore, if no special code is input to the scale code register 10-1, the scale clock given from the scale clock generation circuit 10-3
The AND gate AND10-1 will output SC CLK. This scale clock SC CLK is a clock having a cycle determined for each pitch, and the length of 16 clock pulses corresponds to the cycle of the pitch. Therefore, in the case of the average rate scale, the frequency of the clock SC CLK differs by a factor of N2 between semitones. <2> Waveform step counter section 20 The waveform step counter section 20 includes a waveform step register 20-1 and a half adder 20-2 for incrementing its contents (step data). consists of a shift register that shifts in response to a clock (see FIG. 6a), and performs a four-stage shift operation on four bits in parallel. The waveform step register 20-1 is set to "0" to "0" to the waveform RAM section 30.
Specify the 16-step address of "15". Further, its contents are incremented by the scale clock SC CLK supplied from the scale clock generation path 10 being supplied to the carry input terminal Cin of the half adder 20-2. A control signal is sent to the waveform step counter section 20 from the control section 3 via the control bus _C1 .
STW and control signal STR are supplied. This control signal STW is normally a high level signal, and transfers the step data output from the output terminal of the waveform step register 20-1 to the transfer gate G.
20-1, G20-2, G20-3, G20-
4, and is supplied to the half adder 20-2 to form a resacillate loop, but this control signal
When STW is set as a low level signal,
The above transfer gates G20-1 to G20-4
is closed, transfer gates G20-5 and G20- connected to NAND gate NAND20-1
6, G20-7 and G20-8 are opened. Therefore, the 4-bit data given from the control section 3 via the data bus _D1 can be written as waveform step data. In that case, the control unit 3
are the timing signals t ₁ to t shown in FIG. 6 g to j.
t ₄ allows you to control which channel is selected. Further, the control signal STR is normally a high level signal, but when this signal is set to low level, the transfer gates G20-5 to G20-
8 is opened, and the step data from the waveform step register 20-1 is sent to the control section 3 via the data bus _D1 .
It is possible to determine what step the specified channel is at. <3> Waveform RAM section 30 The waveform RAM section 30 includes a waveform RAM section 30-1.
has. This waveform RAM 30-1 is set to input the difference value of two types (MAIN/SUB) of waveforms (one step is expressed by 3 bits) divided into 16 steps, and the waveform step register 2
Corresponding data is read out by the step data "0" to "15" applied from the output terminals 0-1 and the signal MAIN/SUB from the channel control section 40. That is, this waveform RAM section 30-1 has 2 (types)
× 16 (steps) × 3 (bits) = 96 bit capacity
This waveform RAM section 30-1 has address terminals A ₁ , A ₂ , A ₄ , A ₈ as well as
Has MAIN/SUB, I ₁ as data input terminal,
Has I ₂ and I ₃ , and R/W as read/write terminals.
has. When writing a predetermined waveform from the control unit 3 to this waveform RAM 30-1, first, the data input terminal I ₁ ,
For I ₂ and I ₃ , "1", "2" of data bus D ₁ ,
The data is applied via a line with a weight of "4". Then, when the control signal R/W is set to Low level, the address given from the waveform step register 20-1 is used, and the signal MAIN/W supplied from the channel control section 40, which will be described later, is input.
The above waveform will be written in the type of waveform area selected by SUB. Therefore, when writing predetermined data to this waveform RAM 30-1, it is necessary to specify in advance the area in which the contents of the waveform step register 20-1 or the contents of the timbre control register 40-1 in the channel control section 40 are to be written. The control signals STW and W/SW from the control unit 3 and the data on the data bus _D1 are rewritten in advance, and the above waveform is sequentially created using the data.
All you have to do is specify the address of RAM30-1. That is, to explain the waveform data writing operation in detail with reference to FIG. A special code "1111" is applied through the weighted lines of " ₁ ", "2", "4", and "8" of D1 (processing of step _S1 ). At the same time, the control section 3 sets the control signal SCW to a low level (step S ₂ ). As a result, the special code "1111" is input to the scale code register via the transfer gates G10-1 to G10-4 at the timing of a certain channel (the timing of all channels may be used), and is thereafter recirculated. In response to this, the scale clock SC CLK is no longer output from the AND gate AND10-1 at the timing for the channel. Next, the processes of steps S ₃ and S ₄ are executed, and in accordance with the tone selection instruction from the external operation switch, the control section ₃ sets the logic value [0] (SUB information) or logic value "1")) is applied, and the control signal M/SW is set to Low level. As a result, the above MAIN/SUB information is transferred to the transfer gate G.
The signal is input to the timbre control register 40-1 via the channel 40-1 at the timing of the above channel, and is thereafter recirculated. And this MAIN/SUB
The information is the input terminal of the waveform RAM section 30-1.
Applied to MAIN/SUB. Next, steps _S5 to _S9 of the "0" step waveform data writing process are executed. That is, data "0000" indicating step data "0" is applied to the data bus _D1 (step _S5 ). At this time, the control section 3 sets the control signal STW to Low level (step S ₆ ). As a result, the above step data becomes “0”.
are transfer gates G20-5 to G20-8,
The signal is input to the waveform step register 20-1 via the half adder 20-2 at the timing of the above channel, and is thereafter recirculated. Next, when 3-bit waveform data is input, it is applied to this waveform data bus _D1 (step _S7 ).
Next, the control section 3 sets the control signal R/W to Low level (step S ₈ ). As a result, the waveform data for step data "0" is placed in the area in the waveform RAM selected by the address given from the waveform step register 20-1 and the signal MAIN/SUB supplied from the timbre control register 40-1. In other words, the area corresponds to the step data "0" of the above channel.
Written to either MAIN/SUB designated area. Next, in the process of step _S9 , it is determined whether writing of waveform data up to step data "15" has been completed or not, and the process returns to step _S5 . Thereafter, in the same way, step data "1" ~
Since the waveform data "15" is written to the waveform RAM 30-1, the processes of steps _S5 to _S9 are repeated under the control of the control section 3. In this way, the data W ₁ to W ₃ written for each step has a 3-bit configuration, the first bit W ₁ and the second bit W ₂ indicating the waveform difference value, and the third bit indicating the difference value of the waveform. W ₃ will indicate the sign "+/-". However, as shown in Table 4, depending on the combination of the first bit W ₁ and the second bit W ₂ .
It will now indicate "0", "1", "2", and "4".

[Table] The waveform difference value data written in this way is the waveform step data supplied from the waveform step register 20-1 and the signal MAIN/SUB supplied from the timbre control register 40-1.
The address is specified by the address, and the corresponding data is sequentially read out. <4> Channel control section 40 As described above, the channel control section 40 has a timbre control register 40-1, and this timbre control register 40-1 has a shift register that is shifted by the clock φ (see FIG. 6a). It consists of a register and performs a four-stage shift operation with one bit of capacitance. This timbre control register 40-1 specifies the characteristics of MAIN if its content is a logical value "1",
A logical value of "0" specifies the characteristics of the SUB. Therefore, this tone control register 40
When rewriting the contents of -1, data bus D ₁
Send that data to the line with weighting "1" and send the control signal M/SW from the control bus _C1.
Output as low level. The above control signal M/SW is a NAND gate NAND
40-1, transfer gate G40
-1 is opened, while tone control register 40-1 is opened.
Transfer gate G40-2 on the recirculating loop is closed. Therefore, the data sent to the data bus _D1 can be written into the timbre control register 40-1. In this case, each channel can be specified in the control section 3 using the timing signals shown in FIGS. 6g to 6j, so that each channel can be discriminated. Furthermore, in the control section 3, the timbre control register 40-
The MAIN/SUB information written to 1 can be read by setting the control signal M/SR to low level, and its output is obtained on the weighted `` ₁ '' line of the data bus D1. Now, the case where the data shown in Table 5 is written into the timbre control register 40-1 will be described below.

[Table] As a result, the signal MAIN/SUB output from the audio control register 40-1 becomes as shown in FIG. 6b. In addition to the address terminal MAIN/SUB of the waveform RAM 30-1, the signal is directly sent to the AND gate AND40-1 in the channel control section 40.
Inverter 40- to AND gate AND40-2
1, and further supplied to each block to be described later. In addition, the output of the inverter I40-1 is sent as a control signal to the ADSR register section 50.
Supplied as MAIN/SUB. And the above AND gate AND40-1,
AND40-2 has the basic clock φ of FIG. 6a.
The AND gate AND40-1 outputs a clock φM as shown in FIG. 6c, and the AND gate AND40-2 outputs a clock φS as shown in FIG. 6d. Note that the clock φM and the clock φS are supplied to an accumulator 100, etc., which will be described later. <5> ADSR register unit 50 The ADSR register unit 50 includes latches 50-1 and 50-2 that store attack clock selection data that determines the attack time, and a latch 5 that stores decay lock selection data that determines the decay time.
0-3, 50-4, a latch 50-4 for storing release clock selection data that determines the release time;
5, 50-6, a latch 50-7 for storing sustain level data that determines the sustain level;
50-8. And this latch 50-1, 50-3, 50
-5 and 50-7 are latches that store information on the MAIN side of the two types of musical tones (MAIN/SUB), and latches 50-2, 50-4, 50-6, 5
0-8 are latches that store information on the SUB side. Therefore, each of this data determines the shape of the envelope waveform shown in FIG. That is, the attack time (time from the start point to the maximum level point) is determined by the attack clock selection data stored in the latches 50-1 and 50-2, and the attack clock selection data stored in the latches 50-3 and 50-4 determines the attack time (time from the start point to the maximum level point). Decay time (time from maximum level point to sustain level) depending on selected data
is determined, and the release time (time from the sustain level to the end point of sound generation) is determined by the release clock selection data stored in latches 50-5 and 50-6. Furthermore, latches 50-7, 50
The sustain level is determined by the sustain level data stored in -8. Note that if this sustain level data is set to be the same as the maximum level (as described later, this sustain level data is weighted the same as the upper 4 bits of the envelope data output from the envelope counter section 70). , an organ-like envelope can be added, and if this sustain level data is kept the same as the minimum level (0 level), a string-like envelope can be added, as shown in Figure 5. By setting the sustain level to such a level, you can add an envelope with attack, decay, sustain, and release changes (status). Next, the case where each data is set in the latches 50-1 to 50-8 will be explained. First, when inputting the attack clock selection data to the latches 50-1 and 50-2, the control section 3 outputs SUB data to the data bus _D1 . and,
The data is latched 50- by clock φTA.
Set to 1. Note that this clock φTA is a clock given from the control section 3, and the latch 50-
1 and 50-2. Next, the control unit 3 outputs MAIN data to the data bus _D1 . And by clock φTA,
Set that data to latch 50-1, and also set the SUB data that was already input to latch 50-1.
data is set in latch 50-2. In this way, the MAIN attack clock selection data is transferred to the latch 50-1, and the data is transferred to the latch 50-2.
Set the SUB attack clock selection data to . Further, when setting the decay clock selection data to the latches 50-3 and 50-4, it can be done in the same manner as described above, but in this case, the control unit 3 outputs φTD as the read clock to the latches 50-3 and 50-4.
4 is supplied. Furthermore, release clock selection data is applied to latches 50-5 and 50-6, and release clock selection data is applied to latches 50-7 and 50-8.
When setting sustain level data to
and clock φTR to latches 50-7 and 50-8.
supply. As described above, each latch 50-1 to 50-8
The data stored in is based on the signal supplied from the channel control section 40, the signal ATT inputted from the status register section 80 described above,
Selective output is performed using DEC and REL. That is, the output of latch 50-1 is output from transfer gates G50-1, G50-2, G50-3, and G50-1.
50-4 and further transfer gate G50
-5, G50-6, G50-7, and G50-8 to the envelope clock generator 60. In addition, the output of the latch 50-2 is the transfer gate G50-9, G50-10, G50-
11, via G50-12, transfer gates G50-5, G50-6, G50-7, G50-
8 to an envelope clock generator 60. The above transfer gates G50-1 to G50-
The gate signal No. 4 is a signal obtained by inverting the signal MAIN/SUB via the inverter I50-1. Therefore, when the channel control section 40 specifies the MAIN tone, the transfer gates G50-1 to G50-1 are inverted. G50-4 will be opened. On the contrary, transfer gate G50-9~G50
-12 gate signal is the above signal, therefore, the channel control unit 40
When a musical tone is specified, the transfer gates G50-9 to G50-12 are opened. And transfer gate G50-5~G5
0-8 are signals from the status register section 80
If ATT is supplied, open it. In this way, the attack clock selection data for the musical tones MAIN and SUB stored in the latches 50-1 and 50-2 can be selected only when the envelope status is attack, and moreover, can be selected selectively by the designation of MAIN/SUB. Tsuk generation part 6
It will be supplied to 0. Next, the case where the decay clock selection data stored in the latches 50-3 and 50-4 is supplied to the envelope clock generator 60 will be described. That is, the output of latch 50-3 is transferred to transfer gates G50-13, G50-14, and G50-1.
5. Through G50-16, further transfer gates G50-17, G50-18, G50-19,
It is supplied to envelope clock generator 60 via G50-20. In addition, the output of the latch 50-4 is the transfer gate G50-21, G5
0-22, G50-23, G50-24,
Transfer Gate G50-17, G50-1
8, G50-19, and G50-20 to the envelope clock generator 60. The above transfer gate G50-13~G50
The gate signal -16 is a signal obtained by inverting the above signal via the inverter I50-2, and therefore the channel control section 40
When the MAIN tone is specified, the transfer gates G50-13 to G50-16 are opened. On the other hand, transfer gate G50-21~G5
The gate signals 0-24 are the above signals MAIN/
SUB, therefore, the channel control unit 40
When the musical tone of SUB is specified, the transfer gates G50-21 to G50-24 are opened. And transfer gate G50-17~G
50-20 is a signal from the status register section 80
Open if DEC is supplied. In this way, the decay clock selection data for the musical tones MAIN and SUB stored in the latches 50-3 and 50-4 can be selectively applied to the envelope clock only when the envelope status is Decay, and moreover, according to the designation of MAIN/SUB. Tsuk generation part 6
It will be supplied to 0. Next, the case where the release clock selection data stored in the latches 50-5 and 50-6 is supplied to the envelope clock generator 60 will be explained. That is, the output of latch 50-5 is transferred to transfer gates G50-25, G50-26, G50-2.
7, via G50-28, further transfer gate G50-29, G50-30, G50-31,
It is supplied to the envelope clock generator 60 via G50-32. In addition, the output of the latch 50-6 is the transfer gate G50-33, G5
0-34, G50-35, G50-36,
Furthermore, transfer gate G50-29, G50-
30, G50-31, and G50-32 to the envelope clock generator 60. The above transfer gate G50-25~G50
The gate signal -28 is a signal obtained by inverting the above signal via the inverter I50-3, and therefore the channel control section 40
When the MAIN tone is specified, the transfer gates G50-25 to G50-28 are opened. On the other hand, transfer gate G50-33~G5
The gate signals of 0-36 are the above signals.
SUB, therefore, the channel control unit 40
When the musical tone of SUB is specified, the transfer gates G50-33 to G50-36 are opened. And transfer gate G50-29~G
50-32 are signals from the status register section 80.
Opens if REL is supplied. In this way, the release clock selection data for the musical tones MAIN and SUB stored in the latches 50-5 and 50-6 can be selectively applied to the envelope only when the envelope status is release, and moreover, by specifying MAIN/SUB. Clock generator 60
will be supplied to Next, the sustain level data stored in the latches 50-7 and 50-8 is transferred to the status register section 8.
The case where the signal is supplied to 0 will be explained. That is, the output of latch 50-7 is transferred to transfer gates G50-37, G50-38, and G50-3.
The output of the latch 50-8 is supplied to the status register section 80 via the transfer gates G50-41, G50-42, and G50-40.
It is supplied to the status register unit 80 via G50-43 and G50-44. And the above transfer gate G50-37
~G50-40 gate signal is the above signal
This is a signal obtained by inverting MAIN/SUB via the inverter I50-4. Therefore, when the channel control section 40 specifies the MAIN tone, the transfer gates G50-37 to G50-40
is developed. On the other hand, transfer gate G50-41~G5
The gate signals 0-44 are as described above, and therefore, when the channel control section 40 specifies the SUB tone, the transfer gates G50-41 to G50-44 are opened. In this way, the sustain level data of the musical tones MAIN and SUB stored in the latches 50-7 and 50-8 are selectively supplied to the status register section 80 according to the designation of MAIN/SUB. <6> Envelope clock generation section 60, envelope counter section 70, status register section 80 The musical tone of this embodiment is envelope-controlled by the envelope clock generation section 60, envelope counter section 70, and status register section 80. . Therefore, the envelope clock generator 60
generates an envelope clock ENV CLK at a speed corresponding to the data supplied from the ADSR register section 50 and the signals ATT, DEC, REL, and SUS supplied from the status register section 80 (if the signal SUS is input, (The envelope clock ENV CLK is not generated.) It is supplied to the envelope counter section 70. Although a detailed circuit diagram of the envelope clock generating section 60 is omitted, it corresponds to the time division operation of four channels of other blocks, and generates an envelope clock ENV CLK for each channel. Note that this envelope clock generator 60
A similar circuit is also disclosed in Japanese Patent Application No. 53-31369 (Japanese Unexamined Patent Publication No. 54-123937, title of invention: ``Musical sound waveform setting method in electronic musical instruments''), which the present applicant has already filed. be. The envelope clock ENV CLK generated from the envelope clock generator 60 is
The signal is input to the envelope counter section 70. The detailed circuit configuration of this envelope counter section 70 will be omitted (note that the above-mentioned patent application No. 53-31369
This technique is also disclosed in Japanese Patent Application Laid-Open No. 123937/1983, title of the invention: ``Sound waveform setting method for electronic musical instruments''. ) is an adder, 4 stages of 5
It consists of a shift register that shifts bits in parallel and other gate circuits. Note that the shift register is shifted by a clock φ (see FIG. 6a). In addition, this envelope counter section 70 includes
From the status register section 80, the signal ATT,
DEC, REL, and SUS are given, and it is specified whether to count up (at attack) or count down (at decay or release). The 5-bit output of the envelope counter 70 is supplied to the multiplier 90, and in addition, in order to detect coincidence with the sustain level, the 5-bit output of the envelope counter 70 is supplied with 4-bit output (weighting "2", "4", "8", "16"). is the inclusive NOR gate of the status register section 80.
ENOR80-1, ENOR80-2, ENOR80
-3, supplied to ENOR80-4. Further, the envelope carry (borrow) signal ENVC ₀ from the envelope counter section 70 is supplied to the carry input terminal Ci of the half adder 80-1 in the status register section 80 in order to change the envelope status. Next, details of the status register section 80 will be explained. This status register section 80 has a status register 80-2 and a sustain status register 80-3. This status register 80-2 is set to the clock φ
It is a four-stage 2-bit parallel shift register that shifts at the clock φ (see FIG. 6a).
This is a 4-stage shift register with 1 bit shifted in the 4-stage shift register (see Figure a). The contents of this status register 80-2 and the contents of sustain status register 80-3,
The relationship with envelope status is shown in Table 6.

[Table] As shown in Table 6 and as shown in FIG. determined by. Therefore, in order to change the contents of the status register 80-2 from the clear state to the attack state, in other words, to start playing musical tones, the control signal KEYON is sent from the control section 3.
Set to low level (logical value "0"). Note that this control signal KEYON is at a high level (logical value "1") in a normal state. Then, the control signal KEYON is inverted by the inverter I80-1, and the OR gate OR80
-1, and a signal with a logical value of "1" is supplied to the weighted "1" input terminal of the status register 80-2. On the other hand, the above control signal
Since KEYON is supplied to the AND gate AND80-1, a signal with a logical value of "0" is supplied to the weighted "2" input terminal of the status register 80-2. As a result, the contents of the status register 80-2 become "0, 1" and are set to the attack state. The contents are then sequentially shifted by the clock φ and supplied from the output terminal to the decoder 80-4. Now, when the decoder 80-4 detects the attack state, the signal ATT is transferred to the above-mentioned transfer gates G50-5 to G50.
-8, is supplied to the envelope clock generator 60 and envelope counter 70, and the attack state operation is started. Further, the output of the status register 80-2 is sent via the half adder 80-1 to the OR gate OR80-1 or the OR gate OR80-2.
It will be recirculated to the input terminal via the AND gate AND80-1. Therefore, only the operation of the channel set to the attack state as described above will be explained below, but the other channels also perform operations for envelope control completely independently. Now, for the channels set to the attack state, the envelope counter section 70 sequentially counts up in response to the envelope clock ENV CLK input from the envelope clock generating section 60. Therefore, the output increases sequentially from "00000" and reaches the maximum level "11111" as shown in FIG. And the next envelope clock ENV
When CLK is input, envelope carry signal
The envelope counter unit 70 outputs ENVCO and provides it to the half adder 80-1. As a result, the half adder 80-1 performs a "+1" operation on the current value "01", making the content "10", and the status register 80-2 holds this content cyclically. . The decoder 80-4 detects the decay state and sends the signal DEC to the transfer gates G50-17 to G50-20, the envelope clock generator 60, the envelope counter 70, and the status register 80. The signal is supplied to the AND gate AND80-2 to start the decay state operation. As a result, for the channels set in the decay state, the envelope counter section 70 sequentially performs a countdown operation in response to the envelope clock ENV CLK input from the envelope generation section 60. The output of the envelope counter section 70 is supplied to the multiplication section 90, and the upper bit output is sent to the exclusive NOR gate ENOR80.
-1 to ENOR80-4. This exclusive Noah Gate ENOR80-1~
Sustain level data is supplied from the ADSR register section 50 to the other input terminal of ENOR80-4, and when the contents of all bits match, the exclusive NOR gates ENOR80-1 to ENOR
AND gate AND to which the output of 80-4 is applied
A logical value "1" is output from 80-3. Then, the output of the AND gate AND80-3 is supplied to the AND gate AND80-2, and now all other inputs of the AND gate AND80-2 are "1" (that is, the decoder 80-
4, the signal DEC is given with a logic value of "1", and the output of the sustain status register 80-3 is inverted by the inverter I80-2 and given with a logic value of "1". ) by ORGATE OR80-3
The signal is supplied to the sustain status register 80-3 via the sustain status register 80-3. Therefore, sustain status register 80-
The corresponding channel of No. 3 has a logical value of "1", and its output is supplied as a signal SUS to the envelope clock generating section 60 and envelope counter section 70, so that the envelope data is held at the sustain level. In addition, the output of the sustain status register 80-3 is an AND gate
Supplied to AND80-4, this AND gate
AND80-4 contains the signal of decoder 80-4.
Since REL is supplied via the inverter I80-3, its output has a logical value of "1" and is applied to the input terminal of the sustain status register 80-3 via the OR gate OR80-3. Therefore, the sustain status register 80-
3, a "1" signal indicating the sustain state is cyclically stored in the corresponding channel. The change from this sustain state to the release state is caused by the control signal KEY from the control section 3.
This is done by setting OFF to Low level (logical value "0"). Note that this control signal KEY OFF is
It is at High level (logical value "1") in the normal state. Then, this control signal KEY OFF is inverted by the inverter I80-4 and sent to the OR gate OR8.
0-1, given to OR80-2. Therefore, the contents of the status register 80-2 become "1, 1" and are in the released state, and the signal REL is output from the decoder 80-4. This signal REL is supplied to the transfer gates G50-29 to G50-32, as well as to the envelope clock generator 60 and the envelope counter 70. Further, the signal REL is applied to an AND gate AND80-4 via an inverter I80-3. As a result, the envelope clock generator 60 is given release clock selection data, and the envelope clock generator 60 is given release clock selection data, and the envelope clock generator 60 generates an envelope clock at a speed corresponding to the data.
ENV CLK is applied to the envelope counter section 70, and the envelope counter section 70 starts counting down. Also, sustain status register 80-3
Since the AND gate AND80-4 is closed, the recirculating loop is closed and the logic value "0" is held. The down count continues until the envelope counter section 70 outputs the carry (borrow) signal ENVCO, and the data is transferred to the multiplication section 9.
Applied to 0. And the above carry signal
When ENVCO outputs, the signal is applied to the carry input terminal of half adder 80-1, and the contents of the corresponding channel in status register 80-2 are set to "0, 0". As a result, the musical tone output of that channel will be stopped. From the above explanation, it is understood that envelope data as shown in FIG. 4 is output according to each state of attack, decay, sustain, and release. When the control signal KEY OFF is output from
For example, the status register 80-2 may contain data "0, 1" indicating the attack state or decay state.
Even if "1, 0" is stored, the release state of "1, 1" can be forced, and the release operation will be performed. Note that the above-mentioned signals KEY ON and KEY OFF indicate key-on and key-off in the case of manual performance, and also indicate the start of sound generation and transition to the release state, respectively, in the case of automatic performance. In this way, under the control of the status register section 80, the envelope clock generating section 60 and the envelope counter section 70 come to operate, and sequentially transmit envelope data to the multiplication section 90 in accordance with the time-division operation of four channels. It will start outputting. The control unit 3 also controls the status register 80-
2. The contents of the sustain status register 80-3 can be read to perform processing such as detecting an empty channel. That is, when the control signal ENVR is output as a low level signal from the control section 3,
The output is transferred to transfer gates G80-45, G80-46, G8 via inverter I80-5.
0-47, and this transfer gate G
With the development of 80-45~G8047,
The weighting “1” and “2” lines of the status register 80-2 and the weighting “1” and “2” of the data bus _D1 , respectively,
The data "2" and the contents of the sustain status register 80-3 are output to the weighted "4" line of the data bus _D1 . <7> Multiplication section 90 The multiplication section 90 includes a decoder 90-1 and a shift circuit 90-2. And decoder 90-1
are supplied with waveform difference value data W ₁ and W ₂ output from the waveform RAM unit 30. Using these data W ₁ and W ₂ , outputs in four stages as shown in Table 4 are obtained. That is, if the difference value data W ₁ and W ₂ are "0, 0", no matter what value the envelope data from the envelope counter section 70 is, the output of the logical value "0" is obtained from the multiplication section 90. . That is, the output of "0" from the decoder 90-1 is transferred to the transfer gate G90- in the shift circuit 90-2.
1, G90-2, G90-3, G90-4, G9
0-5, G90-6, and G90-7.
This transfer gate G90-1 to G90-7
One end is applied to the ground level (Low level, logical value "0"), and the other end is supplied to the output lines _L1 to _L7 . Therefore, when the output "0" is obtained from the decoder 90-1, the outputs of all lines _L1 to _L7 are all "0". Further, the output of "1" from the decoder 90-1 is transferred to the transfer gate G90 in the shift circuit 90-2.
-8, G90-9, G90-10, G90-1
1, G90-12, G90-13, G90-14
is applied to The envelope data of the envelope counter section 70 is supplied to one end of the transfer gates G90-8 to G90-12, and the transfer gates G90-13 and G
The ground level is connected to one end of 90-14, and the other end is supplied to output lines _L1 to _L7 . Therefore, when the output "1" is obtained from the decoder 90-1, the envelope data is directly output from the lines _L1 to _L7 . Further, the output "2" of the decoder 90-1 is transferred to the transfer gate G90 in the shift circuit 90-2.
-15, G90-16, G90-17, G90-
18, G90-19, G90-20, G90-2
1. This transfer gate G90-15 is connected to the ground level, and the other end is connected to the line _L1 . Further, one end of the transfer gates G90-16 to G90-20 is connected to the envelope output terminal of the envelope counter section 70, and the other end is connected to the lines _L2 to _L6 .
Furthermore, one end of the transfer gate G90-21 is connected to the ground level, and the other end is connected to the line _L7 . Therefore, when an output "2" is obtained from the decoder 90-1, data with a value obtained by doubling the envelope data (shifted by 1 bit) is output from lines _L1 to _L7 . Further, the output of "4" of the decoder 90-1 is transferred to the transfer gate G90 in the shift circuit 90-2.
-22, G90-23, G90-24, G90-
25, G90-26, G90-27, G90-2
8. One end of the transfer gates G90-22 and G90-23 is connected to the ground level, and the other end is connected to the lines _L1 and _L2 . Also, transfer gate G50-24~
One end of G90-28 is envelope counter section 7
0 envelope output terminal, and the other end is
Connected to lines _L3 to _L7 . Therefore, when the output "4" is obtained from the decoder 90-1, the lines L ₁ to
From _L7 , the envelope data is output approximately four times (shifted by 2 bits). In this way, the waveform difference value data W ₁ , W ₂
is multiplied by the envelope data, and the accumulator 1
00. Note that the transfer gates G90-29 and G90-30 in the multiplication section 90 are opened only when the scale clock SC CLK is generated from the scale clock generation section 10, and the transfer gates G90-29 and G90-30 are opened only when the scale clock SC CLK is generated from the scale clock generation section 10, and the transfer gates _G90-29 and G90-30 are opened only when the scale clock SC CLK is generated from the scale _clock generation section 10. -1, and the multiplier 90 outputs valid data only when the scale clock SC CLK is generated, and at other timings, the multiplier 90 outputs "0". <8> Accumulator 100 The accumulator 100 has two types (MAIN/SUB)
By accumulating the envelope-controlled difference value data of /A converter. Now, as shown in Table 5, channel 1 is
Channels 2 to 4 are MAIN as the SUB musical tone.
The case of outputting as a musical tone will be explained below. That is, the 7-bit data supplied from the multiplication section 90 via lines _L1 to _L7 is sent to the adder 100.
Weighting “1”, “2” among the A input terminals of −1,
Exclusive or gate to terminals "4", "8", "16", "32", "64", EOR100-1, EOR1
00-2, EOR100-3, EOR100-4,
EOR100-5, EOR100-6, EOR100
-7. Also. Each of these exclusive or gates EOR100-1 to EOR10
0-7 other input terminal, input terminal weighting "128", "256", "512" terminal, carry input terminal
The output W ₃ (sign bit) of the waveform RAM 30-1 is supplied to Cin via the transfer gate G100-1. Therefore, from the scale clock generation circuit 10-3,
When the scale clock SC CLK is generated, the waveform
If the output data _W3 of the RAM 30-1 is "0", the adder 100-1 receives the data supplied to the B input terminal (10 bits with weighting "1" to "512") and the data from the multiplier 90. The S output terminal (with weighting "1" to "512") is
If the data _W3 is "1", the logic level of the data supplied from the multiplier 90 is inverted and the value is added "+1".
In other words, the data obtained by inverting the sign of the output data of the multiplier 90 and making it a negative value is sent to the adder 1.
00-1 A input terminal and carry input terminal Din
is added to the data from the other B input terminal and output from the S output terminal. In this way, it is possible to accumulate both positive and negative difference value data in the accumulator 100. Then, the data output from the adder 100-1 is transferred to the transfer gates G100-2 and G10.
0-3, G100-4, G100-5, G100
-6, G100-7, G100-8, G100-
9, applied to G100-10 and G100-11, and the transfer gates G100-2 to G1
The output of 00-11 is the latch 110-2, 100
-3 is applied. Therefore, the output of the carry output terminal Cout of the adder 100-1 is connected to the transfer gates G100-2 to G100-11.
The waveform data _W3 of the waveform RAM 30-1 supplied via the transfer gate G100-12 is supplied to the exclusive gate ENOR100-1, and its output is applied. In other words, this exclusive Noah gate
ENOR100-1 performs processing when the adder 100-1 overflows, and under normal conditions, the transfer gates G100-2 to G1
00-11 is open, but when a positive or negative overflow occurs, the transfer gates G100-2 to G100-11 are closed. And at this overflow, latch 1
Transfer gate G100 is connected so that the output of latch 00-2 or latch 100-3 is again input to latch 100-2 or latch 100-3.
-13, G100-14, G100-15, G1
00-16, G100-17, G100-18,
G100-19, G100-20, G100-2
1, G100-22 is opened. That is, these transfer gates G100-13 to G100-22
Includes the above exclusive Noah Gate ENOR
The output of 100-1 is inverted by inverter 100-1 and applied. The latches 100-2 and 100-3 perform reading operations using clocks φM and φS (see FIGS. 6c and d), respectively, and their memory states are changed as shown in FIGS. 6e and 6f. That will happen. Therefore, in this case, the data on channel 1 is stored in latch 1.
It will be stored in 00-3. The data in the latch 100-2 is transferred to transfer gates G100-23, G100-24, G100- which are controlled to open and close by the signal MAIN/SUB from the channel control unit 40 (see FIG. 6b).
25, G100-26, G100-27, G10
0-28, G100-29, G100-30, G
100-31, G100-32, and is supplied to the B input terminal of the adder 100-1.
A transfer gate G to which a clock tn (see Figure 6k) that inverts the level for each channel is applied.
100-33, G100-34, G100-3
5, G100-36, G100-37, G100
-38, G100-39, G100-40, G1
Latch 10 via 00-41, G100-42
0-4 and clock φn (see Figure 6l).
It is read in. On the other hand, the data in the latch 100-3 is transmitted from the channel control section 40 by the signal MAIN/SUB (FIG. 6b).
reference) is provided by inverting the inverter I100-2.
100-44, G100-45, G100-4
6, G100-47, G100-48, G100
-49, G100-50, G100-51, G1
00-52 to the B input terminal of the adder 100-1.
transfer gate G100-53, G
100-54, G100-55, G100-5
6, G100-57, G100-58, G100
-59, G100-60, G100-61, G1
00-62 and is applied to and read from latch 100-4. As a result, from this latch 100-4, the sixth
As shown in Figure m, each musical tone of MAIN and SUB is alternately synchronized with clock φn (see Figure 6l) and sent to the D/A converter on bus line _B3 (10-bit line).
It will be output via . As described above, when the adder 100-1 overflows, the data before the overflow is stored in the latch 100-2 or the latch 100-2.
3, the above transfer gate G1
The outputs of 00-23 to G100-32 and the outputs of transfer gates G100-43 to G100-52 are the outputs of transfer gates G100-13 to G1.
00-222 is being supplied. As described above, in this accumulation section 100,
The amplitude data of the two types of MAIN/SUB musical tones or the sum value data of the amplitude data of each channel are sent to independent latches 100-2 and 100-3.
The data is then alternately output to the D/A converter, and outside of this LSI chip 1, the alternately output data can be further independently filtered. , the volume ratio can be variably controlled by musical tone MAIN/SUB. Therefore, for example, melody sounds and accompanist sounds, manual performance sounds and automatic performance sounds, and other two systems of musical sounds can be processed independently and externally. In this embodiment, as described above, in an electronic musical instrument that performs time-sharing processing of four channels, the waveform
Arbitrary waveform data can be set in advance in the RAM 30-1, and each channel can be specified as a channel that generates one of two types of musical tones: MAIN/SUB, and waveform or envelope data can be set for each musical tone. can be set arbitrarily,
Since each musical tone can be generated simultaneously, two types of musical tones can be obtained with an extremely small amount of hardware, and the circuit of this embodiment is a one-chip LSI.
This configuration has the advantage that it is also possible to manufacture a very compact electronic musical instrument. In the above embodiment, the present invention is applied to an electronic musical instrument that performs time-sharing processing on four channels, but the present invention may also be applied to an electronic musical instrument that performs time-sharing processing on more or less than four channels. In addition, in the above embodiment, two types of musical tones MAIN/
Although the SUB can be specified for each channel, the present invention can also be applied to a case where it is fixedly set which channel is the MAIN and which channel is the SUB. In that case, for example, should all channels be generated by one tone, or should a fixed sound be generated?
It may also be possible to select and specify whether musical tones are generated from each channel depending on the type of MAIN/SUB. Furthermore, in the above example, there are two types (MAIN/SUB)
Although the case where musical tones are generated has been described, it is also possible to selectively generate more types of musical tones from each channel of time-sharing processing. In addition, in the above embodiment, since two types of musical tones can be controlled outside the LSI, the accumulator 100
Inside is a latch that stores MAIN data,
A latch for storing SUB data is provided independently, and amplitude data of two types of musical tones or sum value data of amplitude data of each channel is supplied to the D/A converter in a time-sharing manner. ,
If such control is not performed externally, the envelope-controlled difference value data of all channels may be accumulated and stored in one latch in sequence. Then, the output of the latch is connected to an external D/A.
By supplying the signal to a converter, it is possible to obtain an amplitude level signal that changes over time or a summation level signal of the amplitude levels of each channel. In addition, in the above embodiment, the scale clock SC CLK is generated according to the pitch of the musical tone, and the address of the waveform is incremented by this clock.
The waveform was read out at each step, but now the phase angle data is selected according to the pitch, and this phase angle data is accumulated for each time-division cycle to specify the phase angle of the waveform. electronic musical instruments, for example, Japanese Patent Publication No. 52-46088 (title of invention: ``electronic musical instruments'',
Of course, the present invention can also be applied to electronic musical instruments such as those disclosed by Nippon Musical Instruments Manufacturing Co., Ltd. (applicant: Nippon Musical Instrument Manufacturing Co., Ltd.); obtain. Further, in the above embodiment, waveform difference value data is stored in the waveform RAM 30-1, but waveform amplitude value data can also be stored, and in that case, the accumulator 100 is not required. In the above embodiment, the waveform and envelope waveform are selected as musical tone characteristics, and two types of musical tones are generated simultaneously by switching between them. It is also possible to change the method for each type, or to change other effects for each type. Furthermore, the present invention can of course be applied to electronic musical instruments that do not perform time-sharing processing as described above. Furthermore, the storage capacity of the waveform RAM is arbitrary. When inputting waveform data to the waveform RAM 30-1, in addition to writing the waveform data stored in the control unit 3, the external
The contents of the ROM can be read out and input, and furthermore, various waveform data can be written using pre-recorded magnetic tape, bar code display, etc., or using a numeric keypad etc.
It is also possible to input from outside. In addition, without departing from the gist of the present invention,
Of course, various applications and modifications are possible. As explained above, the present invention provides a waveform storage means capable of storing multiple types of arbitrary tone waveform data, and digitally stores the peak values of the tone waveforms read out in each sound generation channel for each type of waveform. Since the accumulated values for each type of waveform are output in a time-division manner, it is possible to realize a musical waveform generator using a digital accumulation method with higher applicability.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention. Fig. 1 is a diagram showing the functional blocks of an LSI chip used in the electronic musical instrument of this embodiment, and Figs. 2 A to C show the detailed circuit configuration of the same embodiment. 3 is a diagram showing the connection state of the drawings in FIGS. 2A to C, and FIG. 4 is a diagram showing the connection state of the diagrams of FIGS.
FIG. 5 is a flowchart illustrating the operation when writing waveform data to 1, FIG. 5 is a diagram showing the envelope waveform of this embodiment, and FIG. 6 is a time chart illustrating the operation of this embodiment. 1...LSI chip, 2...music tone generation section, 3...
Control section, 10... Scale clock generation section, 20...
Waveform step counter section, 30...Waveform RAM,
40...Channel control section, 40-1...Tone control register, 50...ADSR register section, 60...
...Envelope clock generation section, 70...Envelope counter section, 80...Status register section, 90...Multiply section, 100...Accumulation section.

Claims (1)

[Scope of Claims] 1. A musical sound waveform data input setting means for inputting and setting musical sound waveform data prior to performance; and a plurality of types of musical sound waveforms having a plurality of memory areas and inputted from the musical sound waveform data inputting and setting means. A waveform storage means capable of storing data, a write control means for controlling writing of the plurality of types of musical waveform data to the waveform storage means, and a plurality of time-division readout channels, the plurality of time-division readout channels having a plurality of time-division readout channels. readout control means for reading out specified types of musical waveform data among the plurality of types of musical waveform data from the waveform storage means by each of the channels, thereby obtaining different types of musical waveform data in a time-divisional manner; and an accumulating means for separately accumulating a plurality of types of musical sound waveform data read from the waveform storage means for each type, and one or more musical tones accumulated for each type by the accumulating means. output means for time-divisionally outputting the accumulated value of the waveform data for each of a plurality of times obtained by dividing the total channel time of the plurality of time-division readout channels by the number of the accumulated values; Characteristic musical waveform generator.