JPH04252371A - Operation analyzer for semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the analyzer capable of executing the semiconductor device modeling without using a large-size computer as well as describing a complicated program. CONSTITUTION:This is the device resolving Poisson formula representing the relational expression between potential and space charge in the semiconductor device modeling. At that time, the division point arrangement (M, N) of the semiconductor device is decided, and the time differentiation of psi(M, N)/ t=lambdapsi(M, N)fpsi(M, N) is conducted until it becomes the normal state by supplying space position dependence to a sensitivity coefficient lambdapsi. Accordingly, a parallel calculation processing processor 16 is used. In this case, the parallel number of the parallel calculation processor 16 can be arbitrarily and variably set.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to semiconductor device modeling.

0002

2. Description of the Related Art Semiconductor device modeling is widely applied to the purpose of simulating characteristics, predicting characteristics, and optimizing design conditions of various semiconductor devices. The outline of the implementation method is as follows.

[0003] Below, Poisson's equation for a stationary problem
fψ=0

...Let us find the solution to (c). For concrete discussion, we will assume a two-dimensional space model below, and define division points (M,
N) is determined, and the discretization formula fψ (M, N) = 0 is obtained by approximating equation (c) by the finite element method or finite element method.

...Rewrite it as (c'). Next, we transform this equation into a variable ψ(M
, N), and the multidimensional simultaneous linear equations derived as a result are solved using a computer, and the variable ψ and function fψ are updated. Perform iterative calculations until convergence to a value.

0004

[Problem to be solved by the invention] Generally, dividing points (M,
For example, the total number of N) is divided into 30 in the horizontal direction and 50 in the vertical direction.
In order to solve multidimensional simultaneous linear equations using the calculation method described above, as in the case of a two-dimensional partitioned model, it is only necessary to obtain a large number of unknown variables ψ defined on each of a total of 1,500 points and use a large computer. However, it was necessary to write a complex calculation program, and device modeling was usually only possible after detailed checks (so-called debugging) were performed until the program was able to operate normally.

The present invention departs from such conventional methods by
The present invention provides an analysis device that can perform semiconductor device modeling without using a large-scale computer or writing complicated programs.

[0006]

[Means for Solving the Problems] A first semiconductor device operation analysis apparatus of the present invention converts a Poisson equation representing a relational expression between electric potential and space charge into a time differential term in semiconductor device modeling.

[0007]

[Math 5] Replaced with the following equation (a) including the sensitivity coefficient λψ,

00
08]

[Mathematical 6] However, fψ=divgrad ψ+(q/ ε)[Γ+n
ie-θψ-nieθ(ψ-V)]


...(b) θ=q/(kT)

...(b') By performing the time differentiation of (a) until the steady state is reached, the steady equation fψ=0

...When finding the solution to (c), the division point arrangement (M, N) of the semiconductor device is determined, and the sensitivity coefficient λ
Giving spatial position dependence to ψ, converting the above equation (a) to the following equation (d),

[0009]

[Formula 7] In a semiconductor device operation analysis apparatus that calculates a solution to equation (a) by time-differentiating equation (d) until it reaches a steady state, a plurality of processors arranged in parallel, Parallel processing control means for processing a plurality of processors in parallel, data exchange means for exchanging data with the processing processors, address supply means for supplying address information to the processing processors, and driving the parallel processing control means. It is characterized by comprising a drive means, and a control means for controlling the data exchange and address supply by controlling the data exchange means and the address supply means, and the number of parallel processing processors can be arbitrarily and variably set. do.

The second analysis device of the present invention has a sensitivity coefficient λψ
If the eigenvalue of the error propagation matrix associated with equation (d) is 1
It is characterized by not exceeding .

The third analysis device of the present invention has a sensitivity coefficient λψ
is given by the following equation (e).

0012

[Math. 8]

[0013]

[Operation] That is, starting from a certain initial state, the variable ψ on the dividing point representing discrete time set on the time axis
and the function fψ are sequentially and iteratively determined while proceeding on the time axis to perform time integral calculations. By taking a sufficiently large number of steps on the time axis, the time derivative d
Assuming that ψ/dt becomes sufficiently small, this fact means that fψ=0 holds true, which means that the predetermined objective has been achieved.

[0014] The details of the above solution have already been disclosed in an earlier application (Japanese Patent Application No. 2-49484, filed March 2, 1990).
I have already mentioned this, so I won't go into it here. In summary, the adoption of this calculation eliminates the need to calculate solutions to large multidimensional simultaneous linear equations, which was essential in conventional solution methods, and the calculation algorithm, and therefore the calculation program that specifically describes it, becomes significantly simpler. . Furthermore, this eliminates the need for large-capacity memory to store a large number of matrix elements, and makes it possible to create a dedicated computing device to perform device modeling, which was considered difficult with conventional methods. becomes.

Various basic forms of such computing devices have already been proposed and detailed in the earlier application (mentioned above). Continuing on from these, the present invention, in carrying out the principles of these basic systems, pays particular attention to the properties of the above-mentioned solution method that are suitable for parallel processing, and aims to exploit the characteristics of this solution method to its limit. This was proposed as a purpose.

That is, the present apparatus is based on the premise that a parallel arithmetic processing processor is used. The minimum number is 1, which is the normal case without parallel processing, and the maximum is the total number of space division points, that is, in the example of 30 x 50 points mentioned above, the total number is 15.
It is assumed that 1500 parallel processing processors corresponding to 00 points are used. In addition, a key feature of this device is that the number of parallel processing processors can be arbitrarily and variably set.

By adding this condition, once the present analysis device is completed, it is possible to arbitrarily increase or decrease the number of parallel processing processors according to the scale of a given problem without changing the design of the device. This makes it versatile enough to meet a wide range of demands. This feature makes this device suitable for use with boards or integrated circuits, especially ASI
C (Application Specific In
When realized in the form of tegrated circuits, no new design is required, which significantly increases the economic efficiency of device development.

[0018] Claims 2 and 3 are characterized in that the above-mentioned maximum points of the present device are given as additional conditions in the same way for a more limited calculation method.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device operation analysis apparatus according to the present invention will be described with reference to FIGS. 1 and 2.

The analysis device of this embodiment includes a personal computer 10, a data control device 12, a binary counter 14, and a plurality of processors 16k (k=1, . . .
n), a connector 32, a parallel processing control device 28, and buses 34, 36a, and 36b.

First, the leftmost personal computer 10
provide the input data provided to the analysis device;
It also plays the role of displaying the solution (output data) of the equation obtained by this analysis device on the display screen in the form of a numerical table or graphic display. Simple calculations on input and output data are also performed if necessary. However, the calculations at this time are executed by inputting them directly on the screen or using a program or software inputted using a storage medium such as a floppy disk, in accordance with the normal usage of a personal computer.

[0022] This personal computer 10 and this analysis device exchange necessary input/output data,
At this time, the personal computer 10 also has an address control function that determines which data is stored at which address.

Next, the data control device 12 directly connected to the personal computer 10 will be explained. The data control device 12 first issues a start/stop command to instruct the analysis device to start and end calculations.

Second, mode setting selects either the normal calculation execution mode or the single-step mode in which calculations are stopped every clock and intermediate calculation results can be checked. The latter is selected when it is necessary to check whether the operation of the device is correct.

Third, the memory address of each processor 16k is set via the buses 34, 36a, and 36b, and the addresses of initial data and data to be updated during calculation are specified.

In addition to the above-mentioned functions, the data control device 12 also generates a clock pulse having a constant frequency such as 10 MHz, and inputs the clock pulse to the binary counter 1.
Send it to 4.

A binary counter 14 placed below the data control device 12 has functions such as controlling a program written in a ROM using a bit pattern, which will be described later.

The number of the plurality of processors 16k can be selected as appropriate depending on the content of the equation to be solved, and can be set by connecting a predetermined number of processors to the connector 32 in parallel. In this way, the feature of the equation analysis apparatus of this embodiment is that the number of processors can be set arbitrarily, and it has the versatility of being usable for solving any equation.

Each processor 16k is connected in parallel to a parallel processing control device 20 via a bus 34, and the parallel processing control device 20 controls each processor 16k in parallel in response to instructions from the binary counter 14.

Next, with reference to FIG. 2, the arithmetic processing unit (processor) 16k, which is the calculation execution section of this analysis apparatus, will be explained. First, in accordance with the spirit of the present invention, as shown in FIG. 1, there are n processors, and 1≦n. Hereinafter, attention will be paid to the processor 161.

First, the bus transceivers 18a and 18b connected to the connector 32 via the data bus 38 are
Data is read into the respective RAMs 20a and 20b on the right, and data is read from the RAMs 20a and 20b. The RAMs 20a and 20b store initial data or data to be updated during calculation.

There are two pairs of the above-mentioned bus transceivers 18a, 18b and RAMs 20a, 20b, and the first pair 18
a, 20a is input A of the arithmetic unit ALU22, which will be described later.
Also, the second set 18b, 20b is also connected to input B.

Next, the ROM 24 stores a calculation procedure written in a bit pattern, that is, a program, and the calculation content to be executed by the entire processor 161 is determined here. The ROM24 receives the clock from the binary counter 14 via the connector 32, and
A program written using a bit pattern of 4 is controlled. The output of the ROM 24 is the output of the RAM 18 mentioned above.
a, 18b, and at the same time, the arithmetic unit ALU (A
The data is also transferred to the (rithmetic logic unit) 22.

In ALU 22, input A and input B
For each, predetermined calculations, such as A±B, A×B, A÷B, etc., are performed. When it is necessary to obtain an exponential function ex, a logarithm calculation log x, etc., these calculations are performed by replacing them with the algebraic calculations of a predetermined procedure written in the ROM 24 described above. In this way, all calculations involving transcendental functions are performed by reducing them to the four arithmetic operations. ALU
22 is sent to the RAM via the bus transceiver 26.
20a and 20b, and also to the parallel processing control device 28 via the data bus 38.

Next, using FIG. 3, the individual processors 16
The equation solving process executed within k will be specifically explained. The analysis apparatus of the present invention can be realized by following the procedure shown in FIG. 3 and performing the calculations shown in this figure using hardware such as a memory chip and an arithmetic processor chip. At this time, the program representing the calculation procedure is stored in, for example, a rewritable memory, that is, an EPROM.
It can be created by writing in the form of a bit command to .

First, input data 30 as shown in the upper left
Prepare. Its contents are primarily physical constants, including the Boltzmann constant k, electron charge q, dielectric constant ε of semiconductor materials, absolute temperature T, θ=q/(kT), and intrinsic electron density ni. It will be done.

Secondly, there is a limit error used to determine the end of calculation, and a proportionality constant ωψ included in the expression of the product of the sensitivity coefficient and the time step δt.

Thirdly, there is the mesh interval. For a two-dimensional problem, if a rectangular mesh as shown in FIG. 4 is adopted, for example, the values for the horizontal interval hx (M) and the vertical interval hy (N) are determined. Furthermore, div, divg
When expressing a differential operator such as rad using a difference approximation formula, two adjacent ones of the above intervals, i.e. hx(M-1
), hx(M) and the interval between the midpoints of hy(N-1), hy(N), so these are h′x(M),
h′y(N), and determine these values in advance. FIG. 5 shows an actual example in which the mesh spacing is determined based on a two-dimensional pn diode model.

Fourth, an impurity doping function Γ, that is, the algebraic sum of the donor concentration as positive and the acceptor concentration as negative, is defined for the entire two-dimensional model shown in FIG.

Fifth, boundary conditions are provided that determine the structure of the device to be analyzed. In the example of FIG. 5, a fixed potential corresponding to each electrode is applied at mesh points on each of the anode and cathode electrodes. Also, the central axis (y = 0 μm)
For example, an object boundary condition is given on each line of the side wall portion (y=3 μm). Furthermore, each point on the upper surface also provides, for example, an object boundary condition. Specifically, in FIG.
Mesh point (1,1) is a point on the anode electrode, mesh point (5,1), (5,2), (5,
3) and (5, 4) are points on the cathode electrode. A predetermined fixed potential is applied to each of these points, such as an anode potential of 0 volts and a cathode potential of +10 volts.

Next, mesh points (2, 1), (3
, 1), and (4, 1) are located on the central axis, object boundary conditions are given for these.

Next, mesh points (1, 2), (1
, 3) are located on the surface of the semiconductor chip, so object boundary conditions are given for these as well in a simple case. Furthermore, in complicated cases, it may be possible to create mesh points in the space outside the semiconductor and add these to the calculations, but these can be easily performed without changing the principle, so the explanation is omitted here. do.

Next, mesh points (2, 4), (3
, 4), and (4, 3) are located on the side wall, so the target conditions are easily given for these as well. Mesh points (
Since points 1 and 4) are located at corners, two points, the left neighbor and the bottom neighbor, are assumed for these as well, and a double target condition is given.

[0044] The remaining mesh points (2, 2), (3
,2),(4,2),(2,3),(3,3),(4,
3) is a point inside the semiconductor, so there are mesh points on the top, bottom, left and right of each point. To classify each mesh point above, for example, define an integer called IBDY (M, N), and for internal points IBDY (M, N) = 1, and on the anode electrode IBDY (M, N) = 2. , IBDY (M, N) = 3 on the cathode 0 electrode, IBDY (M, N) on the central axis
, N) = 4, on the surface IBDY (M, N) = 5, on the sidewalls IBDY (M, N) = 6, at the corner points IBDY (
By making a correspondence such as M, N)=7, the properties of each point can be easily recognized.

Sixth, the initial value of the basic variable ψ for starting the calculation is given for all mesh points.

The calculations necessary to prepare the above input data are as follows:
Since it is usually simple and does not involve repeated calculations, it is sufficient to use a personal computer to accomplish the purpose.

Returning to FIG. 3, once the input data is prepared, calculation of the solution to the equation begins. The equation to be solved is the Poisson equation (a), and the fundamental variable is ψ. Below, for this ψ, 4 points above, below, left and right centering on one mesh point
Pay attention to the 5 points. These 5 points (M-1, N)
, (M, N), (M+1, N), (M, N-1), (M
, N+1) is schematically shown in section 40 of FIG.

In the following, a calculation method for updating each potential value at the central point (M, N) by executing time integration using the potential values at these five points will be explained. Note that the calculations proceed from left to right in the diagram.

ψ(M,N) at the upper left represents the potential on the mesh point, and the points above, below, left and right correspond to the mesh point arrangement in FIG. At this time, if the left neighbor point does not exist, apply the target condition and ψ(M-1
, N) = ψ(M+1, N), and the calculation is performed as if the point to the left existed. If the mesh point is a fixed potential point of the anode or cathode, ψ(M,N) is known and there is no need to perform the following calculations.

Hereinafter, by multiplying the center point and surrounding points by corresponding counts and then performing addition and subtraction, the value of divgrad ψ is determined in step S1.

In the area from the lower left to the center, the second term on the right side of equation (b), that is, (q/ε)[Γ
The value of +nie−θψ−nieθ(ψ−V) is calculated,
By calculating the sum of this and the above divgrad ψ, fψ in equation (b) is found in step S2.

In the bottom row from left to right, the product λδt of the sensitivity coefficient and the time step is calculated. The example in this figure is a concrete draft of equation (e). λδt
Considering the numerical factor ωψ (0<ωψ<1) included in By adding, the updated ψ(M,N) is found. Next, the relative error δψ(M
, N)/ψ(M, N), take the absolute value, compare this with the error limit eps (for example, = 10-6), and if the former is larger than this, the updated ψ(M, Repeat the same calculation as above using N). At this time, ψ of all other mesh points is also updated at the same time.

Otherwise, the calculation of the time integral is considered to have reached a steady state, so the entire calculation is terminated,
Transfer the final result to the output device.

Next, the parallel processing control device 28 of FIG. 1 controls the plurality of processors 161, 161,
162, ...16n. Returning to FIG. 1 below, the specific configuration of the parallel processing control device 28 will be explained. First, the controller 28 controls the processor 16.
Detect how many 1, 162, ...16n there are. For this purpose, for example, the counter may be operated simultaneously with the connection of the connector pin 32. As a result, processors 161, 162, ...16n (n in the figure)
2) are all connected to the main control device 28 by lines including data lines, address lines, and power lines. This device 28 is connected to a general program (specifically, it is written in a PROM or the like in the form of bit signals).

One of the gist of the present invention is to allow the number n to vary. In other words, when the scale of the problem, that is, the total number of mesh points increases, with this device, by increasing the number n, it is possible to obtain a solution in a short time as before, which significantly increases the advantages of using the device. .

Next, the entire mesh points are distributed almost equally to the n processors. For this reason, for example, if the total number of mesh points is NT, and i is an integer 1 greater than the integer part of NT/n, the processor 161 has mesh points 1 to i, the processor 122 has mesh points (i+1) to 2i, . . . processor 16n. -1 has mesh points (n-2)i+1 to (n-1)i processor 16
n has mesh point (n-1)i+1~
It is sufficient to allocate NT. Calculation of this assignment is extremely simple, and therefore, like the preparation of input data, it can be executed in a software program using an input/output device connected to the entire computer, such as a personal computer or a workstation. Alternatively, it is of course possible to provide the above-mentioned allocation function inside the present computing device.

In the above, if you want to use only n' out of n processors for some reason, for example, the number of processors n is larger than the total number of mesh points NT, you can use only n'. Of course, activation is also possible.

Next, in each processor, the above-mentioned FIG.
The calculation shown in the following is performed, but at that time,
As shown in FIG. 1, each processor 161, 162,
...16n includes arithmetic units and a memory (SRA) that stores necessary data during calculations for the assigned mesh points.
M), and each processor from 1 to n has, for example, a basic variable ψ(M,N) on the mesh points for the allocation.
Note that the value of is memorized.

In such a configuration, when executing the calculation shown in FIG. 3 for a current mesh point (M, N), if this point is a fixed boundary point, the potential ψ (M, N) at the same point is all data. Since it is determined at the time of input, there is no need to calculate it again. Therefore, in this case we simply omit the entire calculation.

If the point of interest is an interior point, all four points on the upper, lower, left, and right sides exist around that point, so calculations are performed while referring to the necessary data associated with these four points. At this time, if any of the four points on the top, bottom, left, and right belong to the division in charge of another processor, refer to the data stored in the processor through the data line and address line connected via the connector 32 and parallel processing control device 28. It shall be.

If the point of interest is a point on the central axis (y=0), there are no mesh points to the right of the same point, so
Assuming that an object boundary condition is given to the current point, it is assumed that a point (M-1, N) exists on the right side of the same point, and the variable value on that point is the same as that of the point (M+1, N). shall be equal. Furthermore, if data of adjacent points are stored in another processor, the handling is the same as above.

[0062] The handling when the point of interest has other attributes is similar to the above and can be easily inferred, so the following explanation will be omitted.

Further, a convergence condition is given that determines whether to continue or terminate the iterative calculation, and the absolute value of the variable change at the mesh point calculated in each processor is within a predetermined error limit eps, for example 10- It is determined whether the absolute values of all the changes are less than 6, and if the absolute values of all the changes are less than this, the calculation is terminated and the output data is transferred to the personal computer.

In the manner described above, the present apparatus, which is characterized in that the number of processors is arbitrary and variable, can perform predetermined calculations.

[0065] In the above description, it is assumed that each processor 16k has a ROM inside, and calculations are executed by the program written therein. In this method, the same program must be prepared for all n processors 16k, but since it is generally easy to copy a program written in hardware, this is not possible with this device. There will be no hindrance to implementation.

Separately, as shown in FIG. 2, the program on the ROM in each processor 16k is removed,
Instead, one central control program is prepared in the parallel processing control device 28, and thereby n processors 16k
It is also possible to drive all of them at once.

[0067] In the above explanation, the apparatus according to claim 3 has been taken as an example, but the present invention is not limited to the above embodiment. For example, if the sensitivity coefficient λψ is set so that the eigenvalue of the error propagation matrix associated with equation (d) regarding the sensitivity coefficient λψ does not exceed 1, the motion analysis can be quickly and accurately achieved.

[0068]

As described above, when semiconductor device modeling is performed using the semiconductor device operation analysis apparatus of the present invention, the calculation algorithm is simple and optimal for parallel processing. Furthermore, since the parallel processing processors can be arbitrarily and variably set, the number of processor units can be increased or decreased to optimally deal with the scale of the problem. Therefore, since there is no need to change the basic configuration of the device in terms of design or use, economical efficiency and versatility are significantly increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a semiconductor device analysis apparatus of the present invention.

FIG. 2 is a block diagram of a processor used in the semiconductor device analysis apparatus.

FIG. 3 is a diagram showing a processing flow of the semiconductor device analysis apparatus.

FIG. 4 is a diagram showing an example of mesh spacing used in the semiconductor analysis apparatus of the present invention.

FIG. 5 is a diagram showing an example of boundary conditions that determine a device structure used in the semiconductor analysis apparatus of the present invention.

[Explanation of symbols]

10...Personal computer, 12...Data control device, 14...Binary counter, 16...Processor, 18
a, 18b, 26... bus transceiver, 20a, 20
b...RAM, 22...Arithmetic unit ALU, 24...R
OM, 28... parallel processing control device, 30... input data,
32...Connector.

Claims (3)

[Claims] [Claim 1] In semiconductor device modeling,
Replace the Poisson equation, which expresses the relational expression between potential and space charge, with the following equation (a), which includes the time differential term [Equation 1] and the sensitivity coefficient λψ, and obtain [Equation 2]
] However, fψ=divgrad ψ+(q/ε)[Γ+n
ie-θψ-nieθ(ψ-V)]


...(b) θ=q/(kT)

...(b') By performing the time differentiation of (a) until the steady state is reached, the steady equation fψ=0

...When finding the solution to (c), the division point arrangement (M, N) of the semiconductor device is determined, and the sensitivity coefficient λ
By giving spatial position dependence to ψ and converting the above equation (a) into the following equation (d), [Equation 3] By time-differentiating the above equation (d) until it reaches a steady state, the above equation A semiconductor device operation analysis device for obtaining the solution of (a) includes a plurality of processing processors arranged in parallel, a parallel processing control means for causing the plurality of processing processors to perform parallel processing, and exchanging data with the processing processor. A data exchange means, an address supply means for supplying address information to the processing processor, a drive means for driving the parallel processing control means, and a control unit for controlling the data exchange means and the address supply means to perform data exchange and address 1. A semiconductor device operation analysis apparatus, comprising: a control means for controlling supply, and the number of parallel processing processors can be arbitrarily and variably set. 2. The semiconductor device operation analysis apparatus according to claim 1, wherein the eigenvalue of the error propagation matrix associated with equation (d) regarding the sensitivity coefficient λψ does not exceed 1. 3. The semiconductor device operation analysis apparatus according to claim 1, wherein the sensitivity coefficient λψ is given by the following equation (e). [Math 4]