JPH04240927A - Processing system for tdma reception data - Google Patents

Abstract

PURPOSE:To make the configuration of a reception data processing circuit available for general purpose and to realize the processing system of a TDMA reception data able to relieve the load of the software by using the hardware to identify a type of the reception data and designating a timing and an address required for identifying the reception data. CONSTITUTION:The system is provided with a processing unit 10, a storage buffer 20, a reception data identification means 30, and a storage buffer setting means 40. Then a type of a TDMA reception data is set to a reception data identification means 30 and the reception data is compared with a content of the reception data identification means 30 to identify the reception data and a storage buffer setting means 40 is set based on the result and the content of the storage buffer setting means 40 is read to output an address and an interrupt processing request signal of the storage buffer 20 into which the reception data is written thereby processing the reception data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TDMA received data processing method. For wireless communication, TDMA (Time Device) is used to effectively utilize the limited radio frequency band.
sion Multiple Access) is widely used.

[0002] The data transmitted through such TDMA communication has become more diverse, and the data processing of received data has also become more diverse, and its control circuits have also become more complex. There is a need for a received data processing method that can process such TDMA received data with a versatile circuit configuration, reduce the load on the processing device as much as possible, and perform the processing efficiently.

0003

2. Description of the Related Art FIG. 3 is a diagram illustrating a conventional example. In the figure, 10 is a processing unit (hereinafter referred to as MPU), 20 is a storage buffer, and 31 is a serial/parallel conversion circuit (hereinafter referred to as S
/P conversion circuit), 34 is a reception ID detection circuit, 3
5 is a frame counter, and 36 is a timing generation circuit.

In the conventional example described above, the MPU 10 is used to process various data, and the storage buffer 20 is used to temporarily write received data. Reception ID
The detection circuit 34 detects the beginning of a frame of received data. The frame counter 35 is operated based on this signal, and the timing of various processes, such as read/write, error detection processing timing, or write address to the storage buffer 20, is output from the count value.

On the other hand, the received data is converted from serial data to parallel data by the S/P conversion circuit 31, and then written to the storage buffer 20 at the timing and address generated by the timing generation circuit 36.

[0006] Furthermore, an interrupt signal IRQ generated by the timing generation circuit 36 interrupts the MPU 10 and notifies the software.

[0007]

[Problems to be Solved by the Invention] In the conventional example described above, when data is received, the received data is stored in a designated address of the storage buffer 20 regardless of the type of data, and then the software of the MPU 10 is instructed to receive the received data. The MPU 10 generates a data processing request signal and processes the data.
This is done using software.

Therefore, in the above configuration, the interrupt signal IRQ is applied to the software regardless of the type of received data, and data that does not need to be processed by the software of the MPU 10 is also processed by the software. load increases.

[0009] The present invention is a TDM system that can generalize the configuration of a received data processing circuit and further reduce the software load by identifying the type of received data using hardware and specifying the timing and address necessary for the type of received data.
We are trying to realize a processing method for A received data.

0010

Means for Solving the Problems FIG. 1 is a block diagram illustrating the principle of the present invention. In the figure, 10 is a processing device that processes the received data, 20 is a storage buffer that temporarily stores the received data, and 30 is a storage buffer in which the received data type is written and a match with the received data is detected. 40 is a storage buffer setting unit that generates a data storage address in the storage buffer 20 and an interrupt request signal IRQ to the processing device 10 based on the detection result of the reception data identification unit 30. The type of TDMA received data is written in the received data identifying means 30, the received data is compared with the contents of the received data identifying means 30, the type of received data is identified, and the storage buffer setting means 40 is used based on the result. is set, and by reading the contents of the storage buffer setting means 40, the address of the storage buffer 20 into which the received data is written and an interrupt request signal IRQ are outputted to process the received data. By employing this configuration, a TDMA reception data processing method can be obtained which can generalize the configuration of the reception data processing circuit and further reduce the software load.

[0011]

[Operation] The type of TDMA reception data is written in the reception data identification means 30, and the storage buffer setting means 40
A control signal including a write address of the storage buffer 20 designated by the type of TDMA received data and an interrupt request IRQ to the MPU 10 is written in the field.

[0012] When TDMA data is received in this state,
The received data type is compared with the data type written in the received data identifying means 30 to identify the received data type. When the received data can be identified, the storage buffer setting means 40 is set according to the type of the received data, and by reading the contents, the write address of the storage buffer 20 determined for each type of received data, processing timing, Generates an interrupt request signal IRQ.

[0013] Therefore, the writing of TDMA reception data to the storage buffer 20 is performed by a circuit with a general-purpose configuration under hardware control, and the interrupt processing of the MPU 10 is executed only for necessary reception data, reducing the software load. It becomes possible to do so.

[0014]

Embodiment FIG. 2 is a diagram illustrating an embodiment of the present invention. The embodiment shown in FIG. 2 is based on the received data identification means 3 explained in FIG.
0, the S/P conversion circuit 31 and the data type detection circuit 32
, a counter 33, a storage buffer setting circuit 41 as a storage buffer setting means 40, and the same MPU 10 and storage buffer 20 as explained in the conventional example of FIG.

The S/P conversion circuit 31 is composed of a shift register, and sequentially writes serial reception data.
By taking out the output at a certain timing, S/
Performing P conversion.

The data type detection circuit 32 is composed of a read-only memory (hereinafter referred to as ROM).
Write all types of data to be received in M. In this state, input the S/P converted received data and store it in the ROM.
The type of received data is identified by comparing it with the content of the received data. For example, the data type is output to the counter 33 and the storage buffer setting circuit 41 by outputting the address of the matched data.

The counter 33 counts the amount of data corresponding to the maximum data length determined by the data type. In addition, the storage buffer setting circuit 41 is also composed of a ROM, and by reading data at an address specified by the type of received data, various control signals (for example, read/write signals, error detection timing, interrupts to the MPU 10) are generated. A request signal IRQ, etc.) is generated.

Writing of received data to the storage buffer 20 is performed using the output of the counter 33 and the storage buffer setting circuit 41.
The storage buffer setting circuit 41 generates a control signal at an address specified by the output of the storage buffer setting circuit 41.

The received data written in the storage buffer 20 is sent to the MPU 10 by an interrupt request signal IRQ.
It is loaded into the storage device of PU10 (not shown in the figure), and the MPU
10 starts processing by the software.

However, depending on the type of received data, M
There are some that do not require interrupt processing for the PU 10. For such received data, when the data type is identified and the storage buffer setting circuit 41 generates a control signal, the interrupt request signal IRQ is not generated, and the valid data that needs to be processed by the MPU 10 is Since the interrupt request signal IRQ is generated only for data and interrupt processing is performed, the software load on the MPU 10 can be reduced.

[0021]

According to the present invention, the data type of TDMA received data is written in the data type detection circuit, a match is detected to identify the data type, and the write control to the storage buffer is controlled based on the data type detection circuit. This is done using a control signal generated by reading out the data written to the storage buffer setting circuit for each type, and processing is performed by hardware control, resulting in a versatile circuit configuration.Furthermore, for unnecessary received data, the MPU Since no interrupt request signal IRQ is generated, the software load on the MPU can be reduced.

[Brief explanation of the drawing]

[Figure 1] Block diagram explaining the principle of the present invention

[Figure 2
] Diagram explaining an embodiment of the present invention

[Figure 3] Diagram explaining a conventional example

[Explanation of symbols]

10 Processing device
20 Storage buffer 30 Received data identification means 31
S/P conversion means 32 Data type detection circuit 33
Counter 34 Reception ID detection circuit
35 Frame counter 36 Timing generation circuit 40
Storage buffer setting means 41 Storage buffer setting circuit

Claims (1)

[Claims] [Claim 1] TDMA used in digital radio
A method for processing received data in communication, which includes a processing device (10) that processes received data, a storage buffer (20) that temporarily stores received data, and a type of received data written therein. A received data identifying means (30) detects a match with the data and identifies the data type, and from the detection result of the received data identifying means (30), the storage address of the data in the storage buffer (20) and the processing It includes storage buffer setting means (40) for generating an interrupt request signal (IRQ) to the device (10), writes the TDMA reception data type in the reception data identification means (30), and stores the received data in the reception data identification means (30). (3
0), the type of received data is identified, the storage buffer setting means (40) is set based on the result, and the contents of the storage buffer setting means (40) are read. said storage buffer to write (
20) A TD characterized in that it processes received data by outputting an address and an interrupt request signal (IRQ).
MA reception data processing method.