JPH04207035A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To further enhance an electromigration-resistant property and a stress migration-resistant property by a method wherein an insulating layer is formed on a P-type semiconductor substrate in which an N<+> impurity region is formed and, after that, a substratum conductor layer is applied and formed. CONSTITUTION:A silicon dioxide film 13 in a thickness of about 8000Angstrom is formed on a silicon (100) substrate 11. After that, TiN in a thickness of 1000Angstrom is deposited on the insulating film by a DC magnetron sputtering method. Rectangular grooves 17 whose width is at 0.5mum and whose depth is at 500Angstrom are formed in the TiN layer 16 at intervals of 1mum by a photolithographic operation. The TiN layer is etched by a reactive ion etching (RIE) operation. Aluminum in a thickness of 4000Angstrom is deposited, by a DC magnetron sputtering method, on the TiN layer in which the rectangular grooves are formed. The Al is deposited under the same conditions as when the TiN is formed; the aluminum layer is heat-treated at 500 deg.C for one minute by a rapid thermal process.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a semiconductor device, and more specifically, a semiconductor device having excellent electromigration resistance and stress migration resistance. The present invention relates to a method of manufacturing a semiconductor device including a wiring layer.

(Prior Art) In recent years, semiconductor devices, particularly memory integrated circuits typified by DRAM, have become significantly smaller and more highly integrated, and along with this, the wiring that connects each element is also becoming smaller. Generally, to form a wiring layer, an insulating film is formed on a semiconductor substrate, such as silicon, on which a predetermined impurity region has been formed, and a contact hole is formed in this insulating film to partially expose the impurity region. This includes filling the hole with an electrode material to form a contact portion.

Forming a wiring material layer on the contact portion and the insulating film,
This is turned into a predetermined wiring shape. The commonly used wiring material is aluminum or aluminum alloy.

(Problems to be Solved by the Invention) However, as wiring becomes finer, the conditions required for wiring are becoming increasingly severe.

In particular, in recent years, wire breakage has become a problem due to nielectromigration due to high density current flowing through the wires, and stress migration due to a difference in thermal expansion between the wires and a protective film covering the wires to protect them. Aluminum or aluminum alloy wiring layers formed by conventional methods are polycrystalline, and the orientation of each crystal is aligned to some extent, but because the orientation is not uniform as a whole, It is easy to break.

It is known that the more the <111> orientation of the crystals of the thin film constituting the wiring is aligned perpendicularly to the top surface of the wiring, the better the electromigration resistance is (Vaidya, S. et al. , Thjn So
d FjlIIl, 75 (1981) 235)
However, the specific method is still not satisfactory.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device including a wiring layer having excellent electromigration resistance and stress migration resistance.

[Structure of the Invention] (Means and Effects for Solving the Problems) As a result of intensive research into a method for forming a wiring layer with excellent electromigration resistance and stress migration resistance, the present inventors discovered that the wiring layer One crystal orientation (especially <111> or <100> orientation in cubic crystals) of a good conductor (such as aluminum) that governs the conductivity of
It has been found that when the wiring layers are aligned substantially perpendicularly to the plane of the wiring layer, the bidirectionality is improved. In order to align the crystal orientation, a base conductor layer is formed before forming a good conductor, and predetermined grooves are periodically and symmetrically formed in the surface layer of this base conductor layer. and/or irradiating the surface layer of this base conductor layer with an energy beam in a periodic and symmetrical pattern, and then depositing and forming a good conductor layer. We have found that this is the most effective method and have completed the present invention. After forming a good conductor layer, it is heat treated to align the crystal orientation, but the temperature at that time is lower than the melting point of the good conductor.
Furthermore, at least the surface layer of the base conductor layer must have a melting point higher than the melting point of the good conductor.

That is, according to the present invention, there is a step of forming an uppermost conductor layer made of a first good conductor for electrically connecting the elements on a substrate on which an element having a semiconductor junction is formed; Before forming the uppermost conductor layer, form a base conductive layer in which at least the surface layer is made of a second conductor having a higher melting point than the first good conductor; Forming grooves of a predetermined shape periodically and symmetrically in the surface layer, forming the uppermost conductor layer on the base conductor layer in which the grooves have been formed, and forming the uppermost conductor layer, A method for manufacturing a semiconductor device is provided, which comprises heat-treating at a temperature lower than its melting point and processing the uppermost conductor layer and the underlying conductor layer into a predetermined wiring shape.

Further, according to the present invention, there is a step of forming an uppermost conductive layer consisting of a first conductive material for electrically connecting the elements on the substrate on which the elements having the semiconductor junction are formed. , before forming the uppermost conductor layer, forming a base conductive layer made of a second conductor whose surface layer has a melting point higher than that of the first good conductor; irradiating the surface layer of the conductive layer with an energy beam periodically and symmetrically in streaks, forming the uppermost conductor layer on the base conductor layer irradiated with the energy beam; A method for manufacturing a semiconductor device, characterized in that the upper conductor layer is heat-treated at a temperature lower than its melting point, and the upper conductor layer and the base conductor layer are processed into a predetermined wiring shape. Ru.

It is considered that the corner of the groove Ii formed in the base conductive layer according to the present invention becomes a starting point for crystal growth of the good conductor, and the crystal orientation of the good conductor is aligned in accordance with the shape. By heat-treating the good conductor layer, the crystal orientation can be aligned in an orderly manner.

Even when the underlying conductive layer is irradiated with an energy beam, the irradiated area becomes the starting point for crystal growth of the good conductor, and the crystal orientation of the good conductor is aligned according to the planar shape of the irradiated area. .

By the way, when forming a metal thin film, grooves are formed in the base layer,
Methods for aligning the crystal orientation of metal thin films are already available in M, W,
Gets et al. J, Vac, Sci
.

Technol, 1B (1979), 1640
has been disclosed.

However, in this method, the underlying layer in which the grooves are formed is silicon dioxide, which is amorphous and has no crystallinity, and has high stress migration resistance and electromigration resistance required for semiconductor integrated circuits. It is simply impossible to provide wiring with

The present invention will be explained in more detail below with reference to the drawings.

I will clarify. Similar parts are indicated by the same reference numerals throughout the figures.

FIGS. 18 to 1E show a method for manufacturing a semiconductor device according to a first aspect of the present invention.

As shown in FIG. 1A, an insulating layer (for example, silicon dioxide) 13 is formed on a P-type semiconductor substrate 11 in which, for example, an N+ impurity region 12 is formed.

A contact hole 14 that partially exposes the impurity region 12 is formed in this insulating layer 13, and a conductive material is filled in the contact hole 14 to form a contact portion 15.

Thereafter, a base conductor layer 16 is deposited over the entire structure of FIG. 1A. This base conductor layer 16 has a higher melting point than a good conductor layer to be formed later, and can be formed of, for example, metal silicide, nitride, or the like.

This base conductor layer 16 has a specific resistance value of 200 μΩC.
It is preferably ll1 or less, and in order to align the crystal orientation of the good conductor to be formed later, it is particularly preferable that the crystal system is the same as that of the good conductor to be used. Specifically, the base conductor layer 16 can be formed of titanium nitride, cobalt silicide, nickel silicide, or the like.

The base conductor layer 16 is preferably formed by a method that allows a base conductor layer with excellent crystal orientation to be formed on the insulating layer. This is because the crystal orientation of the good conductor formed thereon is improved, and electromigration resistance and stress migration resistance can be further improved.

Such formation methods can be selected from any known means such as sputtering (including reactive sputtering), chemical vapor deposition (CVD), vapor deposition, and the like.

Next, as shown in FIG. 1B, grooves 17 of a predetermined shape are formed periodically and symmetrically in the surface of the base conductor layer 16. Although the figure shows a groove 16 having a rectangular cross-section, the present invention is not limited to this, and grooves having a triangular (V-groove), trapezoidal, etc. cross-section may be formed. In short, grooves of a certain shape are formed periodically and symmetrically. A preferable groove is one in which the bottom surface is parallel to the surface of the semiconductor substrate 11, and the angle between the side surface and the bottom surface is 90 degrees or less.

Also, there are no particular restrictions on the width, depth, and spacing of the grooves; preferably, the width is 0.5 μm and the depth is 500 to 150 μm.
0A, the spacing is 0.5 to 1.5 μm.

As mentioned above, these grooves improve the crystal orientation of the good conductor that will be formed later, or this effect can be achieved by irradiating the grooves with an energy beam (preferably along the corners of the grooves). ). Therefore, in a more preferred embodiment of the present invention, as shown in FIG.
7 is formed, an energy beam 18 is irradiated along the corner of the groove 17. As the energy beam, electron beams, X-rays, etc. can be used.

After forming the grooves 17, a good conductor layer 19 is formed on the base conductor layer 16 which is irradiated with or not irradiated with an energy beam, as shown in FIG. 1E.

The good conductor layer 19 can be formed of, for example, aluminum, silver, gold, copper, or an alloy thereof. The good conductor layer 19 also
In order to further improve electromigration resistance and stress migration resistance, it is preferable to form the conductive layer by a method that provides a conductive layer with excellent crystal orientation. Such a formation method may be selected from any known means such as sputtering (including reactive sputtering), chemical vapor deposition (CVD), vapor deposition, and the like.

After forming the good conductor layer 19 in this manner, it is subjected to heat treatment in order to align its crystal orientation.

This heat treatment must be performed at a temperature lower than the melting point of the good conductor so as not to lose its crystal orientation. In particular, good crystal orientation can be achieved by heat treatment at a temperature 50°C to 100°C lower than the melting point. There are no particular restrictions on the heat treatment method, and the heat treatment time varies depending on the heat treatment method employed. For example, in the case of lamp annealing, the heat treatment time is preferably 30 seconds to 5 minutes, and in the case of electric furnace annealing, the heat treatment time is preferably 20 minutes to 40 minutes.

By this heat treatment, the crystal orientation of the good conductor 1 is aligned in the direction perpendicular to the plane of the layer 19. For example, if the good conductor is a cubic crystal system such as aluminum, its <111> or <100> orientation will be aligned in the direction perpendicular to the plane of the layer 19.

After the heat treatment, the good conductor layer 19 and base conductor layer 16 are turned into a wiring shape by a conventional method to form a wiring layer.

2A and 2B illustrate a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

In this embodiment, instead of forming grooves, an energy beam is irradiated.

That is, referring to FIG. 2A, first, as described with respect to FIGS. 1A and 1B, the N+ type impurity region 1 is
forming an insulating layer 13 on a P-type semiconductor substrate 11 having 2;
A contact hole 14 and a contact portion 15 are formed, and a base conductor layer 16 is formed. Thereafter, the energy beam 21 is irradiated periodically and symmetrically in a streak pattern.

For example, the energy beam can be applied linearly (describing an equilateral triangle) with a three-fold axis of symmetry, as shown in plan in FIG. 3A. Or 3rd B
As shown in the plane in the figure, irradiation may be performed in a streakwise manner (as if drawing a square) so as to have a four-fold axis of symmetry. There are no particular restrictions on the distances d1 and d2 between the parallel lines of these drawings, but
Preferably, the spacing is between 0.1 μm and 0.5 μm.

Next, referring to FIG. 2B, after energy beam irradiation,
As described with reference to FIG. 1E, a good conductor layer 19 is formed on the underlying conductor layer 16, and is subjected to heat treatment. Then, the part irradiated with the energy beam acts as a crystal orientation control part, and the crystal orientation of layer 1 of the good conductor layer is
Align in the direction perpendicular to the plane of 9. Thereafter, similarly to the first embodiment, layers 19 and 16 are patterned into a predetermined wiring shape.

Note that in the first and second embodiments, the base conductor layer consists of one layer, but the base layer may consist of a plurality of layers, in which case the uppermost layer (
That is, the physical properties, conditions, and means described for the base conductor layer may be applied to the layer on which the good conductor layer is directly formed. In addition, as mentioned earlier, in the cubic crystal conductor layer, it is preferable that the <111> or <100> orientations are aligned perpendicular to the wiring, and among them, the <100> orientation is preferable. , are particularly preferably aligned vertically. Such crystal orientation can be achieved, for example, by irradiating the base conductive layer with an energy beam in a line-wise manner so as to have a 4-fold symmetry axis, as shown in FIG. 3B, and then depositing a good conductor layer. This can be conveniently achieved by

(Examples) Hereinafter, the present invention will be explained in more detail with reference to Examples. In the following examples, the formation of impurity regions and contact holes are not discussed for the sake of simplicity.

Example 1 A silicon dioxide film was formed to a thickness of about 800 OA on a silicon (100) substrate by thermal oxidation.

Thereafter, TiN (cubic crystal) was deposited to a thickness of 100 OA on this insulating film by DC magnetron sputtering. This deposition was performed by reactive sputtering in nitrogen gas, with a sputtering output of 500 W and a pressure of 4 x 1.
The 0-3 Torrs deposition time was 20 seconds.

When the crystal orientation of the thus obtained TiN film was analyzed by X-ray diffraction, it was found that the <111> orientation of this TiN film was oriented perpendicular to the substrate surface. Also,
When the half width of the (111) diffraction line was measured by the θ scan method, it was 8 to 10 degrees.

Rectangular grooves with a width of 0.5 μm and a depth of 500 A were formed in the TiN layer at intervals of 1 μm by photolithography.

Etching of the TiN layer is performed using reactive ion etching (R
IE).

On the TiN layer in which the rectangular grooves were formed, aluminum (cubic crystal) was deposited at 40% by DC magnetron sputtering.
It was deposited to a thickness of 0A. The deposition conditions were the same as for TiN formation, except that the deposition time was 30 seconds.

The aluminum layer thus obtained was heat treated at 500° C. for 1 minute by a rapid thermal process (RTP).

When the crystal orientation of the aluminum layer after heat treatment was measured by X-ray diffraction, the half width of the (111) diffraction line was approximately 0.
．． 7 degrees, indicating very good orientation. moreover,
The same process was performed while changing the width and depth of the groove in the TiN layer, and the crystal orientation of the aluminum layer was investigated. As a result, it was found that the crystal orientation of aluminum was much improved compared to the case where no grooves were formed in the TiN layer.

Next, the aluminum layer and the TiN layer were formed to a width of 1°0 μm.
% 0, 6 μm, and 0.4 μm, and deposited phosphosilicate glass (PSG) at 450°C.
A TEG (test element group) for measuring stress migration was prepared, and stress migration resistance characteristics were evaluated. The results are shown in Figure 4. In FIG. 4, line a refers to the wiring layer of the present invention, and line a refers to the wiring layer obtained in the same manner except that no grooves were formed in the TiN layer. From these results, it is clear that the wiring layer of the present invention exhibits excellent stress migration resistance.

Furthermore, for the wiring of the present invention processed to a width of 0.3 μm, the current density was 2 × 106 A/cm 2.150
Electromigration tests were conducted under the conditions of ℃. From the result of the resistance increase at that time, the wiring of the present invention
It was found that the lifespan was approximately 50 times longer than that of conventional AI-81-Cu wiring.

Example 2 Silicon (100) was prepared under exactly the same conditions and film thickness as in Example 1.
A silicon dioxide film and a TiN layer were formed on the substrate.

Next, the TiN layer was irradiated with an electron beam in a streakwise manner at an accelerating voltage of 20 kV so as to have a 3-fold symmetry axis, as shown in FIG. 3A. One side of the drawn equilateral triangle is 0.3μ
It was m.

Thereafter, aluminum was deposited on the TiN layer under exactly the same conditions and thickness as in Example 1. Next, TiN/AI
The two-layer film was heated at 500°C in an electric furnace in an argon gas atmosphere.
The sample was heat-treated for 1 minute. When the crystal orientation of the aluminum layer after the heat treatment was measured by X-ray diffraction, the half width of the (111) diffraction line was about 1.0 degrees, indicating very good orientation.

Furthermore, the TiN layer was irradiated with an electron beam at various accelerating voltages to examine the crystal orientation of the aluminum layer. As a result, it was found that the crystal orientation of aluminum was much improved compared to the case where the TiN layer was not irradiated with an electron beam.

Then, in exactly the same manner as in Example 1, a TEG for stress migration measurement was produced, and the stress migration resistance characteristics were evaluated. The results are shown in Figure 5. In FIG. 5, line C is related to the wiring layer of the present invention, line d is Ti
This example relates to a wiring layer obtained in the same manner except that the N layer was not irradiated with an electron beam.

From these results, it is clear that the wiring layer of the present invention exhibits excellent stress migration resistance. Furthermore, an electromigration test was conducted on the wiring of the present invention under exactly the same conditions as in Example 1. As a result of the increase in resistance at that time, the wiring of the present invention is different from the conventional Al-5i
-CuWi! It was found that the lifespan is approximately 20 times longer than that of wire.

Example 3 After forming grooves in the TiN layer and before depositing the aluminum layer, an electron beam was accelerated at a voltage of 20 along the corners of the grooves in the TiN layer.
The operation was exactly the same as in Example 1 except that irradiation was performed at kV. The crystal orientation of the aluminum layer after heat treatment is
When measured by line diffraction, the half width of the (111) diffraction line was about 0.7 degrees, indicating very good orientation. Furthermore, the same treatment was performed except that the width and depth of the groove in the TiN layer were changed, and the crystal orientation of the aluminum layer was investigated. As a result, the crystal orientation of aluminum is T
It was found that this was much improved compared to the case where the iN layer was not irradiated with an electron beam.

Then, in exactly the same manner as in Example 1, a TEG for stress migration measurement was produced, and the stress migration resistance characteristics were evaluated. The results are shown in Figure 5. In FIG. 6, the line e is related to the wiring layer of the present invention, and the line f is related to the wiring layer of the present invention.
This is a wiring layer obtained in the same manner except that the N layer was not provided with a groove and was not irradiated with an electron beam. From these results, it is clear that the wiring layer of the present invention exhibits excellent stress migration resistance. Furthermore, an electromigration test was conducted on the wiring of the present invention under exactly the same conditions as in Example 1. The results of the increase in resistance showed that the wiring of the present invention had a lifespan approximately 70 times longer than that of conventional Al-5i-Cu wiring.

[Effects of the Invention] As detailed above, according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having excellent stress migration resistance and electromigration resistance can be manufactured.

[Brief explanation of the drawing]

1A to SLE are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the first aspect of the present invention in order of steps, and FIGS. 2A to 2B are sectional views according to the second aspect of the present invention. 3A and 3B are cross-sectional views for explaining the method for manufacturing a semiconductor device in the order of steps, and FIG. 6 through 6 are graphs showing characteristics of wiring layers obtained according to the present invention together with comparative examples. 11... Semiconductor substrate, 12... Impurity region, 13.
...Insulating layer, 14...Contact hole, 15...
Contact portion, 16... Base conductor layer, 17... Groove, 18, 21... Energy beam, 19... Good conductor layer Applicant's agent Patent attorney Takehiko Suzue Figure 2B

Claims (2)

[Claims] (1) On a substrate on which an element having a semiconductor junction is formed,
The step includes forming an uppermost conductor layer made of a first good conductor that electrically connects the elements, and before forming the uppermost conductor layer, at least the surface layer is made of the first good conductor. forming a base conductive layer made of a second conductor having a melting point higher than that of the base conductor layer; forming grooves of a predetermined shape periodically and symmetrically in the surface layer of the base conductor layer; forming the uppermost conductor layer on the base conductor layer in which the grooves are formed; heat-treating the uppermost conductor layer at a temperature lower than its melting point; and forming the uppermost conductor layer and the base conductor layer. 1. A method for manufacturing a semiconductor device, which comprises processing a semiconductor device into a predetermined wiring shape. (2) On a substrate on which an element having a semiconductor junction is formed,
The step includes forming an uppermost conductor layer made of a first good conductor that electrically connects the elements, and before forming the uppermost conductor layer, at least the surface layer is made of the first good conductor. forming a base conductive layer made of a second conductor having a melting point higher than that of the body; irradiating the surface layer of the base conductive layer with an energy beam in a periodic and symmetrical pattern; forming the uppermost conductor layer on the base conductor layer irradiated with the energy beam; heat-treating the uppermost conductor layer at a temperature lower than its melting point; 1. A method for manufacturing a semiconductor device, comprising processing a body layer into a predetermined wiring shape.