JPH042040U - - Google Patents

Info

Publication number
JPH042040U
JPH042040U JP4279290U JP4279290U JPH042040U JP H042040 U JPH042040 U JP H042040U JP 4279290 U JP4279290 U JP 4279290U JP 4279290 U JP4279290 U JP 4279290U JP H042040 U JPH042040 U JP H042040U
Authority
JP
Japan
Prior art keywords
semiconductor package
outer periphery
center
accommodating
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4279290U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4279290U priority Critical patent/JPH042040U/ja
Publication of JPH042040U publication Critical patent/JPH042040U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例である半導体用パ
ツケージの斜視図、第2図は第1図の組立断面図
、第3図は従来の半導体用パツケージの展開斜視
図、第4図は第3図の封止後の組立断面図である
。 図において、9はセラミツク、10a,10b
は各々封止面の中央部および外周部、11は金め
つき金属板を示す。
Fig. 1 is a perspective view of a semiconductor package which is an embodiment of this invention, Fig. 2 is an assembled sectional view of Fig. 1, Fig. 3 is an exploded perspective view of a conventional semiconductor package, and Fig. 4 is an exploded perspective view of a conventional semiconductor package. FIG. 4 is an assembled sectional view of FIG. 3 after sealing; In the figure, 9 is ceramic, 10a, 10b
1 represents the center and outer periphery of the sealing surface, respectively, and 11 represents a gold-plated metal plate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプを収納するための直方体形状及び
円柱状の空間を持つ半導体用パツケージにおいて
、前記半導体用パツケージの枠部上面の中央寄り
と外周部で段差を設けたことを特徴とする半導体
用パツケージ。
A semiconductor package having a rectangular parallelepiped and cylindrical space for accommodating a semiconductor chip, characterized in that a step is provided near the center and on the outer periphery of the upper surface of the frame of the semiconductor package.
JP4279290U 1990-04-20 1990-04-20 Pending JPH042040U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4279290U JPH042040U (en) 1990-04-20 1990-04-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4279290U JPH042040U (en) 1990-04-20 1990-04-20

Publications (1)

Publication Number Publication Date
JPH042040U true JPH042040U (en) 1992-01-09

Family

ID=31554644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4279290U Pending JPH042040U (en) 1990-04-20 1990-04-20

Country Status (1)

Country Link
JP (1) JPH042040U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006054304A (en) * 2004-08-11 2006-02-23 Sanyo Electric Co Ltd Ceramic package, aggregaed substrate, and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006054304A (en) * 2004-08-11 2006-02-23 Sanyo Electric Co Ltd Ceramic package, aggregaed substrate, and manufacturing method thereof
JP4511278B2 (en) * 2004-08-11 2010-07-28 三洋電機株式会社 Ceramic package

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