JPH04196550A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04196550A
JPH04196550A JP2328122A JP32812290A JPH04196550A JP H04196550 A JPH04196550 A JP H04196550A JP 2328122 A JP2328122 A JP 2328122A JP 32812290 A JP32812290 A JP 32812290A JP H04196550 A JPH04196550 A JP H04196550A
Authority
JP
Japan
Prior art keywords
pad
semiconductor device
agent
resist
exposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2328122A
Other languages
Japanese (ja)
Inventor
Tadaaki Nakano
中野　忠明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2328122A priority Critical patent/JPH04196550A/en
Publication of JPH04196550A publication Critical patent/JPH04196550A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Abstract

PURPOSE:To expedite generation of alloy of a conductive wire and various metals and to enhance bond strength of the pad to the wire by forming an uneven part on the pad in a special step, and forming the part in a special range. CONSTITUTION:Various types of patterns 2 are formed on an Si wafer 1, and a pad 3 of Al is formed as its electrode. Thereafter, the pad 3 is further coated with resist agent 4. When it is exposed by using a mask 6 except resist of places to be desirably formed with protrusions, the agent 4 is cured at the exposed position 5. It is developed to remove the resist 3 which is not exposed, further baked, and the cured agent 5 is solidified. The part having no agent as seen from above is etched to form recesses. When the agent 5 of the protrusions is removed, the pad having an uneven surface having lower recesses than those of the pad formed initially is formed. The pad has 0.1-1.0mum of protrusions and recesses on the surface.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、ワイヤボンディング工程を有する半導体装置
のパッド部の表面のあらさに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to surface roughness of a pad portion of a semiconductor device having a wire bonding process.

［従来の技術］ 半導体装置のバ・ソド部はＳｉウェハを酸化、露光、エ
ツチング等の工程を数回繰り返した後、半導体装置から
外部へ信号を比したり、半導体装置に電源を供給したり
、半導体装置が外部からの信号を受は取ったりするため
の電極として第５図のように半導体装置の外形に沿って
設けられており、第６図のように１のＳｉのベースの上
に２の各種パターンが形成され、３のパッド部が４の保
護膜の１部からのぞいているという構造をしている。[Prior Art] The semiconductor device's substrate is made by repeating processes such as oxidizing, exposing and etching the Si wafer several times, and then transmitting signals from the semiconductor device to the outside or supplying power to the semiconductor device. , electrodes for the semiconductor device to receive and receive signals from the outside are provided along the outer shape of the semiconductor device as shown in FIG. 5, and as shown in FIG. Various patterns 2 are formed, and the pad portion 3 is exposed through a portion of the protective film 4.

部材としては、現在はＡｌ−３ｉが多く用いられ、最近
ではその他にＣｕを加えたＡｌ−Ｃｕ−３ｉで生成され
ているものも増えてきている。Currently, Al-3i is often used as a material, and recently there has been an increase in the number of materials made of Al-Cu-3i with Cu added to it.

導電性ワイヤによりリードフレームインナリードやセラ
ミック基板やガラエポ等樹脂基板表面と半導体装置のパ
ッド部とを接続するワイヤボンディング工程は半導体装
置の組立工程の１つである。A wire bonding process in which a conductive wire is used to connect the inner lead of a lead frame or the surface of a resin substrate such as a ceramic substrate or glass epoxy resin to a pad portion of a semiconductor device is one of the assembly processes of a semiconductor device.

第７図にワイヤボンディング工程後の半導体装置の状態
を示す。第７図において１の半導体装置のパッド部と２
のリードフレームのインナリード部の先端を３のＡｕワ
イヤまたは、Ａｌワイヤ等で接続するものである。４は
、ワイヤボンディング後ワイヤ部材であるＡｕまたはＡ
１とパッド部材であるＡｌ−３ｉまたはＡｌ−Ｃｕ−３
ｉとの間に生成された合金である。その合金により半導
体装置とリードフレームは接続される。FIG. 7 shows the state of the semiconductor device after the wire bonding process. In FIG. 7, the pad portion of the semiconductor device 1 and the pad portion of the semiconductor device 2
The tips of the inner lead portions of the lead frames are connected with No. 3 Au wires, Al wires, or the like. 4 is Au or A which is a wire member after wire bonding
1 and Al-3i or Al-Cu-3 which is a pad member
It is an alloy formed between The semiconductor device and the lead frame are connected by the alloy.

［発明が解決しようとする課題］ しかし、上言己のような従来技術では、最近増加してき
たＣｕを含んであるＡｌ−Ｃｕ−３ｉやその他の金属が
含んでいる部材等で形成されている半導体装置のパッド
とＡｕやＡ１等で形成されているボンディングボールと
は合金が生成されづらいという問題点が有り、その結果
パッドとボンディングボールとの接合強度も弱くなって
しまう問題点も発生してきている。[Problems to be Solved by the Invention] However, in the conventional technology such as the one described above, it is formed of materials containing Al-Cu-3i, which contains Cu, which has been increasing recently, and other metals. There is a problem in that it is difficult to form an alloy between the pad of a semiconductor device and a bonding ball made of Au, A1, etc., and as a result, the bonding strength between the pad and the bonding ball is also weakened. There is.

本発明は上記の課題を解決すべくなされてもので、パッ
ド部材であるＡｌ−５ｉやＡｌ−Ｃｕ−３ｉとボンディ
ングワイヤ材のＡｕやＡ１との合金の生成を促進するの
を目的とした半導体装置及び、製造方法である。The present invention has been made to solve the above problems, and is a semiconductor aimed at promoting the formation of an alloy between Al-5i or Al-Cu-3i, which is a pad member, and Au or Al, which is a bonding wire material. An apparatus and a manufacturing method.

［課題を解決するための手段］ 本発明に係わる半導体装置は、リードフレームインナリ
ードやセラミック基板あるいはガラエポ等樹脂基板表面
の端子とパッド部（半導体装置と外部との信号をやりと
りする外部接続端子）を導電性ワイヤにより接続して組
立を行う半導体装置において、前記パッド部は特定の工
程により凹凸を形成されＪその凹凸は０．１〜１．０ｕ
ｍであることを特徴とする。[Means for Solving the Problems] A semiconductor device according to the present invention has terminals and pads (external connection terminals for exchanging signals between the semiconductor device and the outside) on the surface of a lead frame inner lead, a ceramic substrate, or a resin substrate such as glass epoxy resin. In a semiconductor device that is assembled by connecting the pads with conductive wires, the pad portion is formed with unevenness by a specific process, and the unevenness is 0.1 to 1.0 μm.
It is characterized by being m.

［実施例コ 第１図は本発明の実施例である半導体装置の製造方法１
、第２図は半導体装置の製造方法２である。[Example 1] Figure 1 shows a method 1 for manufacturing a semiconductor device which is an example of the present invention.
, FIG. 2 shows a second method for manufacturing a semiconductor device.

製造方法１として、第１図（ａ）のＳｉウェハ１を露光
、エツチング、拡散を数回繰り返し、　（ｂ）の各種の
パターンが形成される。　（Ｃ）においてＳｉウェハ１
の上に各種パターン２が形成され、さらにその電極とし
てＡＩのパッド３を形成する。　（ｄ〉においてその後
さらにパッド３上にレジスト剤（感光性樹脂）４を塗布
する。　（ｅ）において凸を形成したい場所のレジスト
を残すようなマスク（またはレチクル）６を用い露光す
ると、レジスト剤（感光性樹脂）４は露光された箇所５
は硬化する。　（ｆ）において露光されていないレジス
ト３を除去するために現像を行い、さらにベークをし硬
化したレジスト剤５を固める。　（ｇ）において上から
みてレジスト剤の無い部分のパッドを工；ソチングし凹
部分を形成する。そして凸の部分のレジスト剤５を除去
すると最初に形成されたパッドよりも低い凹部を持つ凹
凸面を持ったパッドを形成する。In manufacturing method 1, the Si wafer 1 shown in FIG. 1(a) is exposed, etched, and diffused several times to form various patterns shown in FIG. 1(b). In (C), Si wafer 1
Various patterns 2 are formed thereon, and AI pads 3 are further formed as electrodes thereof. In (d), a resist agent (photosensitive resin) 4 is further coated on the pad 3. In (e), when exposed using a mask (or reticle) 6 that leaves the resist at the location where the convexity is to be formed, the resist agent (photosensitive resin) 4 is applied. (Photosensitive resin) 4 is the exposed area 5
hardens. In (f), development is performed to remove the unexposed resist 3, and further baking is performed to harden the hardened resist agent 5. In (g), the pad in the area where there is no resist agent when viewed from above is etched; a recessed area is formed. Then, when the resist agent 5 on the convex portion is removed, a pad having an uneven surface with a concave portion lower than that of the initially formed pad is formed.

つぎに製造方法２として、第２図（ａ）のＳｉウェハ１
を露光、エツチング、拡散を数回線り返し、　（ｂ）の
各種のパターンが形成される。　（Ｃ）においてＳｉウ
ェハ１の上に各種パターン２が形成され、さらにその電
極としてＡ１のパッド３を形成する。さらにその上にパ
ッド部材と同種または異種の材料４を蒸着させる。　（
ｄ）においてその後さらにバッド３上の材料４の上にレ
ジスト剤（感光性樹脂）５を塗布する。　（ｅ）におい
て凸を形成したい場所のレジストを残すようなマスク（
またはレチクル）７を用い露光すると、レジスト剤（感
光性樹脂）５の露光された箇所６は硬化する。　（ｆ）
において露光されていないレジスト５を除去するために
現像を行い、さらにベークをし硬化したレジスト剤６を
固める。　（ｇ）において上からみてレジスト剤の無い
部分のパッドをエツチングし凹部分を形成する。そして
凸の部分の硬化したレジスト剤６を除去すると最初に形
成されたパッドよりも高い凸部を持つ凹凸面を持ったパ
ッドを形成する。Next, as manufacturing method 2, the Si wafer 1 shown in FIG.
By repeating exposure, etching, and diffusion several times, the various patterns shown in (b) are formed. In (C), various patterns 2 are formed on the Si wafer 1, and pads 3 of A1 are further formed as electrodes thereof. Furthermore, a material 4 of the same type or different type as the pad member is deposited thereon. (
In step d), a resist agent (photosensitive resin) 5 is then applied onto the material 4 on the pad 3. In (e), a mask (
When exposed using a reticle (or reticle) 7, the exposed portions 6 of the resist agent (photosensitive resin) 5 are cured. (f)
In order to remove the unexposed resist 5, development is performed, and further baking is performed to harden the hardened resist agent 6. In (g), the pad in the area where there is no resist agent when viewed from above is etched to form a concave portion. When the hardened resist agent 6 on the convex portions is removed, a pad with an uneven surface having convex portions higher than the initially formed pad is formed.

第３図（ａ）は半導体装置のパッド部の表面図、（ｂ）
は断面図である。第４図は本発明のパッド上にボンディ
ングを行ったばあいの断面面である。Figure 3 (a) is a surface view of the pad portion of the semiconductor device, (b)
is a sectional view. FIG. 4 is a cross-sectional view of a case where bonding is performed on the pad of the present invention.

半導体装置のパッド１とボンディングボール２との間の
ボール側界面に生成された合金３は、半導体装置のパッ
ドとボンディングボールと接している面が広くなったこ
とにより促進される。そのことによって半導体装置のパ
ッド部とボンディングワイヤとの接合強度が強くなる。The alloy 3 generated at the ball-side interface between the pad 1 of the semiconductor device and the bonding ball 2 is promoted by the widening of the surface in contact with the pad of the semiconductor device and the bonding ball. This increases the bonding strength between the pad portion of the semiconductor device and the bonding wire.

［発明の効果コ 以上に述べたように発明すれば、導電性ワイヤにより接
続するワイヤボンディングにより、リードフレームイン
ナリードやセラミック基板あるいはガラエポ等樹脂基板
表面と接続するパッド部（半導体装置と外部との信号を
やりとりする外部接続端子）表面に０．　１〜１．０ｕ
ｍの凹凸を形成することによって、導電性ワイヤとパッ
ド部材である各種金属との合金の生成を促進し、パッド
部と導電性ワイヤとの接合強度が強化されるという効果
がある。[Effects of the Invention] If the invention is made as described above, wire bonding using conductive wires can be used to connect the lead frame inner lead, the pad portion connected to the surface of the ceramic substrate, or the resin substrate such as glass epoxy resin (the connection between the semiconductor device and the outside). External connection terminal for exchanging signals) 0. 1~1.0u
By forming the unevenness of m, the formation of an alloy between the conductive wire and various metals of the pad member is promoted, and the bonding strength between the pad portion and the conductive wire is strengthened.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）〜（ｇ）は本発明の実施例である半導体装
置の製造方法１を示す図、第２図（ａ）〜（ｇ）は同じ
〈実施例の半導体装置の製造方法２を示す区、第３図（
ａ）（ｂ）は同じ〈実施例の半導体装置の表面図と断面
図、第４図は同じ〈実施例の半導体装置上にワイヤボン
ディングを行った場合の断面図、第５面は従来の半導体
装置のパッドの配置図、第６図は従来のパッド部の断面
図、第７図は従来のパッド部上にワイヤボンディングを
行った場合の断面図である。 、以上 出願人　セイコーエプソン株式会社 代理人　弁理士　鈴木喜三部　ｆｌ！！１名第　　多節
　図　　（ａ） 笛　　１　　図　　（ｂ） 第　　１　　図　　（ｄ） 第　　１　　図　　（ｅ） へ 第　　１　　図　　（ｆ） 第　　１　　図　　（ｇ） 第　　２　　図　　（ａ） Ｚ　　２　　図　　（ｂ） 第　　２　　図　　（Ｃ） 第　　２　　図　　（ｄ） 第　　２　　図　　（ｅ） 第　　２　　図　　（ｆ） 第　　２　　図　　（ｇ） 第　　３　　図　　（ａ） 第　　３　　図　　（ｂ） 莞　　４　　図 ］ 范６図 第　　７　　図1(a) to (g) are diagrams showing a method 1 for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) to (g) are the same (method 2 for manufacturing a semiconductor device according to an embodiment). District showing the area, Figure 3 (
a) and (b) are the same〈Surface view and cross-sectional view of the semiconductor device of the example, Figure 4 is the same〈a cross-sectional view when wire bonding is performed on the semiconductor device of the example, and the fifth side is a conventional semiconductor device. FIG. 6 is a cross-sectional view of a conventional pad portion, and FIG. 7 is a cross-sectional view when wire bonding is performed on the conventional pad portion. , Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki fl! ! Figure 1 (a) Whistle 1 Figure (b) Figure 1 (d) Figure 1 (e) to Figure 1 (f) Figure 1 (g) Figure 2 (a) Z 2 Figure ( b) Figure 2 (C) Figure 2 (d) Figure 2 (e) Figure 2 (f) Figure 2 (g) Figure 3 (a) Figure 3 (b) Figure 4] Fan 6 Figure 7

Claims (2)

【特許請求の範囲】[Claims] （１）リードフレームインナリードやセラミック基板あ
るいはガラエポ等樹脂基板表面の端子とパッド部（半導
体装置と外部との信号をやりとりする外部接続端子）を
導電性ワイヤにより接続して組立を行なう半導体装置に
おいて、前記パッド部が特定の工程により凹凸を形成さ
れていることを特徴とする半導体装置(1) In semiconductor devices that are assembled by connecting terminals and pads (external connection terminals for exchanging signals between the semiconductor device and the outside) on the surface of lead frame inner leads, ceramic substrates, glass epoxy resin substrates, etc. using conductive wires. , a semiconductor device characterized in that the pad portion has irregularities formed by a specific process. （２）リードフレームインナリードやセラミック基板あ
るいはガラエポ等樹脂基板表面の端子とパッド部（半導
体装置と外部との信号をやりとりする外部接続端子）を
導電性ワイヤにより接続して組立を行なう半導体装置に
おいて、前記パッド部表面に０．１〜１．０ｕｍの凹凸
を持つことを特徴とする請求項１記載の半導体装置(2) In semiconductor devices that are assembled by connecting terminals and pads (external connection terminals that exchange signals between the semiconductor device and the outside) on the surface of lead frame inner leads, ceramic substrates, glass epoxy resin substrates, etc. using conductive wires. 2. The semiconductor device according to claim 1, wherein the surface of the pad portion has an unevenness of 0.1 to 1.0 um.
JP2328122A 1990-11-28 1990-11-28 Semiconductor device Pending JPH04196550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2328122A JPH04196550A (en) 1990-11-28 1990-11-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2328122A JPH04196550A (en) 1990-11-28 1990-11-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04196550A true JPH04196550A (en) 1992-07-16

Family

ID=18206731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2328122A Pending JPH04196550A (en) 1990-11-28 1990-11-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04196550A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003510815A (en) * 1999-09-20 2003-03-18 テレフオンアクチーボラゲット エル エム エリクソン（パブル） Semiconductor chip having an adhesive pad provided on an active element
JP2007165884A (en) * 2005-12-09 2007-06-28 Agere Systems Inc Integrated circuit having bondpad in which thermal and mechanical properties are improved
EP2339622A1 (en) * 2009-12-23 2011-06-29 Nxp B.V. Wirebonding Process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003510815A (en) * 1999-09-20 2003-03-18 テレフオンアクチーボラゲット エル エム エリクソン（パブル） Semiconductor chip having an adhesive pad provided on an active element
JP2007165884A (en) * 2005-12-09 2007-06-28 Agere Systems Inc Integrated circuit having bondpad in which thermal and mechanical properties are improved
EP2339622A1 (en) * 2009-12-23 2011-06-29 Nxp B.V. Wirebonding Process

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